Omap3.2 Operating System Timer; Dsp And Mpu Os Timer Start And Stop - Texas Instruments OMAP5912 Reference Manual

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OMAP3.2 Operating System Timer

Timer Block Diagram

There are six timers for the OS and general-purpose housekeeping functions

inside the hardware engine. Three are in the MPU subsystem (controlled by

the MPU), and the other three are controlled by the DSP. Figure 3 shows the

timer block diagram.

The functionality for all timers is identical, except the MPU timer interface to

the 32-bit MPU private TI peripheral bus (TIPB) and the DSP timer interface

to the 16-bit DSP private TIPB.

The timer is configured either in autoreload or in one-shot mode with on-the-fly

read capability. The timer generates an interrupt to the MPU or DSP when the

value is equal to zero.

TI peripheral bus interface

Timer control

Clock divider

An OS timer can be started by setting the ST bit of the DSP_CNTL_TIMER or

the MPU_CNTL_TIMER register. At start, the timers are loaded with the values

programmed to the DSP_LOAD_TIMER_HI, DSP_LOAD_TIMER_LO, and

MPU_LOAD_TIMER registers. The timer is stopped by resetting the ST bit.

When stopped, the timer value is frozen at the current value.

OMAP3.2 Operating System Timer

32-bit counter

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