Lvb And Lru Status Registers - Texas Instruments OMAP5912 Reference Manual

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½ Ramset Control Registers (RCR1, RCR2)

½ Ramset TAG Registers (RTR1, RTR2)

LVB and LRU Status Registers

Table 10. I-Cache LVB and LRU I/O Space Map

DSP Subsystem

When either the ½ ramset1..2 or TAG registers are written through

the TIPB bus in debug mode, this bit is set. This bit is reset to 0 if

this register is read in normal operation; it is not reset to 0 if this

When the two ½ ramset TAG registers are configured to be the

same address, I-cache sets this bit and returns a bus error to the

CPU. This bit is reset to 0 if this register is read in normal operation;

it is not reset to 0 if this register is read during emulation.

½ ramset enable mask:

0: ½ ramset n is not enabled when CAEN = 1.

1: ½ ramset n is enabled when CAEN = 1.

½ ramset flush mask:

0: ½ ramset n is not flushed when CACLR = 1.

1: ½ ramset n is flushed when CACLR = 1.

(All the line valid bits are invalidated; tag valid bit is invalidated).

Indicates that the ½ ramset fill has been completed and all of its line

valid bits are set:

1: ½ ramset fill has been completed.

0: ½ ramset fill has not started or not completed.

Byte address:

Because a ramset size is 4K bytes, the TAG field represents

PADDR (23:12).

The LRU bits of the two-way cache and the line valid bits of cache and ramsets

are readable through the TIPB bus. They are mapped to the I/O space, as

shown in Table 10.

Start Word Address

End Word Address

512 LVBs of bank0 = 32 words

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