Mpu 32-Bit Os Timers - Texas Instruments OMAP5912 Reference Manual

OMAP3.2 Operating System Timer
Table 23. DSP Read Timer Value, 1/2 MSW (DSP_READ_TIMER_HI)
Base Address = 0xE100 5000, 0xE100 5800, 0xE100 6000, Offset = 0x0A
Bit Name
15:0 DSP_READ_
TIMER_HI
3.7.2

MPU 32-Bit OS Timers

Table 24. MPU OS Timer Registers
Name
MPU_CNTL_TIMER
MPU_LOAD_TIMER
MPU_READ_TIMER
Table 25. MPU Control Timer Register (MPU_CNTL_TIMER)
Base Address = 0xFFFE C500, 0xFFFE C600, 0xFFFE C700, Offset = 0x00
Bit Name
31:7 RESERVED
6 FREE
28 Timers
Function
Value of the timer bits (31:16): To read correct
value for DSP 32-bit OS timer, this register must
be read first, followed by lower 16 bits of
DSP_READ_TIMER_LO.
Accesses to the MPU 32-bit OS timer configuration registers are controlled by
the MPU private TIPB.
Table 24 lists the MPU OS timer registers. Table 25 through Table 27 provide
register bit descriptions.
Base Address = 0xFFFE C500, 0xFFFE C600, 0xFFFE C700
Description
MPU control timer
MPU load timer
MPU read timer
Function
Specifies what action the timer takes upon
receiving a suspend indication from the TIPB
bridge. (For example, suspend is indicated if
processor execution has been suspended at an
emulation breakpoint.)
0: Stop counting on suspend indication (even when
ST = 1).
1: Suspend indication has no effect on the count.
R/W Reset
R Undefined
R/W Offset
R/W 0x00
W 0x04
W 0x08
R/W Reset
0x0000000
R/W 0
SPRU759B