Ulpd Interrupt Generation; Ulpd Registers - Texas Instruments OMAP5912 Reference Manual

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Ultralow-Power Device

ULPD Interrupt Generation

ULPD Registers

COUNTER_32_LSB_REG

COUNTER_32_MSB_REG

COUNTER_HIGH_FREQ_LSB_REG

COUNTER_HIGH_FREQ_MSB_REG

GAUGING_CTRL_REG

IT_STATUS_REG

SETUP_ANALOG_CELL3_ULPD1_REG

Power Management

The ULPD generates an interrupt when one of the following events has been

An overflow occurred on the 32-kHz counter during gauging. This event

is the same as the one that triggers the IT_STATUS_REG [2] bit.

An overflow occurred on the HI_FREQ counter during gauging versus

high frequency. This event is the same as the one that triggers the

IT_STATUS_REG [1] bit.

Gauging has stopped. This event is the same as the one that triggers the

IT_STATUS_REG [0] bit.

The following two conditions have been met:

USB_MCLK_REQ clock request has been set or SOFT_REQ_REG

[3] has been active high for more than two 32-kHz clock cycles.

CLOCK_CTRL_REG [5] is cleared to 0.

Table 7 lists the 16-bit ULPD registers. Table 8 through Table 39 describe the

Unless otherwise specified, all of the registers in this table are reset by any

warm reset (for a listing of warm resets, please see Chapter 5).

Base Address = 0xFFFE 0800

Counter 32 LSB

Counter 32 MSB

Counter high-frequency LSB

Counter high-frequency MSB

Gauging control

Interrupt status

Setup analog cell3 ULPD1

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