Flush I-Cache - Texas Instruments OMAP5912 Reference Manual

3.5.3

Flush I-Cache

SPRU750A
1) Set the GCR to have the following settings:
a) Global enable = 1
b) Way presence = 1
c) Way number = 00
d) ½ ramset presence = 1
e) ½ ramset number = 0000
f) Streaming = 1
g) Line_Fill_Mode = 1
2) Set the NWCR to have the following settings:
a) Way size = 011
b) Others = Don't care
3) Write 1 to CAEN bit in CPU ST3 register.
4) Query the I-CACHE_ENABLE bit in the I-cache status register to verify
that the cache is enabled.
5) Set the RTR1 to map to desired address space. For example, to load the
first 4K bytes starting from address 800000h, 0x0800h is loaded into
RTR1
The following sequence then occurs during ramset mode = 1.
1) The tag valid bit in the RCR is reset and the ramset is automatically
reinitialized/reloaded.
2) During ramset loading, CPU requests have lower priority than ramset fill
requests and are not serviced until the ramset is loaded. It is
recommended then for optimal performance to avoid external memory
accesses during ramset load operations. As each line of the ramset is
filled, the lVB of the line is set so that the progress of the ramset fill
operation can be monitored.
3) Once the ramset is filled, the tag valid bit in the RCR is set. This field can
be monitored for ramset load completion.
To flush the whole I-cache (invalidate all the line valid bits), you must:
1) Set the global flush bit in GCR.
DSP Memory
DSP Subsystem 35