Low-Dropout Voltage Regulator - Texas Instruments OMAP5912 Reference Manual

Low-Dropout Voltage Regulator

Table 6. Clock Timings
4 Low-Dropout Voltage Regulator
28 Clocks
Description
CLKREF duty cycle
Min CLKREF frequency
Max CLKREF frequency
Max CLKOUT frequency
LDO005 is a linear voltage regulator that supplies the OMAP3.2 DPLL macro.
This LDO uses peripheral supply input voltage to make the DPLL a quiet power
supply.
LDO005 contains:
-
Embedded voltage and current reference circuit
-
Adaptive biasing error amplifier as voltage regulator
-
Offset steady comparator
-
Initialization circuit to ensure local powerdown during VDD fast rampup
-
Level shifter
-
Bypass switch
The regulated supply is delivered to DPLL macros and is available on a unique
bond pad. (LDO005 is a complex I/O cell). A decoupling capacitor of 1 µF must
be connected externally between the pin of the cell and ground.
The LDO is bypassed when it is in power-down mode because the node VOUT
is in high-impedance mode. In this configuration, the DPLL circuit is supplied
from the pad (external power supply). To support this mode of operation, the
LDO is also in power-down mode after ramp-up of VDD, to avoid potential
contention between VDDS and VOUT.
The cell operates in sleep mode when sleep input is high. In this mode, VDD
is shorted to VOUT with a resistive switch, and the voltage regulator is kept in
power down. This mode retains the status in the registers of the DPLL macros
when they are in idle mode (they do not pull current from the power line).
Figure 6 shows the LDO005. Table 7 describes the pins.
Value Unit
From 40 to 60 %
2.5 MHz
50 MHz
250 MHz
SPRU751A