Ocp To Via Asynchronous Bridge - Texas Instruments OMAP5912 Reference Manual

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SSI Interconnect

DMA requests

Interupt requests

SYSTEM_RESET

SYSTEM_OCP_CLOCK

SYSTEM_SSR_CLOCK

OMAP5912_CONF

OCP to VIA Asynchronous Bridge

Clock and reset module

The clock and reset module manages clock and reset signals for the SSI

interconnect module and the SSI (SSR and SST) module. This module re-

synchronizes reset signals and implements the AUTOIDLE mechanism

for the SSI interconnect module.

Internal clock and reset signals

Clock and reset

OCP to the VIA asynchronous bridge is a connection bridge between an OCP

bus and a VIA bus. This submodule is a target on the OCP bus and a master

on the VIA bus. On the OCP, this bridge provides only basic functionality

signals plus SError (slave error). The slave error signal is needed because

only basic read and basic write transactions are supported.

Burst transactions are treated as a sequence of basic read and write accesses

and do not cause SError to be asserted. When unsupported commands occur,

SError is asserted.

SSI interconnect

asynchronous bridge

SSR status signals

SST status signals

synchronous bridge

Peripheral Interconnects

SSI Interconnect

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