Power-Up Sequence In External Clock Mode - Texas Instruments OMAP5912 Reference Manual

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Ultralow-Power Device

Power-up Sequence in Oscillator Mode

ANALOG_CELL_2_EN

ANALOG_CELL_3_EN

Power-up Sequence in External Clock Mode

Power Management

In external mode, all the analog cell setup counters are bypassed at power-up

It follows this sequence:

1) PWRON_RESET is released. LOW_PWR is reset to inactive state.

2) The input system clock is released internally in ULPD.

3) The ULPD FSM1 moves to awake mode.

4) The ULPD enables the input clock to OMAP3.2.

Glitch less latency mechanism

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