Accessing Watchdog Registers; Modifying Wcrr, Wldr, And Prescaler Ratios; Wcrr Access Restriction; Start/Stop Command - Texas Instruments OMAP5912 Reference Manual

1.6

Accessing Watchdog Registers

1.7

Modifying WCRR, WLDR, and Prescaler Ratios

1.8

WCRR Access Restriction

1.9

Start/Stop Command

SPRU759B
All registers are 32-bit wide, accessible via OCP interface with 16-bit or 32-bit
OCP access (read/write).
To modify the timer counter value (WCRR), prescaler ratio (PTV of WCLR), or
load value (WLDR), the 32-bit watchdog must be disabled by using a specific
start/stop sequence (WSPR).
In this case, the load register value and prescaler ratio are updated registers,
but new values are taken into account only after a new overflow context or a
new trigger command (WTGR).
Because the WCRR register is directly related to timer counter value and is
updated on the timer clock, a 32-bit shadow register is implemented to read
a coherent value of the WCRR.
The shadow register is updated by an 32-bit read command or an 16-bit LSB
read command. To be sure that a coherent value is read inside WCRR, use
32-bit reads, or, in case of 2 × 16-bit reads, be sure the least significant 16-bit
read is performed first (followed by the most significant 16-bit read).
To start/stop the 32-bit watchdog, access must be made through the start/stop
register (WSPR) using a specific sequence.
To disable the 32-bit watchdog, follow this sequence:
1) Write 0xXXXX AAAA in WSPR.
2) Write 0xXXXX 5555 in WSPR.
To enable the 32-bit watchdog, follow this sequence:
1) Write 0xXXXX BBBB in WSPR.
2) Write 0xXXXX 4444 in WSPR.
Other write sequences on WSPR do not have any effect on the start/stop
feature of the module.
32-Bit Watchdog Timer General Overview
Timers 13