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Texas Instruments AM1808 Manuals
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Texas Instruments AM1808 manuals available for free PDF download: Technical Reference Manual, User Manual
Texas Instruments AM1808 Technical Reference Manual (1820 pages)
Sitara ARM Microprocessor
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 10.39 MB
Table of Contents
Am1808/Am1810 Sitara Arm Microprocessor Technical Reference Manual
2
Table of Contents
2
Table of Contents
58
67
Preface
80
1 Overview
81
Introduction
82
ARM Subsystem
82
AM1808/AM1810 ARM Microprocessor Block Diagram
82
2 ARM Subsystem
83
Introduction
84
Operating States/Modes
85
Processor Status Registers
85
Exceptions and Exception Vectors
86
Exception Vector Table for ARM
86
The 16-BIS/32-BIS Concept
87
16-BIS/32-BIS Advantages
87
Co-Processor 15 (CP15)
88
Addresses in an ARM926EJ-S System
88
Memory Management Unit (MMU)
88
Different Address Types in ARM System
88
Caches and Write Buffer
89
3 System Interconnect
90
Introduction
91
AM1808/AM1810 ARM Microprocessor System Interconnect Matrix
91
System Interconnect Block Diagram
92
4 System Memory
93
Introduction
94
ARM Memories
94
Peripherals
94
5 Memory Protection Unit (MPU)
95
Introduction
96
Block Diagram
96
Features
96
Purpose of the MPU
96
MPU Block Diagram
96
Architecture
97
MPU Default Configuration
97
MPU Memory Regions
97
Privilege Levels
97
Device Master Settings
98
Memory Protection Ranges
98
Permission Structures
99
Permission Fields
99
Request Type Access Controls
99
Invalid Accesses and Exceptions
100
MPU Register Protection
100
Protection Check
100
Reset Considerations
100
Emulation Considerations
101
Interrupt Support
101
MPU_BOOTCFG_ERR Interrupt Sources
101
Memory Protection Unit 1 (MPU1) Registers
102
Memory Protection Unit 2 (MPU2) Registers
102
MPU Registers
102
Configuration Register (CONFIG)
104
Revision Identification Register (REVID)
104
Revision ID Register (REVID)
104
Configuration Register (CONFIG) Field Descriptions
104
Revision ID Register (REVID) Field Descriptions
104
Interrupt Raw Status/Set Register (IRAWSTAT)
105
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
105
Interrupt Enable Status/Clear Register (IENSTAT)
106
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
106
Interrupt Enable Set Register (IENSET)
107
Interrupt Enable Clear Register (IENCLR)
107
Interrupt Enable Clear Register (IENCLR) Field Descriptions
107
Interrupt Enable Set Register (IENSET) Field Descriptions
107
Fixed Range End Address Register (FXD_MPEAR)
108
Fixed Range Start Address Register (FXD_MPSAR)
108
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
109
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions
109
Programmable Range N Start Address Registers (Progn_Mpsar)
110
MPU1 Programmable Range N Start Address Register (Progn_Mpsar)
110
MPU2 Programmable Range N Start Address Register (Progn_Mpsar)
110
MPU1 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions
110
MPU2 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions
110
Programmable Range N End Address Registers (Progn_Mpear)
111
MPU1 Programmable Range N End Address Register (Progn_Mpear)
111
MPU2 Programmable Range N End Address Register (Progn_Mpear)
111
MPU1 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions
111
MPU2 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions
111
Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
112
Programmable Range Memory Protection Page Attributes Register (Progn_Mppa)
112
Programmable Range Memory Protection Page Attributes Register (Progn_Mppa) Field Descriptions
112
Fault Address Register (FLTADDRR)
113
Fault Address Register (FLTADDRR) Field Descriptions
113
Fault Status Register (FLTSTAT)
114
Fault Status Register (FLTSTAT) Field Descriptions
114
Fault Clear Register (FLTCLR)
115
Fault Clear Register (FLTCLR) Field Descriptions
115
6 Device Clocking
116
Overview
117
Device Clock Inputs
117
System Clock Domains
117
Overall Clocking Diagram
118
Frequency Flexibility
119
Example PLL Frequencies
120
Peripheral Clocking
120
USB Clocking
120
USB Clocking Diagram
121
USB Clock Multiplexing Options
121
Ddr2/Mddr Memory Controller Clocking
122
Ddr2/Mddr Memory Controller Clocking Diagram
123
Ddr2/Mddr Memory Controller MCLK Frequencies
123
EMIFA Clocking
124
EMIFA Clocking Diagram
124
EMIFA Frequencies
124
EMAC Clocking
125
EMAC Clocking Diagram
125
EMAC Reference Clock Frequencies
126
Upp Clocking
127
Upp Clocking Diagram
127
Upp Transmit Clock Selection
127
Mcasp Clocking
128
Mcasp Clocking Diagram
128
I/O Domains
129
Peripherals
129
7 Phase-Locked Loop Controller (PLLC)
130
Introduction
131
PLL Controllers
131
PLLC Structure
132
Device Clock Generation
133
System PLLC Output Clocks
133
Steps for Programming the Plls
134
PLL Controller 0 (PLLC0) Registers
136
PLLC Registers
136
PLL Controller 1 (PLLC1) Registers
137
PLLC0 Revision Identification Register (REVID)
137
PLLC0 Revision Identification Register (REVID) Field Descriptions
137
PLLC1 Revision Identification Register (REVID)
138
PLLC1 Revision Identification Register (REVID) Field Descriptions
138
Reset Type Status Register (RSTYPE)
138
Reset Type Status Register (RSTYPE) Field Descriptions
138
PLLC0 Reset Control Register (RSCTRL)
139
Reset Control Register (RSCTRL)
139
Reset Control Register (RSCTRL) Field Descriptions
139
PLLC0 Control Register (PLLCTL)
140
PLLC0 Control Register (PLLCTL) Field Descriptions
140
PLLC1 Control Register (PLLCTL)
141
PLLC1 Control Register (PLLCTL) Field Descriptions
141
PLLC0 OBSCLK Select Register (OCSEL)
142
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
142
PLLC1 OBSCLK Select Register (OCSEL)
143
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
143
PLL Multiplier Control Register (PLLM)
144
PLL Multiplier Control Register (PLLM) Field Descriptions
144
PLLC0 Pre-Divider Control Register (PREDIV)
144
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
144
PLLC0 Divider 1 Register (PLLDIV1)
145
PLLC1 Divider 1 Register (PLLDIV1)
145
PLLC0 Divider 2 Register (PLLDIV2)
146
PLLC1 Divider 2 Register (PLLDIV2)
146
PLLC0 Divider 3 Register (PLLDIV3)
147
PLLC1 Divider 3 Register (PLLDIV3)
147
PLLC0 Divider 4 Register (PLLDIV4)
148
PLLC0 Divider 5 Register (PLLDIV5)
148
PLLC0 Divider 6 Register (PLLDIV6)
149
PLLC0 Divider 7 Register (PLLDIV7)
149
PLLC0 Oscillator Divider 1 Register (OSCDIV)
150
PLLC1 Oscillator Divider 1 Register (OSCDIV)
150
PLL Post-Divider Control Register (POSTDIV)
151
PLL Controller Command Register (PLLCMD)
151
PLL Controller Status Register (PLLSTAT)
152
PLLC0 Clock Align Control Register (ALNCTL)
153
PLLC1 Clock Align Control Register (ALNCTL)
154
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
155
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
156
PLLC0 Clock Enable Control Register (CKEN)
157
PLLC1 Clock Enable Control Register (CKEN)
157
PLLC0 Clock Status Register (CKSTAT)
158
PLLC1 Clock Status Register (CKSTAT)
159
PLLC0 SYSCLK Status Register (SYSTAT)
160
PLLC1 SYSCLK Status Register (SYSTAT)
161
Emulation Performance Counter 0 Register (EMUCNT0)
162
Emulation Performance Counter 1 Register (EMUCNT1)
162
8 Power and Sleep Controller (PSC)
163
Introduction
164
Power Domain and Module Topology
164
PSC0 Default Module Configuration
165
Power Domain States
166
Module States
167
Module States
168
Executing State Transitions
169
Module State Transitions
169
Power Domain State Transitions
169
Icepick Emulation Support in the PSC
170
Interrupt Events
170
PSC Interrupts
170
Interrupt Registers
171
Interrupt Handling
172
PSC Registers
173
Interrupt Evaluation Register (INTEVAL)
174
Revision Identification Register (REVID)
174
PSC0 Module Error Pending Register 0 (Modules 0-15) (MERRPR0)
175
PSC1 Module Error Pending Register 0 (Modules 0-31) (MERRPR0)
175
PSC0 Module Error Pending Register 0 (MERRPR0)
175
PSC1 Module Error Pending Register 0 (MERRPR0)
175
PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0)
176
PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0)
176
PSC0 Module Error Clear Register 0 (MERRCR0)
176
PSC1 Module Error Clear Register 0 (MERRCR0)
176
Power Error Clear Register (PERRCR)
177
Power Error Pending Register (PERRPR)
177
Power Domain Transition Command Register (PTCMD)
178
Power Domain Transition Status Register (PTSTAT)
179
Power Domain 0 Status Register (PDSTAT0)
180
Power Domain 1 Status Register (PDSTAT1)
181
Power Domain 0 Control Register (PDCTL0)
182
Power Domain 1 Control Register (PDCTL1)
183
Power Domain 0 Configuration Register (PDCFG0)
184
Power Domain 1 Configuration Register (PDCFG1)
185
Module Status N Register (Mdstatn)
186
PSC0 Module Control N Register (Modules 0-15) (Mdctln)
187
PSC0 Module Control N Register (Mdctln)
187
PSC1 Module Control N Register (Modules 0-31) (Mdctln)
188
PSC1 Module Control N Register (Mdctln)
188
9 Power Management
189
Introduction
190
Power Consumption Overview
190
PSC and PLLC Overview
190
Features
191
Clock Management
192
Module Clock Frequency Scaling
192
Module Clock ON/OFF
192
PLL Bypass and Power down
192
ARM Sleep Mode Management
193
ARM Wait-For-Interrupt Sleep Mode
193
ARM Clock off
194
ARM Subsystem Clock on
194
RTC-Only Mode
195
Dynamic Voltage and Frequency Scaling (DVFS)
195
Frequency Scaling Considerations
195
Voltage Scaling Considerations
196
Deep Sleep Mode
196
Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
197
Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
198
Deep Sleep Sequence
199
Deep Sleep Mode Sequence
199
Additional Peripheral Power Management Considerations
200
Entering/Exiting Deep Sleep Mode Using Software Handshaking
200
USB PHY Power down Control
200
Ddr2/Mddr Memory Controller Clock Gating and Self-Refresh Mode
201
LVCMOS I/O Buffer Receiver Disable
201
SATA PHY Power down
201
Pull-Up/Pull-Down Disable
202
10 System Configuration (SYSCFG) Module
203
Introduction
204
Protection
204
Privilege Mode Protection
204
Kicker Mechanism Protection
205
Master Priority Control
205
Default Master Priority
206
Interrupt Events and Requests
207
Interrupt Multiplexing
207
Interrupt Support
207
SYSCFG Registers
207
System Configuration Module 1 (SYSCFG1) Registers
208
Device Identification Register 0 (DEVIDR0)
209
Revision Identification Register (REVID)
209
Boot Configuration Register (BOOTCFG)
210
Chip Revision Identification Register (CHIPREVIDR)
210
Kick Registers (KICK0R-KICK1R)
211
Kick 0 Register (KICK0R)
211
Kick 1 Register (KICK1R)
211
Host 0 Configuration Register (HOST0CFG)
212
Interrupt Raw Status/Set Register (IRAWSTAT)
213
Interrupt Registers
213
Interrupt Enable Status/Clear Register (IENSTAT)
214
Interrupt Enable Register (IENSET)
215
Interrupt Enable Clear Register (IENCLR)
215
Fault Registers
216
End of Interrupt Register (EOI)
216
Fault Address Register (FLTADDRR)
216
Fault Status Register (FLTSTAT)
217
Master Priority Registers (MSTPRI0-MSTPRI2)
218
Master Priority 0 Register (MSTPRI0)
218
Master Priority 1 Register (MSTPRI1)
219
Master Priority 2 Register (MSTPRI2)
220
Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
221
Pin Multiplexing Control 0 Register (PINMUX0)
221
Pin Multiplexing Control 1 Register (PINMUX1)
223
Pin Multiplexing Control 2 Register (PINMUX2)
225
Pin Multiplexing Control 3 Register (PINMUX3)
227
Pin Multiplexing Control 4 Register (PINMUX4)
229
Pin Multiplexing Control 5 Register (PINMUX5)
231
Pin Multiplexing Control 6 Register (PINMUX6)
233
Pin Multiplexing Control 7 Register (PINMUX7)
235
Pin Multiplexing Control 8 Register (PINMUX8)
237
Pin Multiplexing Control 9 Register (PINMUX9)
239
Pin Multiplexing Control 10 Register (PINMUX10)
241
Pin Multiplexing Control 11 Register (PINMUX11)
243
Pin Multiplexing Control 12 Register (PINMUX12)
245
Pin Multiplexing Control 13 Register (PINMUX13)
247
Pin Multiplexing Control 14 Register (PINMUX14)
249
Pin Multiplexing Control 15 Register (PINMUX15)
251
Pin Multiplexing Control 16 Register (PINMUX16)
254
Pin Multiplexing Control 17 Register (PINMUX17)
256
Pin Multiplexing Control 18 Register (PINMUX18)
258
Pin Multiplexing Control 19 Register (PINMUX19)
260
Suspend Source Register (SUSPSRC)
262
Chip Signal Register (CHIPSIG)
265
Chip Signal Clear Register (CHIPSIG_CLR)
266
Chip Configuration 0 Register (CFGCHIP0)
267
Chip Configuration 1 Register (CFGCHIP1)
268
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
269
Chip Configuration 2 Register (CFGCHIP2)
271
Chip Configuration 3 Register (CFGCHIP3)
273
Chip Configuration 4 Register (CFGCHIP4)
274
VTP I/O Control Register (VTPIO_CTL)
275
DDR Slew Register (DDR_SLEW)
277
Deep Sleep Register (DEEPSLEEP)
278
Pullup/Pulldown Enable Register (PUPD_ENA)
279
Pullup/Pulldown Select Register (PUPD_SEL)
279
Pullup/Pulldown Select Register (PUPD_SEL) Default Values
280
RXACTIVE Control Register (RXACTIVE)
281
Power down Control Register (PWRDN)
281
ARM Interrupt Controller (AINTC)
282
AINTC Interrupt Mapping
283
Introduction
283
AINTC System Interrupt Assignments
284
Flow of System Interrupts to Host
286
AINTC Methodology
286
Interrupt Enabling
287
Interrupt Prioritization
288
Interrupt Vectorization
289
Interrupt Status Clearing
290
Revision Identification Register (REVID)
291
Control Register (CR)
292
Global Enable Register (GER)
293
Global Nesting Level Register (GNLR)
293
System Interrupt Status Indexed Set Register (SISR)
294
System Interrupt Status Indexed Clear Register (SICR)
294
System Interrupt Enable Indexed Set Register (EISR)
295
System Interrupt Enable Indexed Clear Register (EICR)
295
Host Interrupt Enable Indexed Set Register (HEISR)
296
Host Interrupt Enable Indexed Clear Register (HIEICR)
296
Vector Base Register (VBR)
297
Vector Size Register (VSR)
297
Vector Null Register (VNR)
298
Global Prioritized Index Register (GPIR)
298
Global Prioritized Vector Register (GPVR)
299
System Interrupt Status Raw/Set Register 1 (SRSR1)
299
System Interrupt Status Raw/Set Register 2 (SRSR2)
300
System Interrupt Status Raw/Set Register 3 (SRSR3)
300
System Interrupt Status Raw/Set Register 4 (SRSR4)
301
System Interrupt Status Enabled/Clear Register 1 (SECR1)
301
System Interrupt Status Enabled/Clear Register 2 (SECR2)
302
System Interrupt Status Enabled/Clear Register 3 (SECR3)
302
System Interrupt Status Enabled/Clear Register 4 (SECR4)
303
System Interrupt Enable Set Register 1 (ESR1)
303
System Interrupt Enable Set Register 2 (ESR2)
304
System Interrupt Enable Set Register 3 (ESR3)
304
System Interrupt Enable Set Register 4 (ESR4)
305
System Interrupt Enable Clear Register 1 (ECR1)
305
System Interrupt Enable Clear Register 2 (ECR2)
306
System Interrupt Enable Clear Register 3 (ECR3)
306
System Interrupt Enable Clear Register 4 (ECR4)
307
Channel Map Registers (Cmrn)
307
Host Interrupt Prioritized Index Register 1 (HIPIR1)
308
Host Interrupt Prioritized Index Register 2 (HIPIR2)
308
Host Interrupt Nesting Level Register 1 (HINLR1)
309
Host Interrupt Nesting Level Register 2 (HINLR2)
309
Host Interrupt Enable Register (HIER)
310
Host Interrupt Enable Register (HIER) Field Descriptions
310
Host Interrupt Prioritized Vector Register 1 (HIPVR1)
311
Host Interrupt Prioritized Vector Register 2 (HIPVR2)
311
Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions
311
Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions
311
12 Boot Considerations
312
Introduction
313
13 Programmable Real-Time Unit Subsystem (PRUSS)
314
Overview
315
Description
317
PRU Block Diagram
317
Constants Table
318
Event out Mapping (R31): PRU System Events
319
General Purpose Inputs (R31)
319
General Purpose Outputs (R30)
319
PRU Module Interface
319
Status Mapping (R31): Interrupt Events Input
319
Instruction Set
320
Abbreviations for Instruction Descriptions
320
Load/Store Instructions
320
Arithmetic Instructions
320
Logical Instructions
321
Program Flow Control Instructions
322
Instruction Formats
323
Format 1A: (All Arithmetic and Logical Functions - Register Op2)
323
Format 1B: (All Arithmetic and Logical Functions - Immediate Op2)
325
Format 2
326
Format 2A: (JMP,JAL - Register Op2)
327
Format 2B: (JMP, JAL - Immediate Op2)
328
Format 2C: (LDI)
329
Format 2D: (LMBD - Leftmost Bit Detect - Register Op2)
330
Format 2E: (LMBD - Immediate Op2)
331
Format 2F: (SCAN - Register Op2)
332
Format 2G: (SCAN - Immediate Op2)
333
Format 2H: (HALT)
333
Format 2I: (SLP)
333
Format 4A: (Quick Arithmetic Test and Branch - Register Op2)
334
Format 4B: (Quick Arithmetic Test and Branch - Immediate Op2)
335
Format 5A: (Quick Bit Test and Branch - Register Op2)
336
Format 5B: (Quick Bit Test and Branch - Immediate Op2)
337
Format 6A: (LBBO/SBBO - Register Offset)
338
Format 6B: (LBBO/SBBO - Immediate Offset)
339
Format 6C: (LBCO/SBCO - Register Offset)
340
Interrupt Mapping
341
Introduction
341
PRU Interrupt Controller
341
Format 6D: (LBCO/SBCO - Immediate Offset)
341
PRUSS System Events
342
PRUSS System Events [0:31] Assignments
343
ARM and DSP Interrupt Controller Mapping
344
ARM Interrupt Controller Mapping
344
DSP Interrupt Controller Mapping
344
INTC Methodology
345
Registers
348
PRUSS Memory Map
349
Local Instruction Space Memory Map
349
Local Data Space Memory Map
349
Subsystem Global Memory Map
349
CONTROL Register
350
PRU Control/Status Register Memory Map
350
CONTROL Register Field Descriptions
350
STATUS Register
352
WAKEUP Register
352
CYCLECNT Register
352
STATUS Register Field Descriptions
352
WAKEUP Register Field Descriptions
352
STALLCNT Register
353
CONTABBLKIDX0 Register
353
CYCLECNT Register Field Descriptions
353
STALLCNT Register Field Descriptions
353
CONTABPROPTR0 Register
354
CONTABPROPTR1 Register
354
CONTABBLKIDX0 Register Field Descriptions
354
CONTABPROPTR0 Register Field Descriptions
354
CONTABPROPTR1 Register Field Descriptions
354
INTGPR0 to INTGPR31 Register
355
INTCTER0 to INTCTER31 Register
355
INTGPR0 to INTGPR31 Register Field Descriptions
355
INTCTER0 to INTCTER31 Register Field Descriptions
355
INTC Registers
356
Instruction RAM Memory Region
356
PRUSS Interrupt Controller (INTC) Registers
356
REVID Register
357
GLBLEN Register Field Descriptions
358
STATIDXCLR Register
359
HSTINTENIDXSET Register
360
STATESETINT0 Register
361
STATCLRINT1 Register
362
ENABLECLR0 Register
363
HOSTMAP0 to HOSTMAP2 Register
364
TYPE1 Register
365
POLARITY0 Register Field Descriptions
365
TYPE1 Register Field Descriptions
366
HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register
366
HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register Field Descriptions
366
HOSTINTEN Register
366
HOSTINTEN Register Field Descriptions
366
14 Ddr2/Mddr Memory Controller
367
Introduction
368
Features
368
Purpose of the Peripheral
368
Functional Block Diagram
369
Industry Standard(S) Compliance Statement
369
Supported Use Case Statement
369
Data Paths to Ddr2/Mddr Memory Controller
369
Architecture
370
Clock Control
370
Ddr2/Mddr Memory Controller Clock Block Diagram
370
Signal Descriptions
371
Ddr2/Mddr Memory Controller Signals
371
Protocol Description(S)
372
Ddr2/Mddr SDRAM Commands
372
Truth Table for Ddr2/Mddr SDRAM Commands
373
Refresh Command
374
DCAB Command
375
DEAC Command
376
ACTV Command
377
Ddr2/Mddr READ Command
378
Ddr2/Mddr WRT Command
379
Memory Width and Byte Alignment
380
Ddr2/Mddr MRS and EMRS Command
380
Byte Alignment
380
Addressable Memory Ranges
380
Address Mapping
381
Configuration Register Fields for Address Mapping
381
Logical Address-To-Ddr2/Mddr SDRAM Address Map for 16-Bit SDRAM
382
Ddr2/Mddr SDRAM Column, Row, and Bank Access
384
Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1)
384
Address Mapping Diagram (IBANKPOS = 1)
385
Ddr2/Mddr Memory Controller Interface
386
SDRAM Column, Row, Bank Access (IBANKPOS = 1)
386
Ddr2/Mddr Memory Controller FIFO Description
386
Ddr2/Mddr Memory Controller FIFO Block Diagram
387
Refresh Scheduling
389
Self-Refresh Mode
389
Refresh Urgency Levels
389
Partial Array Self Refresh for Mobile DDR
390
Power-Down Mode
390
Configuration Bit Field for Partial Array Self-Refresh
390
Reset Considerations
391
Ddr2/Mddr Memory Controller Reset Block Diagram
391
Reset Sources
391
Auto-Initialization Sequence
392
VTP IO Buffer Calibration
392
DDR2 SDRAM Configuration by MRS Command
393
DDR2 SDRAM Configuration by EMRS(1) Command
393
Mobile DDR SDRAM Configuration by MRS Command
393
Mobile DDR SDRAM Configuration by EMRS(1) Command
394
DMA Event Support
395
Interrupt Support
395
Power Management
396
Ddr2/Mddr Memory Controller Power Sleep Controller Diagram
396
Emulation Considerations
397
Supported Use Cases
398
Connecting Ddr2/Mddr Memory Controller to a 16-Bit DDR2 Memory
398
SDCR Configuration
399
DDR2 Memory Refresh Specification
400
SDRCR Configuration
400
SDTIMR1 Configuration
401
SDTIMR2 Configuration
401
DRPYC1R Configuration
402
Registers
403
Revision ID Register (REVID)
403
Ddr2/Mddr Memory Controller Registers
403
Revision ID Register (REVID) Field Descriptions
403
SDRAM Status Register (SDRSTAT)
404
SDRAM Status Register (SDRSTAT) Field Descriptions
404
SDRAM Configuration Register (SDCR)
405
SPRUH82C - April 2013 - Revised September 2016
405
Submit Documentation Feedback
405
SDRAM Configuration Register (SDCR) Field Descriptions
405
SDRAM Refresh Control Register (SDRCR)
408
SDRAM Refresh Control Register (SDRCR) Field Descriptions
408
SDRAM Timing Register 1 (SDTIMR1)
409
SDRAM Timing Register 1 (SDTIMR1) Field Descriptions
409
SDRAM Timing Register 2 (SDTIMR2)
410
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
410
SDRAM Configuration Register 2 (SDCR2)
411
SDRAM Configuration Register 2 (SDCR2) Field Descriptions
411
Peripheral Bus Burst Priority Register (PBBPR)
412
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
412
Performance Counter 1 Register (PC1)
413
Performance Counter 2 Register (PC2)
413
Performance Counter 1 Register (PC1) Field Descriptions
413
Performance Counter 2 Register (PC2) Field Descriptions
413
Performance Counter Configuration Register (PCC)
414
Performance Counter Configuration Register (PCC) Field Descriptions
414
Performance Counter Filter Configuration
415
Performance Counter Master Region Select Register (PCMRS)
416
Performance Counter Master Region Select Register (PCMRS) Field Descriptions
416
DDR PHY Reset Control Register (DRPYRCR)
417
Performance Counter Time Register (PCT)
417
Performance Counter Time Register (PCT) Field Description
417
Interrupt Masked Register (IMR)
418
Interrupt Raw Register (IRR)
418
Interrupt Raw Register (IRR) Field Descriptions
418
Interrupt Masked Register (IMR) Field Descriptions
418
Interrupt Mask Set Register (IMSR)
419
Interrupt Mask Set Register (IMSR) Field Descriptions
419
Interrupt Mask Clear Register (IMCR)
420
Interrupt Mask Clear Register (IMCR) Field Descriptions
420
DDR PHY Control Register (DRPYC1R)
421
DDR PHY Control Register 1 (DRPYC1R)
421
DDR PHY Control Register 1 (DRPYC1R) Field Descriptions
421
15 Enhanced Capture (Ecap) Module
422
Introduction
423
Features
423
Purpose of the Peripheral
423
Architecture
424
Multiple Ecap Modules
424
Capture and APWM Operating Mode
425
Capture and APWM Modes of Operation
425
Capture Mode Description
426
Capture Function Diagram
426
Event Prescale Control
427
Prescale Function Waveforms
427
Continuous/One-Shot Block Diagram
428
Counter and Synchronization Block Diagram
429
Interrupts in Ecap Module
431
PWM Waveform Details of APWM Mode Operation
432
Applications
433
Absolute Time-Stamp Operation Rising Edge Trigger Example
434
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
434
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
435
Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
436
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
436
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
437
Time Difference (Delta) Operation Rising Edge Trigger Example
438
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
438
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
439
Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
440
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
440
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
441
Application of the APWM Mode
442
PWM Waveform Details of APWM Mode Operation
442
ECAP Initialization for APWM Mode
443
Multichannel PWM Example Using 4 Ecap Modules
444
ECAP1 Initialization for Multichannel PWM Generation with Synchronization
445
Multiphase (Channel) Interleaved PWM Example Using 3 Ecap Modules
447
ECAP1 Initialization for Multichannel PWM Generation with Phase Control
448
Registers
449
Time-Stamp Counter Register (TSCTR)
449
Capture 1 Register (CAP1)
450
Counter Phase Control Register (CTRPHS)
450
Capture 2 Register (CAP2)
451
Capture 3 Register (CAP3)
451
Capture 4 Register (CAP4)
452
ECAP Control Register 1 (ECCTL1)
452
ECAP Control Register 2 (ECCTL2)
454
ECAP Interrupt Enable Register (ECEINT)
455
ECAP Interrupt Enable Register (ECEINT)
456
ECAP Interrupt Flag Register (ECFLG)
457
ECAP Interrupt Clear Register (ECCLR)
458
ECAP Interrupt Forcing Register (ECFRC)
459
Revision ID Register (REVID)
460
16 Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
461
Introduction
462
Submodule Overview
462
Multiple Epwm Modules
463
Submodules and Signal Connections for an Epwm Module
464
Epwm Submodules and Critical Internal Signal Interconnects
465
Register Mapping
466
Architecture
467
Overview
467
Proper Interrupt Initialization Procedure
470
Time-Base (TB) Submodule
471
Time-Base Submodule Block Diagram
471
Time-Base Submodule Signals and Registers
472
Key Time-Base Signals
473
Time-Base Frequency and Period
474
Time-Base Counter Synchronization Scheme 1
475
Time-Base Up-Count Mode Waveforms
477
Time-Base Down-Count Mode Waveforms
478
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
478
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
479
Counter-Compare (CC) Submodule
480
Counter-Compare Submodule
480
Counter-Compare Submodule Signals and Registers
480
Counter-Compare Submodule Registers
481
Counter-Compare Event Waveforms in Up-Count Mode
483
Counter-Compare Events in Down-Count Mode
483
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
484
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
484
Action-Qualifier (AQ) Submodule
485
Action-Qualifier Submodule
485
Action-Qualifier Submodule Inputs and Outputs
486
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
487
Action-Qualifier Event Priority for Up-Down-Count Mode
488
Behavior if CMPA/CMPB Is Greater than the Period
489
Up-Down-Count Mode Symmetrical Waveform
490
Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
491
Epwmx Initialization for
492
Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
493
Epwmx Initialization for
494
Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
495
Epwmx Initialization for
496
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
497
Epwmx Initialization for
498
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary
499
Epwmx Initialization for
500
Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
501
Epwmx Initialization for
502
Dead-Band Generator (DB) Submodule
503
Dead-Band Generator Submodule
503
Configuration Options for the Dead-Band Generator Submodule
504
Classical Dead-Band Operating Modes
505
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
506
PWM-Chopper (PC) Submodule
507
PWM-Chopper Submodule
507
PWM-Chopper Submodule Signals and Registers
508
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
509
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
509
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
510
Trip-Zone (TZ) Submodule
511
Trip-Zone Submodule
511
Trip-Zone Submodule Registers
512
Possible Actions on a Trip Event
513
Trip-Zone Submodule Mode Control Logic
514
Trip-Zone Submodule Interrupt Logic
514
Event-Trigger (ET) Submodule
515
Event-Trigger Submodule
515
Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
516
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
516
Event-Trigger Interrupt Generator
518
High-Resolution PWM (HRPWM) Submodule
519
HRPWM System Interface
519
Resolution Calculations for Conventionally Generated PWM
520
Operating Logic Using MEP
521
Relationship between MEP Steps, PWM Frequency and Resolution
522
Required PWM Waveform for a Requested Duty
523
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
525
High % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
525
Applications to Power Topologies
526
Overview of Multiple Modules
526
Simplified Epwm Module
526
Key Configuration Capabilities
527
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
527
Controlling Multiple Buck Converters with Independent Frequencies
528
Control of Four Buck Stages
528
Pwm1 Pwm2 Pwm3 Pwm4
528
Buck Waveforms for (Note: Only Three Bucks Shown Here)
529
Buck Waveforms for
529
EPWM1 Initialization for
530
Controlling Multiple Buck Converters with same Frequencies
531
Control of Four Buck Stages
531
Pwm1 )
531
Pwm2 Pwm1
532
EPWM1 Initialization for
533
Controlling Multiple Half H-Bridge (HHB) Converters
534
Pwm1 )
534
Pwm2 Pwm1
535
EPWM1 Initialization for
536
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
537
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
537
3-Phase Inverter Waveforms for (Only One Inverter Shown)
538
EPWM1 Initialization for
539
EPWM3 Initialization for
540
Practical Applications Using Phase Control between PWM Modules
541
Configuring Two PWM Modules for Phase Control
541
Controlling a 3-Phase Interleaved DC/DC Converter
542
Timing Waveforms Associated with Phase Control between 2 Modules
542
Control of a 3-Phase Interleaved DC/DC Converter
543
3-Phase Interleaved DC/DC Converter Waveforms for
544
EPWM1 Initialization for
545
EPWM3 Initialization for
546
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
547
Pwm2 Pwm1
547
ZVS Full-H Bridge Waveforms
548
EPWM1 Initialization for
549
Registers
550
Time-Base Submodule Registers
550
Time-Base Control Register (TBCTL)
550
Time-Base Control Register (TBCTL) Field Descriptions
551
Time-Base Status Register (TBSTS)
552
Time-Base Phase Register (TBPHS)
553
Time-Base Counter Register (TBCNT)
553
Counter-Compare Submodule Registers
554
Time-Base Period Register (TBPRD)
554
Counter-Compare Control Register (CMPCTL)
555
Counter-Compare a Register (CMPA)
556
Action-Qualifier Submodule Registers
557
Counter-Compare B Register (CMPB)
557
Action-Qualifier Output a Control Register (AQCTLA)
558
Action-Qualifier Output B Control Register (AQCTLB)
559
Action-Qualifier Software Force Register (AQSFRC)
560
Dead-Band Generator Submodule Registers
561
Action-Qualifier Continuous Software Force Register (AQCSFRC)
561
Dead-Band Generator Control Register (DBCTL)
562
Dead-Band Generator Rising Edge Delay Register (DBRED)
563
Dead-Band Generator Falling Edge Delay Register (DBFED)
563
PWM-Chopper Submodule Register
564
PWM-Chopper Control Register (PCCTL)
564
Trip-Zone Submodule Registers
565
Trip-Zone Select Register (TZSEL)
565
Trip-Zone Control Register (TZCTL)
566
Trip-Zone Enable Interrupt Register (TZEINT)
566
Trip-Zone Flag Register (TZFLG)
567
Trip-Zone Clear Register (TZCLR)
568
Trip-Zone Force Register (TZFRC)
568
Event-Trigger Submodule Registers
569
Event-Trigger Selection Register (ETSEL)
569
Event-Trigger Prescale Register (ETPS)
570
Event-Trigger Flag Register (ETFLG)
571
Event-Trigger Clear Register (ETCLR)
571
High-Resolution PWM Submodule Registers
572
Event-Trigger Force Register (ETFRC)
572
Time-Base Phase High-Resolution Register (TBPHSHR)
573
Counter-Compare a High-Resolution Register (CMPAHR)
573
HRPWM Configuration Register (HRCNFG)
574
17 Enhanced Direct Memory Access (EDMA3) Controller
575
Introduction
576
Features
576
Overview
576
Functional Block Diagram
579
Terminology Used in this Document
579
EDMA3 Controller Block Diagram
579
Architecture
581
Functional Overview
581
EDMA3 Channel Controller (EDMA3CC) Block Diagram
582
EDMA3 Transfer Controller (EDMA3TC) Block Diagram
583
Types of EDMA3 Transfers
584
Definition of ACNT, BCNT, and CCNT
584
A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
585
AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
586
Parameter RAM (Param)
587
Param Set
587
EDMA3 Channel Parameter Description
588
Dummy and Null Transfer Request
591
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)
592
Linked Transfer Example
595
Link-To-Self Transfer Example
596
Initiating a DMA Transfer
597
Completion of a DMA Transfer
600
Event, Channel, and Param Mapping
601
EDMA3 DMA Channel to Param Mapping
602
QDMA Channel to Param Mapping
603
EDMA3 Channel Controller Regions
604
Shadow Region Registers
605
Chaining EDMA3 Channels
606
EDMA3 Interrupts
606
EDMA3 Transfer Completion Interrupts
607
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
608
Interrupt Diagram
609
Error Interrupt Operation
612
Event Queue(S)
613
EDMA3 Transfer Controller (EDMA3TC)
615
Event Dataflow
618
EDMA3 Prioritization
619
EDMA3CC and EDMA3TC Performance and System Considerations
621
EDMA3 Operating Frequency (Clock Control)
622
Power Management
622
Reset Considerations
622
Block Move Example
623
Emulation Considerations
623
Transfer Examples
623
Block Move Example Param Configuration
624
Subframe Extraction Example
625
Subframe Extraction Example Param Configuration
625
Data Sorting Example
626
Data Sorting Example Param Configuration
627
Peripheral Servicing Example
628
Servicing Incoming Mcbsp Data Example
628
Servicing Incoming Mcbsp Data Example Param
629
Servicing Peripheral Burst Example
630
Servicing Peripheral Burst Example Param
630
Servicing Continuous Mcbsp Data Example
631
Servicing Continuous Mcbsp Data Example Param
632
Servicing Continuous Mcbsp Data Example Reload Param
632
Ping-Pong Buffering for Mcbsp Data Example
635
Ping-Pong Buffering for Mcbsp Example Param
636
Ping-Pong Buffering for Mcbsp Example Pong Param
636
Ping-Pong Buffering for Mcbsp Example Ping Param
637
Intermediate Transfer Completion Chaining Example
639
Single Large Block Transfer Example
639
Parameter RAM (Param) Entries
640
Registers
640
Smaller Packet Data Transfers Example
640
Channel Options Parameter (OPT)
641
Channel Source Address Parameter (SRC)
643
A Count/B Count Parameter (A_B_CNT)
643
Channel Destination Address Parameter (DST)
644
Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
644
Link Address/B Count Reload Parameter (LINK_BCNTRLD)
645
Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
646
C Count Parameter (CCNT)
646
EDMA3 Channel Controller (EDMA3CC) Registers
647
Revision ID Register (REVID)
650
EDMA3CC Configuration Register (CCCFG)
650
EDMA3CC Configuration Register (CCCFG) Field Descriptions
651
QDMA Channel N Mapping Register (Qchmapn)
652
DMA Channel Queue Number Register N (Dmaqnumn)
653
QDMA Channel Queue Number Register (QDMAQNUM)
654
Event Missed Register (EMR)
655
Event Missed Clear Register (EMCR)
656
QDMA Event Missed Register (QEMR)
657
QDMA Event Missed Clear Register (QEMCR)
658
EDMA3CC Error Register (CCERR)
659
EDMA3CC Error Clear Register (CCERRCLR)
660
Error Evaluate Register (EEVAL)
661
DMA Region Access Enable Register for Region M (Draem)
662
QDMA Region Access Enable for Region M (Qraem)
663
Event Queue Entry Registers (Qxey)
664
Queue N Status Register (Qstatn)
665
Queue Watermark Threshold a Register (QWMTHRA)
666
EDMA3CC Status Register (CCSTAT)
667
Event Register (ER)
669
Event Clear Register (ECR)
670
Event Set Register (ESR)
671
Chained Event Register (CER)
672
Event Enable Register (EER)
673
Event Enable Clear Register (EECR)
674
Event Enable Set Register (EESR)
674
Secondary Event Register (SER)
675
Secondary Event Clear Register (SECR)
675
Interrupt Enable Register (IER)
676
Interrupt Enable Clear Register (IECR)
677
Interrupt Enable Set Register (IESR)
677
Interrupt Pending Register (IPR)
678
Interrupt Clear Register (ICR)
679
Interrupt Evaluate Register (IEVAL)
680
QDMA Event Register (QER)
681
QDMA Event Enable Register (QEER)
682
QDMA Event Enable Clear Register (QEECR)
683
QDMA Event Enable Set Register (QEESR)
683
QDMA Secondary Event Register (QSER)
684
QDMA Secondary Event Clear Register (QSECR)
685
EDMA3 Transfer Controller (EDMA3TC) Registers
686
Revision ID Register (REVID)
687
EDMA3TC Configuration Register (TCCFG)
688
EDMA3TC Channel Status Register (TCSTAT)
689
Error Status Register (ERRSTAT)
690
Error Enable Register (ERREN)
691
Error Clear Register (ERRCLR)
692
Error Details Register (ERRDET)
693
Error Interrupt Command Register (ERRCMD)
694
Read Command Rate Register (RDRATE)
695
Source Active Options Register (SAOPT)
696
Source Active Source Address Register (SASRC)
697
Source Active Count Register (SACNT)
697
Source Active Destination Address Register (SADST)
698
Source Active B-Index Register (SABIDX)
698
Source Active Memory Protection Proxy Register (SAMPPRXY)
699
Source Active Count Reload Register (SACNTRLD)
700
Source Active Source Address B-Reference Register (SASRCBREF)
700
Source Active Destination Address B-Reference Register (SADSTBREF)
701
Destination FIFO Set Count Reload Register (DFCNTRLD)
701
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF)
702
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF)
702
Destination FIFO Options Register N (Dfoptn)
703
Destination FIFO Source Address Register N (Dfsrcn)
704
Destination FIFO Count Register N (Dfcntn)
704
Destination FIFO Destination Address Register N (Dfdstn)
705
Destination FIFO B-Index Register N (Dfbidxn)
705
Destination FIFO Memory Protection Proxy Register N (Dfmpprxyn)
706
Debug Checklist
707
Tips
707
Miscellaneous Programming/Debug Tips
708
Setting up a Transfer
709
18 EMAC/MDIO Module
710
Introduction
711
Features
711
Purpose of the Peripheral
711
Functional Block Diagram
712
EMAC and MDIO Block Diagram
712
Industry Standard(S) Compliance Statement
713
Terminology
713
Architecture
714
Clock Control
714
Memory Map
715
Signal Descriptions
715
Ethernet Configuration-MII Connections
715
EMAC and MDIO Signals for MII Interface
716
Ethernet Configuration-RMII Connections
717
Ethernet Protocol Overview
718
Ethernet Frame Format
718
Programming Interface
719
Basic Descriptor Format
719
Typical Descriptor Linked List
720
Transmit Buffer Descriptor Format
723
Receive Buffer Descriptor Format
726
EMAC Control Module
730
EMAC Control Module Block Diagram
730
MDIO Module
731
MDIO Module Block Diagram
732
EMAC Module
736
EMAC Module Block Diagram
736
MAC Interface
738
Packet Receive Operation
742
Receive Frame Treatment Summary
745
Middle of Frame Overrun Treatment
746
Packet Transmit Operation
747
Receive and Transmit Latency
748
Transfer Node Priority
748
Reset Considerations
749
Initialization
750
Interrupt Support
752
Emulation Considerations
756
Power Management
756
EMAC Control Module Registers
757
Registers
757
EMAC Control Module Revision ID Register (REVID)
758
EMAC Control Module Software Reset Register (SOFTRESET)
759
EMAC Control Module Interrupt Control Register (INTCONTROL)
760
EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)
761
EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)
762
EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)
763
EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)
764
EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)
765
EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)
766
EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)
767
EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)
768
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)
769
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)
770
MDIO Registers
771
MDIO Revision ID Register (REVID)
771
MDIO Control Register (CONTROL)
772
PHY Acknowledge Status Register (ALIVE)
773
PHY Link Status Register (LINK)
773
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
774
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
775
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
776
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
777
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
778
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
779
MDIO User Access Register 0 (USERACCESS0)
780
MDIO User PHY Select Register 0 (USERPHYSEL0)
781
MDIO User Access Register 1 (USERACCESS1)
782
MDIO User PHY Select Register 1 (USERPHYSEL1)
783
EMAC Module Registers
784
Transmit Revision ID Register (TXREVID)
787
Transmit Control Register (TXCONTROL)
787
Transmit Teardown Register (TXTEARDOWN)
788
Receive Revision ID Register (RXREVID)
789
Receive Control Register (RXCONTROL)
789
Receive Teardown Register (RXTEARDOWN)
790
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
791
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
792
Transmit Interrupt Mask Set Register (TXINTMASKSET)
793
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
794
MAC Input Vector Register (MACINVECTOR)
795
MAC End of Interrupt Vector Register (MACEOIVECTOR)
796
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
797
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
798
Receive Interrupt Mask Set Register (RXINTMASKSET)
799
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
800
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
801
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
801
MAC Interrupt Mask Set Register (MACINTMASKSET)
802
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
802
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
803
Receive Unicast Enable Set Register (RXUNICASTSET)
806
Receive Unicast Clear Register (RXUNICASTCLEAR)
807
Receive Maximum Length Register (RXMAXLEN)
808
Receive Buffer Offset Register (RXBUFFEROFFSET)
808
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
809
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
809
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
810
MAC Control Register (MACCONTROL)
811
MAC Status Register (MACSTATUS)
813
Emulation Control Register (EMCONTROL)
815
FIFO Control Register (FIFOCONTROL)
815
MAC Configuration Register (MACCONFIG)
816
Soft Reset Register (SOFTRESET)
816
MAC Source Address Low Bytes Register (MACSRCADDRLO)
817
MAC Source Address High Bytes Register (MACSRCADDRHI)
817
MAC Hash Address Register 1 (MACHASH1)
818
MAC Hash Address Register 2 (MACHASH2)
818
Back off Random Number Generator Test Register (BOFFTEST)
819
Transmit Pacing Algorithm Test Register (TPACETEST)
819
Receive Pause Timer Register (RXPAUSE)
820
Transmit Pause Timer Register (TXPAUSE)
820
MAC Address Low Bytes Register (MACADDRLO)
821
MAC Address High Bytes Register (MACADDRHI)
822
MAC Index Register (MACINDEX)
822
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
823
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
823
Transmit Channel N Completion Pointer Register (Txncp)
824
Receive Channel N Completion Pointer Register (Rxncp)
824
Statistics Register
825
19 External Memory Interface a (EMIFA)
834
Introduction
835
Features
835
Functional Block Diagram
835
Purpose of the Peripheral
835
Architecture
835
EMIFA Functional Block Diagram
835
Clock Control
836
EMIFA Requests
836
Pin Descriptions
836
EMIFA Pins Specific to SDRAM
837
SDRAM Controller and Interface
838
Timing Waveform of SDRAM PRE Command
839
EMIFA to 2M × 16 × 4 Bank SDRAM Interface
840
EMIFA to 512K × 16 × 2 Bank SDRAM Interface
840
Description of the SDRAM Configuration Register (SDCR)
841
Description of the SDRAM Timing Register (SDTIMR)
842
SDRAM LOAD MODE REGISTER Command
843
Refresh Urgency Levels
844
Timing Waveform for Basic SDRAM Read Operation
847
Timing Waveform for Basic SDRAM Write Operation
848
Mapping from Logical Address to EMIFA Pins for 16-Bit SDRAM
849
Asynchronous Controller and Interface
850
EMIFA Asynchronous Interface
850
EMIFA to 8-Bit/16-Bit Memory Interface
851
Common Asynchronous Interface
851
Description of the Asynchronous M Configuration Register (Cencfg)
852
Description of the Asynchronous Wait Cycle Configuration Register (AWCC)
853
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET)
855
Timing Waveform of an Asynchronous Read Cycle in Normal Mode
856
Asynchronous Write Operation in Normal Mode
857
Timing Waveform of an Asynchronous Write Cycle in Normal Mode
858
Asynchronous Read Operation in Select Strobe Mode
859
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
860
Asynchronous Write Operation in Select Strobe Mode
861
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
862
Description of the NAND Flash Control Register (NANDFCR)
863
EMIFA to NAND Flash Interface
864
ECC Value for 8-Bit NAND Flash
866
Data Bus Parking
869
Reset and Initialization Considerations
869
EMIFA Reset Block Diagram
869
Interrupt Support
870
EDMA Event Support
871
Memory Map
871
Pin Multiplexing
871
Priority and Arbitration
872
System Considerations
873
Power Management
874
EMIFA PSC Block Diagram
874
Emulation Considerations
875
Example Configuration
876
Hardware Interface
876
Software Configuration
876
Example Configuration Interface
877
SDRAM Timing Register (SDTIMR)
878
SDRAM Self Refresh Exit Timing Register (SDSRETR)
879
SDRAM Refresh Control Register (SDRCR)
879
SDRAM Configuration Register (SDCR)
880
EMIFA Input Timing Requirements
881
Timing Waveform of an ASRAM Read
882
Timing Waveform of an ASRAM Write
883
ASRAM Timing Requirements with PCB Delays
884
Timing Waveform of an ASRAM Read with PCB Delays
885
Timing Waveform of an ASRAM Write with PCB Delays
886
EMIFA Timing Requirements for TC5516100FT-12 Example
887
Configuring CE3CFG for TC5516100FT-12 Example
889
EMIFA Read Timing Requirements
890
Timing Waveform of a NAND Flash Read
891
NAND Flash Write Timing Requirements
892
Timing Waveform of a NAND Flash Command Write
893
Timing Waveform of a NAND Flash Address Write
893
Timing Waveform of a NAND Flash Data Write
894
EMIFA Timing Requirements for HY27UA081G1M Example
895
Configuring CE2CFG for HY27UA081G1M Example
897
Registers
898
Asynchronous Wait Cycle Configuration Register (AWCC)
899
Module ID Register (MIDR)
899
Asynchronous Wait Cycle Configuration Register (AWCCR)
899
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
900
SDRAM Configuration Register (SDCR)
901
SDRAM Refresh Control Register (SDRCR)
903
Asynchronous N Configuration Registers (CE2CFG-CE5CFG)
904
Asynchronous N Configuration Register (Cencfg)
904
SDRAM Timing Register (SDTIMR)
906
SDRAM Self Refresh Exit Timing Register (SDSRETR)
907
EMIFA Interrupt Raw Register (INTRAW)
908
EMIFA Interrupt Masked Register (INTMSK)
909
EMIFA Interrupt Mask Register (INTMSK)
909
EMIFA Interrupt Mask Set Register (INTMSKSET)
910
EMIFA Interrupt Mask Clear Register (INTMSKCLR)
911
NAND Flash Control Register (NANDFCR)
912
NAND Flash Status Register (NANDFSR)
914
NAND Flash N ECC Registers (NANDF1ECC-NANDF4ECC)
915
NAND Flash N ECC Register (Nandfnecc)
915
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)
916
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1)
917
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2)
917
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3)
918
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4)
918
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1)
919
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)
919
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)
920
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)
920
20 General-Purpose Input/Output (GPIO)
921
Introduction
922
Features
922
Functional Block Diagram
922
Industry Standard(S) Compliance Statement
922
Purpose of the Peripheral
922
Architecture
923
Clock Control
923
Endianness Considerations
923
Pin Multiplexing
923
Signal Descriptions
923
GPIO Block Diagram
923
GPIO Register Structure
924
Using a GPIO Signal as an Output
927
Reset Considerations
928
Using a GPIO Signal as an Input
928
Initialization
929
Interrupt Support
929
EDMA Event Support
930
Emulation Considerations
930
Power Management
930
Registers
931
Revision ID Register (REVID)
932
GPIO Interrupt Per-Bank Enable Register (BINTEN)
933
GPIO Banks 0 and 1 Direction Register (DIR01)
934
GPIO Banks 2 and 3 Direction Register (DIR23)
934
GPIO Banks 4 and 5 Direction Register (DIR45)
934
GPIO Direction Registers (Dirn)
934
GPIO Banks 6 and 7 Direction Register (DIR67)
934
GPIO Bank 8 Direction Register (DIR8)
935
GPIO Output Data Registers (Out_Datan)
936
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01)
936
GPIO Banks 2 and 3 Output Data Register (OUT_DATA23)
936
GPIO Banks 4 and 5 Output Data Register (OUT_DATA45)
936
GPIO Banks 6 and 7 Output Data Register (OUT_DATA67)
936
GPIO Bank 8 Output Data Register (OUT_DATA8)
937
GPIO Set Data Registers (Set_Datan)
938
GPIO Banks 0 and 1 Set Data Register (SET_DATA01)
938
GPIO Banks 2 and 3 Set Data Register (SET_DATA23)
938
GPIO Banks 4 and 5 Set Data Register (SET_DATA45)
938
GPIO Banks 6 and 7 Set Data Register (SET_DATA67)
938
GPIO Bank 8 Set Data Register (SET_DATA8)
939
GPIO Clear Data Registers (Clr_Datan)
940
GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01)
940
GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23)
940
GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45)
940
GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67)
940
GPIO Bank 8 Clear Data Register (CLR_DATA8)
941
GPIO Input Data Registers (In_Datan)
942
GPIO Banks 0 and 1 Input Data Register (IN_DATA01)
942
GPIO Banks 2 and 3 Input Data Register (IN_DATA23)
942
GPIO Banks 4 and 5 Input Data Register (IN_DATA45)
942
GPIO Banks 6 and 7 Input Data Register (IN_DATA67)
942
GPIO Bank 8 Input Data Register (IN_DATA8)
943
GPIO Set Rising Edge Interrupt Registers (Set_Ris_Trign)
944
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01)
944
GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23)
944
GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45)
944
GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67)
944
GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8)
945
GPIO Clear Rising Edge Interrupt Registers (Clr_Ris_Trign)
946
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01)
946
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23)
946
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45)
946
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67)
946
GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8)
947
GPIO Set Falling Edge Interrupt Registers (Set_Fal_Trign)
948
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01)
948
GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23)
948
GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45)
948
GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67)
948
GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8)
949
GPIO Clear Falling Edge Interrupt Registers (Clr_Fal_Trign)
950
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01)
950
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23)
950
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45)
950
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67)
950
GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8)
951
GPIO Interrupt Status Registers (Intstatn)
952
GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01)
952
GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23)
952
GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45)
952
GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67)
952
GPIO Bank 8 Interrupt Status Register (INTSTAT8)
953
21 Host Port Interface (HPI)
954
Introduction
955
Features
955
Purpose of the Peripheral
955
Functional Block Diagram
956
HPI Block Diagram
956
Industry Standard(S) Compliance Statement
957
Terminology Used in this Document
957
Architecture
958
Clock Control
958
Memory Map
958
Signal Descriptions
958
Pin Multiplexing and General-Purpose I/O Control Blocks
959
Operation
960
Protocol Description
960
Example of Host-Processor Signal Connections
961
HPI Strobe and Select Logic
963
Access Types Selectable with the UHPI_HCNTL Signals
964
Multiplexed-Mode Host Read Cycle
965
Multiplexed-Mode Host Write Cycle
966
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write)
967
Cycle Followed by Nonautoincrement HPID Read Cycle)
968
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode
968
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)
968
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode
968
UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1: no Autoincrementing)
969
UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2: Autoincrementing Selected, FIFO Empty before Write)
969
UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode
969
UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3: Autoincrementing Selected, FIFO Not Empty before Write)
970
Fifos in the HPI
971
Initialization
975
Reset Considerations
975
Host-To-CPU Interrupt State Diagram
976
Interrupt Support
976
CPU-To-Host Interrupt State Diagram
977
EDMA Event Support
977
Power Management
977
Emulation Considerations
978
Registers
978
Power and Emulation Management Register (PWREMU_MGMT)
979
Revision Identification Register (REVID)
979
GPIO Enable Register (GPIO_EN)
980
GPIO Data 1 Register (GPIO_DAT1)
981
GPIO Direction 1 Register (GPIO_DIR1)
981
GPIO Direction 2 Register (GPIO_DIR2)
982
GPIO Data 2 Register (GPIO_DAT2)
983
Host Port Interface Control Register (HPIC)
984
Host Port Interface Control Register (HPIC)-CPU Access Permissions
984
Host Port Interface Control Register (HPIC)-Host Access Permissions
984
Host Port Interface Control Register (HPIC) Field Descriptions
985
Host Port Interface Read Address Register (HPIAR)
986
Host Port Interface Write Address Register (HPIAW)
986
22 Inter-Integrated Circuit (I2C) Module
987
Introduction
988
Features
988
Purpose of the Peripheral
988
Functional Block Diagram
989
Industry Standard(S) Compliance Statement
989
I2C Peripheral Block Diagram
989
Architecture
990
Bus Structure
990
Multiple I2C Modules Connected
990
Clock Generation
991
Clocking Diagram for the I2C Peripheral
991
Clock Synchronization
992
Signal Descriptions
992
Synchronization of Two I2C Clock Generators During Arbitration
992
START and STOP Conditions
993
Bit Transfer on the I2C-Bus
993
I2C Peripheral START and STOP Conditions
993
Serial Data Formats
994
I2C Peripheral Data Transfer
994
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)
994
I2C Peripheral 10-Bit Addressing Format with Master-Transmitter Writing to Slave-Receiver (FDF = 0, XA = 1 in ICMDR)
995
I2C Peripheral Free Data Format (FDF = 1 in ICMDR)
995
I2C Peripheral 7-Bit Addressing Format with Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
995
Operating Modes
996
NACK Bit Generation
997
Arbitration
998
Arbitration Procedure between Two Master-Transmitters
998
Initialization
999
Reset Considerations
999
Interrupt Support
1000
DMA Events Generated by the I2C Peripheral
1001
Emulation Considerations
1001
Power Management
1001
Registers
1002
I2C Own Address Register (ICOAR)
1003
I2C Interrupt Mask Register (ICIMR)
1004
I2C Interrupt Status Register (ICSTR)
1005
I2C Clock Divider Registers (ICCLKL and ICCLKH)
1008
I2C Clock Low-Time Divider Register (ICCLKL)
1008
I2C Clock High-Time Divider Register (ICCLKH)
1008
I2C Data Count Register (ICCNT)
1009
I2C Data Receive Register (ICDRR)
1010
I2C Slave Address Register (ICSAR)
1011
I2C Data Transmit Register (ICDXR)
1012
I2C Mode Register (ICMDR)
1013
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits
1015
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
1016
I2C Interrupt Vector Register (ICIVR)
1017
I2C Extended Mode Register (ICEMDR)
1018
I2C Prescaler Register (ICPSC)
1019
I2C Revision Identification Register (REVID1)
1020
I2C Revision Identification Register (REVID2)
1020
I2C Revision Identification Register 1 (REVID1)
1020
I2C Revision Identification Register 2 (REVID2)
1020
I2C DMA Control Register (ICDMAC)
1021
I2C Pin Function Register (ICPFUNC)
1022
I2C Pin Direction Register (ICPDIR)
1023
I2C Pin Data in Register (ICPDIN)
1024
I2C Pin Data out Register (ICPDOUT)
1025
I2C Pin Data Set Register (ICPDSET)
1026
I2C Pin Data Clear Register (ICPDCLR)
1027
23 Liquid Crystal Display Controller (LCDC)
1028
Introduction
1029
Purpose of the Peripheral
1029
LCD Controller
1029
Architecture
1030
Clocking
1030
Features
1030
Terminology
1030
Input and Output Clocks
1030
LCD External I/O Signals
1032
DMA Engine
1033
LIDD Controller
1034
LIDD I/O Name Map
1035
Raster Controller
1036
Logical Data Path for Raster Controller
1037
Frame Buffer Structure
1038
16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP)
1039
256-Entry Palette/Buffer Format (8 BPP)
1040
16-BPP Data Memory Organization (TFT Mode Only)-Little Endian
1040
12-BPP Data Memory Organization-Little Endian
1041
8-BPP Data Memory Organization
1041
2-BPP Data Memory Organization
1042
Color/Grayscale Intensities and Modulation Rates
1043
Monochrome and Color Output
1044
Raster Mode Display Format
1045
LCD Revision Identification Register (REVID)
1046
Registers
1046
LCD Control Register (LCD_CTRL)
1047
Pixel Clock Frequency Programming Limitations
1048
LCD Status Register (LCD_STAT)
1049
LCD LIDD Control Register (LIDD_CTRL)
1052
LCD LIDD Csn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF)
1054
LCD LIDD Csn Configuration Register (Lidd_Csn_Conf)
1054
LCD LIDD Csn Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR)
1055
LCD LIDD Csn Address Read/Write Register (Lidd_Csn_Addr)
1055
LCD LIDD Csn Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA)
1056
LCD LIDD Csn Data Read/Write Register (Lidd_Csn_Data)
1056
LCD Raster Control Register (RASTER_CTRL)
1057
LCD Controller Data Pin Utilization for Mono/Color Passive/Active Panels
1059
Monochrome Passive Mode Pixel Clock and Data Pin Timing
1060
Color Passive Mode Pixel Clock and Data Pin Timing
1060
Active Mode Pixel Clock and Data Pin Timing
1061
TFT Alternate Signal Mapping Output
1062
12-Bit STN Data in Frame Buffer
1063
16-BPP STN Mode
1063
LCD Raster Timing Register 0 (RASTER_TIMING_0)
1064
LCD Raster Timing Register 1 (RASTER_TIMING_1)
1066
Vertical Synchronization Pulse Width (VSW) - Active Mode
1067
Vertical Front Porch (VFP)
1068
Vertical Back Porch (VBP)
1069
LCD Raster Timing Register 2 (RASTER_TIMING_2)
1070
SYNC_CTRL = 0, IPC = 1 in TFT Mode
1072
SYNC_CTRL = 1, SYNC_EDGE = 0, and IPC = 1
1073
LCD Raster Subpanel Display Register (RASTER_SUBPANEL)
1074
Subpanel Display: SPEN = 1, HOLS = 1
1075
Subpanel Display: SPEN = 1, HOLS = 0
1075
LCD DMA Control Register (LCDDMA_CTRL)
1076
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE)
1077
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING)
1077
LCD DMA Frame Buffer N Base Address Registers
1077
LCD DMA Frame Buffer N Ceiling Address Registers
1077
LCD DMA Frame Buffer N Base Address Register (Lcddma_Fbn_Base)
1077
LCD DMA Frame Buffer N Ceiling Address Register (Lcddma_Fbn_Ceiling)
1077
24 Multichannel Audio Serial Port (Mcasp)
1078
Features
1079
Protocols Supported
1080
Functional Block Diagram
1081
Mcasp Block Diagram
1081
Mcasp to Parallel 2-Channel Dacs
1082
Mcasp to 6-Channel DAC and 2-Channel DAC
1082
Mcasp to Digital Amplifier
1083
Mcasp as Digital Audio Encoder
1083
TDM Format-6 Channel TDM Example
1084
TDM Format Bit Delays from Frame Sync
1085
Inter-IC Sound (I2S) Format
1085
Biphase-Mark Code (BMC)
1086
S/PDIF Subframe Format
1087
S/PDIF Frame Format
1088
Definition of Terms
1089
Definition of Bit, Word, and Slot
1089
Bit Order and Word Alignment Within a Slot Examples
1090
Definition of Frame and Frame Sync Width
1091
Clock and Frame Sync Generators
1092
Overview
1092
Transmit Clock Generator Block Diagram
1093
Receive Clock Generator Block Diagram
1094
Frame Sync Generator Block Diagram
1095
Individual Serializer and Connections Within Mcasp
1096
Receive Format Unit
1097
Transmit Format Unit
1098
Mcasp I/O Pin Control Block Diagram
1100
Mcasp I/O Pin to Control Register Mapping
1101
Burst Frame Sync Mode
1106
Transmit DMA Event (AXEVT) Generation in TDM Time Slots
1109
Channel Status and User Data for each DIT Block
1113
DSP Service Time Upon Transmit DMA Event (AXEVT)
1114
DSP Service Time Upon Receive DMA Event (AREVT)
1116
DMA Events in an Audio Example-Two Events
1118
Mcasp Audio FIFO (AFIFO) Block Diagram
1119
Transmit Bitstream Data Alignment
1121
Data Flow through Transmit Format Unit
1122
Receive Bitstream Data Alignment
1123
Data Flow through Receive Format Unit
1124
Audio Mute (AMUTE) Block Diagram
1126
Transmit Clock Failure Detection Circuit Block Diagram
1130
Receive Clock Failure Detection Circuit Block Diagram
1131
Serializers in Loopback Mode
1132
EDMA Event Support
1133
Power Management
1133
Reset Considerations
1133
Registers
1134
Register Bit Restrictions
1137
Revision Identification Register (REV)
1138
Pin Function Register (PFUNC)
1139
Pin Function Register (PFUNC) Field Descriptions
1140
Pin Direction Register (PDIR)
1141
Pin Direction Register (PDIR) Field Descriptions
1142
Pin Data Output Register (PDOUT)
1143
Pin Data Output Register (PDOUT) Field Descriptions
1144
Pin Data Input Register (PDIN)
1145
Pin Data Input Register (PDIN) Field Descriptions
1146
Pin Data Set Register (PDSET)
1147
Pin Data Set Register (PDSET) Field Descriptions
1148
Pin Data Clear Register (PDCLR)
1149
Pin Data Clear Register (PDCLR) Field Descriptions
1150
Global Control Register (GBLCTL)
1151
Audio Mute Control Register (AMUTE)
1153
Digital Loopback Control Register (DLBCTL)
1155
Digital Mode Control Register (DITCTL)
1156
Receiver Global Control Register (RGBLCTL)
1157
Receive Format Unit Bit Mask Register (RMASK)
1158
Receive Bit Stream Format Register (RFMT)
1159
Receive Frame Sync Control Register (AFSRCTL)
1161
Receive Clock Control Register (ACLKRCTL)
1162
Receive High-Frequency Clock Control Register (AHCLKRCTL)
1163
Receive TDM Time Slot Register (RTDM)
1164
Receiver Interrupt Control Register (RINTCTL)
1165
Receiver Status Register (RSTAT)
1166
Current Receive TDM Time Slot Registers (RSLOT)
1167
Receive Clock Check Control Register (RCLKCHK)
1168
Receiver DMA Event Control Register (REVTCTL)
1169
Transmitter Global Control Register (XGBLCTL)
1170
Transmit Format Unit Bit Mask Register (XMASK)
1171
Transmit Bit Stream Format Register (XFMT)
1172
Transmit Frame Sync Control Register (AFSXCTL)
1174
Transmit Clock Control Register (ACLKXCTL)
1175
Transmit High-Frequency Clock Control Register (AHCLKXCTL)
1176
Transmit TDM Time Slot Register (XTDM)
1177
Transmitter Interrupt Control Register (XINTCTL)
1178
Transmitter Status Register (XSTAT)
1179
Current Transmit TDM Time Slot Register (XSLOT)
1180
Transmit Clock Check Control Register (XCLKCHK)
1181
Transmitter DMA Event Control Register (XEVTCTL)
1182
Serializer Control Registers (Srctln)
1183
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
1184
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
1184
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
1185
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
1185
Receive Buffer Registers (Rbufn)
1186
Transmit Buffer Registers (Xbufn)
1186
AFIFO Revision Identification Register (AFIFOREV)
1187
Write FIFO Control Register (WFIFOCTL)
1188
Write FIFO Status Register (WFIFOSTS)
1189
Read FIFO Control Register (RFIFOCTL)
1190
Read FIFO Status Register (RFIFOSTS)
1191
25 Multichannel Buffered Serial Port (Mcbsp)
1192
Introduction
1193
Features
1193
Purpose of the Peripheral
1193
Functional Block Diagram
1194
Industry Standard Compliance Statement
1194
Mcbsp Block Diagram
1194
Architecture
1195
Clock Control
1195
Endianness Considerations
1195
Pin Multiplexing
1195
Signal Descriptions
1195
Clock, Frames, and Data
1196
Clock and Frame Generation
1196
Transmit Data Clocking
1197
Receive Data Clocking
1197
Sample Rate Generator Block Diagram
1198
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1
1201
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3
1201
Digital Loopback Mode
1202
Transmit Clock Selection
1203
Programmable Frame Period and Width
1204
Transmit Frame Synchronization Selection
1205
Dual-Phase Frame Example
1206
Single-Phase Frame of Four 8-Bit Elements
1207
Single-Phase Frame of One 32-Bit Element
1208
Data Delay
1208
2-Bit Data Delay Used to Discard Framing Bit
1209
Mcbsp Buffer FIFO (BFIFO)
1210
Mcbsp Standard Operation
1210
Receive Operation
1211
Transmit Operation
1211
Maximum Frame Frequency for Transmit and Receive
1212
Unexpected Frame Synchronization with (R/X)FIG
1213
Unexpected Frame Synchronization with (R/X)FIG = 1
1214
Maximum Frame Frequency Operation with 8-Bit Data
1214
Data Packing at Maximum Frame Frequency with (R/X)FIG = 1
1215
Serial Port Receive Overrun
1216
Serial Port Receive Overrun Avoided
1216
Decision Tree Response to Receive Frame Synchronization Pulse
1217
Unexpected Receive Frame Synchronization Pulse
1218
Transmit with Data Overwrite
1218
Transmit Empty
1219
Transmit Empty Avoided
1219
Decision Tree Response to Transmit Frame Synchronization Pulse
1221
Unexpected Transmit Frame Synchronization Pulse
1221
Mcbsp Buffer FIFO (BFIFO) Block Diagram
1222
Μ-Law/A-Law Companding Hardware Operation
1224
Companding Flow
1224
Companding Data Formats
1224
Transmit Data Companding Format in DXR
1224
Companding of Internal Data
1225
Multichannel Selection Modes
1226
DX Timing for Multichannel Operation
1227
Receive Channel Assignment and Control When Two Receive Partitions Are Used
1228
Alternating between the Channels of Partition a and the Channels of Partition B
1229
Reassigning Channel Blocks Throughout a Mcbsp Data Transfer
1229
Mcbsp Data Transfer in the 8-Partition Mode
1230
Selecting a Transmit Multichannel Selection Mode with the XMCM Bits
1231
Activity on Mcbsp Pins for the Possible Values of XMCM
1233
Resetting the Serial Port: RRST, XRST, GRST, and RESET
1234
SPI Operation Using the Clock Stop Mode
1234
Mcbsp Initialization Procedure
1235
Interrupt Support
1239
EDMA Event Support
1240
Emulation Considerations
1241
Power Management
1241
Registers
1242
Data Receive Register (DRR)
1243
Data Transmit Register (DXR)
1243
Serial Port Control Register (SPCR)
1244
Receive Control Register (RCR)
1246
Transmit Control Register (XCR)
1248
Sample Rate Generator Register (SRGR)
1250
Multichannel Control Register (MCR)
1251
Multichannel Control Registers (MCR)
1251
Enhanced Receive Channel Enable Registers (RCERE0-RCERE3)
1255
Enhanced Receive Channel Enable Register N (Rceren)
1255
Use of the Receive Channel Enable Registers
1256
Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3)
1257
Enhanced Transmit Channel Enable Register N (Xceren)
1257
Use of the Transmit Channel Enable Registers
1258
Pin Control Register (PCR)
1259
BFIFO Revision Identification Register (BFIFOREV)
1261
Write FIFO Control Register (WFIFOCTL)
1262
Write FIFO Status Register (WFIFOSTS)
1263
Read FIFO Control Register (RFIFOCTL)
1264
Read FIFO Status Register (RFIFOSTS)
1265
SPRUH82C - April 2013 - Revised September 2016
1266
26 Multimedia Card (MMC)/Secure Digital (SD) Card Controller
1266
MMC/SD Card Controller Block Diagram
1267
Introduction
1267
MMC/SD Controller Interface Diagram
1268
Industry Standard(S) Compliance Statement
1268
MMC Configuration and SD Configuration Diagram
1269
Clock Control
1269
MMC/SD Controller Clocking Diagram
1270
Signal Descriptions
1270
MMC/SD Mode Write Sequence Timing Diagram
1271
Protocol Descriptions
1271
MMC/SD Mode Read Sequence Timing Diagram
1272
Data Flow in the Input/Output FIFO
1272
FIFO Operation Diagram
1273
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA
1274
Data Flow in the Data Registers (MMCDRR and MMCDXR)
1274
FIFO Operation During Card Read Operation
1275
FIFO Operation During Card Read Diagram
1276
FIFO Operation During Card Write Operation
1277
FIFO Operation During Card Write Diagram
1278
Initialization
1279
Interrupt Support
1282
DMA Event Support
1283
Procedures for Common Operations
1284
MMC Card Identification Procedure
1285
SD Card Identification Procedure
1286
MMC/SD Mode Single-Block Write Operation Using CPU
1287
MMC/SD Mode Single-Block Write Operation
1288
MMC/SD Mode Single-Block Write Operation Using the EDMA
1289
MMC/SD Mode Single-Block Read Operation
1290
MMC/SD Mode Single-Block Read Operation Using EDMA
1291
MMC/SD Multiple-Block Write Operation
1292
MMC/SD Mode Multiple-Block Write Operation Using EDMA
1293
MMC/SD Mode Multiple-Block Read Operation
1294
MMC/SD Mode Multiple-Block Read Operation Using EDMA
1295
Registers
1296
MMC Control Register (MMCCTL)
1297
MMC Memory Clock Control Register (MMCCLK)
1298
MMC Status Register 0 (MMCST0)
1299
MMC Status Register 1 (MMCST1)
1301
MMC Interrupt Mask Register (MMCIM)
1302
MMC Response Time-Out Register (MMCTOR)
1304
MMC Data Read Time-Out Register (MMCTOD)
1305
MMC Block Length Register (MMCBLEN)
1306
MMC Number of Blocks Register (MMCNBLK)
1307
MMC Number of Blocks Counter Register (MMCNBLC)
1307
MMC Data Receive Register (MMCDRR)
1308
MMC Data Transmit Register (MMCDXR)
1308
MMC Command Register (MMCCMD)
1309
Command Format
1310
MMC Argument Register (MMCARGHL)
1311
MMC Response Register 0 and 1 (MMCRSP01)
1312
MMC Response Register 2 and 3 (MMCRSP23)
1312
MMC Response Register 4 and 5 (MMCRSP45)
1312
MMC Response Register 6 and 7 (MMCRSP67)
1312
MMC Response Registers (MMCRSP0-MMCRSP7)
1312
R1, R3, R4, R5, or R6 Response (48 Bits)
1313
MMC Data Response Register (MMCDRSP)
1314
MMC Command Index Register (MMCCIDX)
1314
SDIO Control Register (SDIOCTL)
1315
SDIO Status Register 0 (SDIOST0)
1316
SDIO Interrupt Enable Register (SDIOIEN)
1317
SDIO Interrupt Status Register (SDIOIST)
1317
MMC FIFO Control Register (MMCFIFOCTL)
1318
Real-Time Clock (RTC)
1319
Real-Time Clock Block Diagram
1320
Introduction
1320
Architecture
1321
Operation
1322
32-Khz Oscillator Counter Compensation
1324
Interrupt Requests
1324
Kick State Machine
1325
Register Protection against Spurious Writes
1325
General-Purpose Scratch Registers
1326
Registers
1327
Second Register (SECOND)
1328
Minute Register (MINUTE)
1328
Hour Register (HOUR)
1329
Days Register (DAY)
1330
Month Register (MONTH)
1330
Day of the Month Register (DAY)
1330
Year Register (YEAR)
1331
Day of the Week Register (DOTW)
1331
Alarm Second Register (ALARMSECOND)
1332
Alarm Minute Register (ALARMMINUTE)
1332
Alarm Hour Register (ALARMHOUR)
1333
Alarm Day Register (ALARMDAY)
1334
Alarm Day of the Month Register (ALARMDAY)
1334
Alarm Month Register (ALARMMONTH)
1335
Alarm Year Register (ALARMYEAR)
1335
Control Register (CTRL)
1336
Status Register (STATUS)
1337
Interrupt Register (INTERRUPT)
1338
Compensation (LSB) Register (COMPLSB)
1339
Compensation (MSB) Register (COMPMSB)
1340
Oscillator Register (OSC)
1341
Scratch Registers (Scratchn)
1342
Kick Registers (Kicknr)
1342
28 Serial ATA (SATA) Controller
1343
Introduction
1344
Terminology Used in this Document
1346
Industry Standard(S) Compliance
1347
Architecture
1348
Signal Descriptions
1349
Transport Layer
1350
Reset
1351
Interrupt Support
1352
EDMA Event Support
1353
General Utilities: Structures and Subroutines Sample Program Uses
1354
Example on Initialization and Spinning up Device
1368
Example of DMA Write Transfer
1370
Example of DMA Read Transfer
1371
SATASS Memory Summary
1373
Registers
1373
SATA Controller Registers
1374
HBA Capabilities Register (CAP)
1375
HBA Capabilities Register (CAP) Field Descriptions
1375
Global HBA Control Register (GHC)
1376
Global HBA Control Register (GHC) Field Descriptions
1376
Interrupt Status Register (IS)
1377
Interrupt Status Register (IS) Field Descriptions
1377
AHCI Version Register (VS)
1378
AHCI Version Register (VS) Field Descriptions
1378
Ports Implemented Register (PI) Field Descriptions
1378
Ports Implemented Register (PI)
1378
Command Completion Coalescing Control Register (CCC_CTL)
1379
Command Completion Coalescing Control Register (CCC_CTL) Field Descriptions
1379
Command Completion Coalescing Ports Register (CCC_PORTS)
1380
Command Completion Coalescing Ports Register (CCC_PORTS) Field Description
1380
BIST Active FIS Register (BISTAFR)
1381
BIST Active FIS Register (BISTAFR) Field Descriptions
1381
BIST Control Register (BISTCR)
1382
BIST Control Register (BISTCR) Field Descriptions
1382
BIST FIS Count Register (BISTFCTR)
1384
BIST Status Register (BISTSR)
1384
BIST FIS Count Register (BISTFCTR) Field Description
1384
BIST Status Register (BISTSR) Field Description
1384
BIST DWORD Error Count Register (BISTDECR)
1385
BIST DWORD Error Count Register (TIMER1MS)
1385
BIST DWORD Error Count Register (BISTDECR) Field Description
1385
BIST DWORD Error Count Register (TIMER1MS) Field Description
1385
Global Parameter 1 Register (GPARAM1R)
1386
Global Parameter 1 Register (GPARAM1R) Field Descriptions
1386
Global Parameter 2 Register (GPARAM2R)
1387
Global Parameter 2 Register (GPARAM2R) Field Descriptions
1387
Port Parameter Register (PPARAMR)
1388
Port Parameter Register (PPARAMR) Field Descriptions
1388
Test Register (TESTR)
1389
Test Register (TESTR) Field Descriptions
1389
ID Register (IDR)
1390
ID Register (IDR) Field Description
1390
Version Register (VERSIONR) Field Description
1390
Version Register (VERSIONR)
1390
Port Command List Base Address Register (P0CLB)
1391
Port FIS Base Address Register (P0FB)
1391
Port Command List Base Address Register (P0CLB) Field Description
1391
Port FIS Base Address Register (P0FB) Field Description
1391
Port Interrupt Status Register (P0IS)
1392
Port Interrupt Status Register (P0IS) Field Descriptions
1392
Port Interrupt Enable Register (P0IE)
1394
Port Interrupt Enable Register (P0IE) Field Descriptions
1394
Port Command Register (P0CMD)
1395
Port Command Register (P0CMD) Field Descriptions
1395
Port Signature Register (P0SIG)
1398
Port Signature Register (P0SIG) Field Description
1398
Port Task File Data Register (P0TFD) Field Descriptions
1398
Port Task File Data Register (P0TFD)
1398
Port Serial ATA Status Register (P0SSTS)
1399
Port Serial ATA Status Register (P0SSTS) Field Descriptions
1399
Port Serial ATA Control Register (P0SCTL)
1400
Port Serial ATA Control Register (P0SCTL) Field Descriptions
1400
Port Serial ATA Error Register (P0SERR)
1401
Port Serial ATA Error Register (P0SERR) Field Descriptions
1401
Port Serial ATA Active (Sactive) Register (P0SACT)
1403
Port Serial ATA Active Register (P0SACT)
1403
Port Serial ATA Active (Sactive) Register (P0SACT) Field Description
1403
Port Serial ATA Active Register (P0SACT) Field Description
1403
Port Serial ATA Notification Register (POSNTF)
1404
Port Serial ATA Notification Register (POSNTF) Field Description
1404
Port DMA Control Register (P0DMACR)
1405
Port DMA Control Register (P0DMACR) Field Description
1405
Port PHY Control Register (P0PHYCR)
1407
Port PHY Control Register (P0PHYCR) Field Descriptions
1407
Port PHY Status Register (P0PHYSR)
1411
Port PHY Status Register (P0PHYSR) Field Description
1411
29 Serial Peripheral Interface (SPI)
1412
Introduction
1413
SPI Block Diagram
1414
Functional Block Diagram
1414
SPI Pins
1415
Architecture
1415
Programmable Registers
1416
SPI Registers
1416
Allowed SPI Register Settings in Master Modes
1417
Master Mode Settings
1417
SPI Register Settings Defining Master Modes
1417
Allowed SPI Register Settings in Slave Modes
1419
Slave Mode Settings
1419
SPI Register Settings Defining Slave Modes
1419
SPI 3-Pin Option
1420
SPI Operation: 3-Pin Mode
1420
SPI Operation: 4-Pin with Chip Select Mode
1421
SPI 4-Pin Option with Spix_Scs[N]
1422
SPI Operation: 4-Pin with Enable Mode
1423
SPI 4-Pin Option with Spix_Ena
1424
SPI Operation: 5-Pin Mode
1425
SPI 5-Pin Option with Spix_Ena and Spix_Scs[N]
1426
Format for Transmitting 12-Bit Word
1427
Format for 10-Bit Received Word
1427
Data Formats
1427
Clock Mode with POLARITY = 0 and PHASE
1428
Clocking Modes
1428
Clock Mode with POLARITY = 0 and PHASE = 1
1429
Clock Mode with POLARITY = 1 and PHASE
1429
Clock Mode with POLARITY = 1 and PHASE = 1
1429
Five Bits Per Character (5-Pin Option)
1430
Interrupt Support
1430
DMA Events Support
1431
Reset Considerations
1433
General-Purpose I/O Pin
1434
SPI 3-Pin Master Mode with WDELAY
1435
Timing Diagrams
1435
SPI 4-Pin with Spix_Scs[N] Mode with T2CDELAY, WDELAY, and C2TDELAY
1436
SPI 4-Pin with Spix_Ena Mode Demonstrating T2EDELAY and WDELAY
1437
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY
1439
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY
1440
SPI Global Control Register 0 (SPIGCR0)
1441
SPI Global Control Register 0 (SPIGCR0) Field Descriptions
1441
SPI Registers
1441
SPI Global Control Register 1 (SPIGCR1)
1442
SPI Global Control Register 1 (SPIGCR1) Field Descriptions
1442
SPI Interrupt Register (SPIINT0)
1444
SPI Interrupt Register (SPIINT0) Field Descriptions
1444
SPI Interrupt Level Register (SPILVL)
1446
SPI Flag Register (SPIFLG)
1447
SPI Pin Control Register 0 (SPIPC0)
1449
SPI Pin Control Register 1 (SPIPC1)
1450
SPI Pin Control Register 2 (SPIPC2)
1451
SPI Pin Control Register 3 (SPIPC3)
1452
SPI Pin Control Register 4 (SPIPC4)
1453
SPI Pin Control Register 5 (SPIPC5)
1454
SPI Data Register 0 (SPIDAT0)
1455
SPI Data Register 1 (SPIDAT1)
1456
SPI Buffer Register (SPIBUF)
1457
SPI Emulation Register (SPIEMU)
1459
SPI Delay Register (SPIDELAY)
1460
C2TDELAY = 8 SPI Module Clock Cycles
1460
T2CDELAY = 4 SPI Module Clock Cycles
1462
Transmit-Data-Finished-To-Spix_Ena-Inactive-Timeout
1462
Chip-Select-Active-To-Spix_Ena-Signal-Active-Timeout
1462
SPI Default Chip Select Register (SPIDEF)
1463
SPI Data Format Register (Spifmtn)
1464
SPI Interrupt Vector Register 1 (INTVEC1)
1466
Bit Timer Plus
1467
Introduction
1468
Timer Block Diagram
1469
Timer Clock Source Block Diagram
1470
64-Bit Timer Mode Block Diagram
1471
Bit Timer Configurations
1472
Dual 32-Bit Timers Chained Mode Block Diagram
1474
Dual 32-Bit Timers Chained Mode Example
1474
Bit Timer Chained Mode Configurations
1475
Dual 32-Bit Timers Unchained Mode Block Diagram
1476
Dual 32-Bit Timers Unchained Mode Example
1477
Bit Timer Unchained Mode Configurations
1478
32-Bit Timer Counter Overflow Example
1480
Architecture – Watchdog Timer Mode
1481
Watchdog Timer Mode Block Diagram
1482
Watchdog Timer Operation State Diagram
1482
Reset Considerations
1483
Timer Operation in Pulse Mode (Cpn = 0)
1484
Timer Operation in Clock Mode (Cpn = 1)
1484
TM64P_OUT Event Support
1484
Interrupt/Dma Event Generation Control and Status
1485
Registers
1486
Revision ID Register (REVID)
1488
Emulation Management Register (EMUMGT)
1488
GPIO Interrupt Control and Enable Register (GPINTGPEN)
1489
GPIO Data and Direction Register (GPDATGPDIR)
1490
Timer Counter Register 12 (TIM12)
1491
Timer Counter Register 34 (TIM34)
1491
Timer Counter Registers (TIM12 and TIM34)
1491
Timer Period Register 12 (PRD12)
1492
Timer Period Register 34 (PRD34)
1492
Timer Period Registers (PRD12 and PRD34)
1492
Timer Control Register (TCR)
1493
Timer Global Control Register (TGCR)
1495
Watchdog Timer Control Register (WDTCR)
1496
Timer Reload Register 12 (REL12)
1497
Timer Reload Register 34 (REL34)
1497
Timer Capture Register 12 (CAP12)
1498
Timer Capture Register 34 (CAP34)
1498
Timer Interrupt Control and Status Register (INTCTLSTAT)
1499
Timer Compare Register (Cmpn)
1500
31 Universal Asynchronous Receiver/Transmitter (UART)
1501
Introduction
1502
UART Block Diagram
1503
UART Clock Generation Diagram
1504
Peripheral Architecture
1504
Relationships between Data Bit, BCLK, and UART Input Clock
1505
Signal Descriptions
1506
UART Protocol Formats
1507
Operation
1508
Character Time for Word Lengths
1509
UART Interface Using Autoflow Diagram
1510
Autoflow Functional Timing Waveforms for Uartn_Rts
1511
Autoflow Functional Timing Waveforms for Uartn_Cts
1511
Reset Considerations
1512
UART Interrupt Request Enable Paths
1513
DMA Event Support
1514
Registers
1515
Receiver Buffer Register (RBR)
1516
Transmitter Holding Register (THR)
1517
Interrupt Enable Register (IER)
1518
Interrupt Enable Register (IER) Field Descriptions
1518
Interrupt Identification Register (IIR)
1519
Interrupt Identification Register (IIR) Field Descriptions
1519
Interrupt Identification and Interrupt Clearing Information
1520
FIFO Control Register (FCR)
1520
FIFO Control Register (FCR)
1521
FIFO Control Register (FCR) Field Descriptions
1521
Line Control Register (LCR)
1522
Line Control Register (LCR) Field Descriptions
1522
Relationship between ST, EPS, and PEN Bits in LCR
1523
Number of STOP Bits Generated
1523
Modem Control Register (MCR)
1524
Modem Control Register (MCR) Field Descriptions
1524
Line Status Register (LSR)
1525
Line Status Register (LSR) Field Descriptions
1525
Modem Status Register (MSR)
1528
Modem Status Register (MSR) Field Descriptions
1528
Scratch Pad Register (SCR)
1529
Scratch Pad Register (MSR) Field Descriptions
1529
Divisor LSB Latch (DLL)
1530
Divisor MSB Latch (DLH)
1530
Divisor LSB Latch (DLL) Field Descriptions
1530
Divisor MSB Latch (DLH) Field Descriptions
1530
Revision Identification Register 1 (REVID1)
1531
Revision Identification Register 2 (REVID2)
1531
Revision Identification Register 1 (REVID1) Field Descriptions
1531
Revision Identification Register 2 (REVID2) Field Descriptions
1531
Revision Identification Registers (REVID1 and REVID2)
1531
Power and Emulation Management Register (PWREMU_MGMT)
1532
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
1532
Mode Definition Register (MDR)
1533
Mode Definition Register (MDR) Field Descriptions
1533
32 Universal Parallel Port (Upp)
1534
Introduction
1535
Upp Functional Block Diagram
1536
Data Flow for Single-Channel Receive Mode
1536
Data Flow for Single-Channel Transmit Mode
1536
Data Flow for Digital Loopback (DLB) Mode (Duplex Mode 0)
1537
Data Flow for Single-Channel Transmit with Data Interleave
1537
Clock Generation for a Channel Configured in Transmit Mode
1538
Clock Generation for a Channel Configured in Receive Mode
1538
Architecture
1538
I/O Clock Speeds for Channel in Transmit Mode Given 150 Mhz Transmit Clock
1539
Upp Signal Descriptions
1539
Signal Description
1539
DATA and XDATA Pin Assignments to Channels a and B According to Operating Mode
1540
Pin Multiplexing
1540
Structure of DMA Window and Lines in Memory
1541
Interface and DMA Channel Mapping for Various Operating Modes
1542
Required Signals for Various Modes
1543
Protocol Description
1543
Signal Timing for Upp Channel in Receive Mode with Single Data Rate
1544
Signal Timing for Upp Channel in Transmit Mode with Single Data Rate
1545
Signal Timing for Upp Channel in Receive Mode with Double Data Rate
1545
Signal Timing for Upp Channel in Transmit Mode with Double Data Rate
1545
Signal Timing for Upp Channel in Receive Mode with Double Data Rate and Data Interleave Enabled (Via UPCTL.DDRDEMUX)
1546
Signal Timing for Upp Channel in Transmit Mode with Double Data Rate and Data Interleave Enabled (Via UPCTL.DDRDEMUX)
1546
Signal Timing for Upp Channel in Transmit Mode with Single Data Rate and Data Interleave Enabled (Via UPCTL.SDRTXIL)
1546
Data Packing Examples for 12-Bit Data Words
1547
Initialization and Operation
1548
Basic Operating Mode Selection
1549
Sample Upp Parameters for Duplex Mode
1550
Upp Parameters Useful for System Tuning
1551
Reset Considerations
1553
Power Management
1554
Upp Peripheral Identification Register (UPPID)
1555
Upp Peripheral Identification Register (UPPID) Field Descriptions
1555
Upp Registers
1555
Upp Peripheral Control Register (UPPCR)
1556
Upp Peripheral Control Register (UPPCR) Field Descriptions
1556
Upp Digital Loopback Register (UPDLB)
1557
Upp Digital Loopback Register (UPDLB) Field Descriptions
1557
Upp Channel Control Register (UPCTL)
1558
Upp Channel Control Register (UPCTL) Field Descriptions
1558
Upp Interface Configuration Register (UPICR)
1560
Upp Interface Configuration Register (UPICR) Field Descriptions
1560
Upp Interface Idle Value Register (UPIVR)
1562
Upp Interface Idle Value Register (UPIVR) Field Descriptions
1562
Upp Threshold Configuration Register (UPTCR)
1563
Upp Threshold Configuration Register (UPTCR) Field Descriptions
1563
Upp Interrupt Raw Status Register (UPISR)
1564
Upp Interrupt Raw Status Register (UPISR) Field Descriptions
1564
Upp Interrupt Enabled Status Register (UPIER)
1566
Upp Interrupt Enabled Status Register (UPIER) Field Descriptions
1566
Upp Interrupt Enable Set Register (UPIES)
1568
Upp Interrupt Enable Set Register (UPIES) Field Descriptions
1568
Upp Interrupt Enable Clear Register (UPIEC)
1570
Upp Interrupt Enable Clear Register (UPIEC) Field Descriptions
1570
Upp End of Interrupt Register (UPEOI)
1572
Upp DMA Channel I Descriptor 0 Register (UPID0)
1572
Upp DMA Channel I Descriptor 0 Register (UPID0) Field Descriptions
1572
Upp End of Interrupt Register (UPEOI) Field Descriptions
1572
Upp DMA Channel I Descriptor 1 Register (UPID1)
1573
Upp DMA Channel I Descriptor 2 Register (UPID2)
1573
Upp DMA Channel I Descriptor 1 Register (UPID1) Field Descriptions
1573
Upp DMA Channel I Descriptor 2 Register (UPID2) Field Descriptions
1573
Upp DMA Channel I Status 0 Register (UPIS0)
1574
Upp DMA Channel I Status 1 Register (UPIS1)
1574
Upp DMA Channel I Status 0 Register (UPIS0) Field Descriptions
1574
Upp DMA Channel I Status 1 Register (UPIS1) Field Descriptions
1574
Upp DMA Channel I Status 2 Register (UPIS2)
1575
Upp DMA Channel I Status 2 Register (UPIS2) Field Descriptions
1575
Upp DMA Channel Q Descriptor 0 Register (UPQD0)
1576
Upp DMA Channel Q Descriptor 1 Register (UPQD1)
1576
Upp DMA Channel Q Descriptor 0 Register (UPQD0) Field Descriptions
1576
Upp DMA Channel Q Descriptor 1 Register (UPQD1) Field Descriptions
1576
Upp DMA Channel Q Descriptor 2 Register (UPID2)
1577
Upp DMA Channel Q Descriptor 2 Register (UPID2) Field Descriptions
1577
Upp DMA Channel Q Status 0 Register (UPQS0)
1578
Upp DMA Channel Q Status 1 Register (UPQS1)
1578
Upp DMA Channel Q Status 0 Register (UPQS0) Field Descriptions
1578
Upp DMA Channel Q Status 2 Register (UPQS2)
1579
33 Universal Serial Bus OHCI Host Controller
1580
Introduction
1581
Architecture
1582
Open Host Controller Interface Functionality
1583
Implementation of OHCI Specification for USB1.1
1584
Relationships between Virtual Address Physical Address
1585
OHCI Interrupts
1585
Registers
1586
HC Operating Mode Register (HCCONTROL)
1587
OHCI Revision Number Register (HCREVISION)
1587
HC Operating Mode Register (HCCONTROL) Field Descriptions
1588
HC Command and Status Register (HCCOMMANDSTATUS)
1589
HC Interrupt and Status Register (HCINTERRUPTSTATUS)
1590
HC Interrupt Enable Register (HCINTERRUPTENABLE)
1591
HC Interrupt Disable Register (HCINTERRUPTDISABLE)
1592
HC Current Periodic Register (HCPERIODCURRENTED)
1593
HC HCAA Address Register (HCHCCA)
1593
HC Current Control Register (HCCONTROLCURRENTED)
1594
HC Head Control Register (HCCONTROLHEADED)
1594
HC Current Bulk Register (HCBULKCURRENTED)
1595
HC Head Bulk Register (HCBULKHEADED)
1595
HC Frame Interval Register (HCFMINTERVAL)
1596
HC Head Done Register (HCDONEHEAD)
1596
HC Frame Number Register (HCFMNUMBER)
1597
HC Frame Remaining Register (HCFMREMAINING)
1597
HC Low-Speed Threshold Register (HCLSTHRESHOLD)
1598
HC Periodic Start Register (HCPERIODICSTART)
1598
HC Root Hub a Register (HCRHDESCRIPTORA)
1599
HC Root Hub B Register (HCRHDESCRIPTORB)
1600
HC Root Hub Status Register (HCRHSTATUS)
1601
HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
1602
HC Port 2 Status and Control Register (HCRHPORTSTATUS2)
1604
34 Universal Serial Bus 2.0 (USB) Controller
1606
Functional Block Diagram
1607
Introduction
1607
USB Clocking Diagram
1608
Industry Standard(S) Compliance Statement
1608
USB Clock Multiplexing Options
1609
Signal Descriptions
1610
USB PHY Initialization
1611
USB Controller Host and Peripheral Modes Operation
1612
Interrupt Service Routine Flow Chart
1613
CPU Actions at Transfer Phases
1618
Sequence of Transfer
1618
Service Endpoint 0 Flow Chart
1620
IDLE Mode Flow Chart
1621
TX Mode Flow Chart
1622
RX Mode Flow Chart
1623
PERI_TXCSR Register Bit Configuration for Bulk in Transactions
1625
PERI_RXCSR Register Bit Configuration for Bulk out Transactions
1626
PERI_TXCSR Register Bit Configuration for Isochronous in Transactions
1628
PERI_RXCSR Register Bit Configuration for Isochronous out Transactions
1630
Setup Phase of a Control Transaction Flow Chart
1633
IN Data Phase Flow Chart
1635
OUT Data Phase Flow Chart
1637
Completion of SETUP or out Data Phase Flow Chart
1639
Completion of in Data Phase Flow Chart
1641
USB Controller Block Diagram
1648
Communications Port Programming Interface (CPPI) 4.1 DMA Overview
1648
Host Packet Descriptor Layout
1651
Host Packet Descriptor Word 2 (HPD Word 2)
1652
Host Packet Descriptor Word 6 (HPD Word 6)
1653
Host Buffer Descriptor Layout
1654
Host Buffer Descriptor Word 4 (HBD Word 4)
1655
Teardown Descriptor Layout
1656
Teardown Descriptor Word
1656
Teardown Descriptor Words
1656
Allocation of Queues
1657
Relationship between Memory Regions and Linking RAM
1659
High-Level Transmit and Receive Data Transfer Example
1665
Transmit Descriptors and Queue Status Configuration
1666
Transmit USB Data Flow Example (Initialization)
1667
Transmit USB Data Flow Example (Completion)
1668
Receive Descriptors and Queue Status Configuration
1669
Receive USB Data Flow Example (Initialization)
1669
Receive USB Data Flow Example (Completion)
1670
Interrupts Generated by the USB Controller
1671
USB Interrupt Conditions
1671
Test Modes
1672
USB Interrupts
1674
Reset Considerations
1674
Use Cases
1675
User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode
1679
User Case 3: Example of How to Program the USB Endpoints in Host Mode
1680
User Case 4: Example of How to Program the USB DMA Controller
1682
Universal Serial Bus OTG (USB0) Registers
1687
Revision Identification Register (REVID)
1694
Control Register (CTRLR)
1694
Control Register (CTRLR) Field Descriptions
1694
Revision Identification Register (REVID) Field Descriptions
1694
Status Register (STATR)
1695
Emulation Register (EMUR)
1695
Emulation Register (EMUR) Field Descriptions
1695
Status Register (STATR) Field Descriptions
1695
Mode Register (MODE)
1696
Mode Register (MODE) Field Descriptions
1696
Auto Request Register (AUTOREQ)
1698
Auto Request Register (AUTOREQ) Field Descriptions
1698
SRP Fix Time Register (SRPFIXTIME)
1699
Teardown Register (TEARDOWN)
1699
SRP Fix Time Register (SRPFIXTIME) Field Descriptions
1699
Teardown Register (TEARDOWN) Field Descriptions
1699
USB Interrupt Source Register (INTSRCR)
1700
USB Interrupt Source Register (INTSRCR) Field Descriptions
1700
USB Interrupt Source Set Register (INTSETR)
1701
USB Interrupt Source Set Register (INTSETR) Field Descriptions
1701
USB Interrupt Source Clear Register (INTCLRR)
1702
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions
1702
USB Interrupt Mask Register (INTMSKR)
1703
USB Interrupt Mask Register (INTMSKR) Field Descriptions
1703
USB Interrupt Mask Set Register (INTMSKSETR)
1704
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions
1704
USB Interrupt Mask Clear Register (INTMSKCLRR)
1705
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions
1705
USB Interrupt Source Masked Register (INTMASKEDR)
1706
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions
1706
USB End of Interrupt Register (EOIR)
1707
Generic RNDIS EP1 Size Register (GENRNDISSZ1)
1707
Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions
1707
USB End of Interrupt Register (EOIR) Field Descriptions
1707
Generic RNDIS EP2 Size Register (GENRNDISSZ2)
1708
Generic RNDIS EP3 Size Register (GENRNDISSZ3)
1708
Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions
1708
Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions
1708
Generic RNDIS EP4 Size Register (GENRNDISSZ4)
1709
Function Address Register (FADDR)
1709
Function Address Register (FADDR) Field Descriptions
1709
Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions
1709
Power Management Register (POWER)
1710
Power Management Register (POWER) Field Descriptions
1710
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
1711
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (Intrtx)Field Descriptions
1711
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
1712
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions
1712
Interrupt Enable Register for INTRTX (INTRTXE)
1713
Interrupt Enable Register for INTRRX (INTRRXE)
1713
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions
1713
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions
1713
Interrupt Register for Common USB Interrupts (INTRUSB)
1714
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions
1714
Interrupt Enable Register for INTRUSB (INTRUSBE)
1715
Frame Number Register (FRAME)
1715
Frame Number Register (FRAME) Field Descriptions
1715
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions
1715
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
1716
Register to Enable the USB 2.0 Test Modes (TESTMODE)
1716
Index Register for Selecting the Endpoint Status and Control Registers (Index)Field Descriptions
1716
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions
1716
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
1717
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions
1717
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
1718
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions
1718
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
1719
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions
1719
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
1720
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions
1720
Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
1721
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions
1721
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
1722
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions
1722
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
1723
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions
1723
Control Status Register for Host Receive Endpoint (HOST_RXCSR)
1724
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions
1724
Count 0 Register (COUNT0)
1725
Receive Count Register (RXCOUNT)
1725
Count 0 Register (COUNT0) Field Descriptions
1725
Receive Count Register (RXCOUNT) Field Descriptions
1725
Type Register (Host Mode Only) (HOST_TYPE0)
1726
Transmit Type Register (Host Mode Only) (HOST_TXTYPE)
1726
Type Register (Host Mode Only) (HOST_TYPE0) Field Descriptions
1726
Naklimit0 Register (Host Mode Only) (HOST_NAKLIMIT0)
1727
Transmit Interval Register (Host Mode Only) (HOST_TXINTERVAL)
1727
Receive Type Register (Host Mode Only) (HOST_RXTYPE)
1728
Receive Interval Register (Host Mode Only) (HOST_RXINTERVAL)
1729
Configuration Data Register (CONFIGDATA)
1730
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
1731
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
1731
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
1732
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
1732
Device Control Register (DEVCTL)
1733
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
1733
Receive Endpoint FIFO Size (RXFIFOSZ)
1734
Transmit Endpoint FIFO Size (TXFIFOSZ)
1734
Receive Endpoint FIFO Address (RXFIFOADDR)
1735
Transmit Endpoint FIFO Address (TXFIFOADDR)
1735
Hardware Version Register (HWVERS)
1736
Transmit Function Address (TXFUNCADDR)
1737
Transmit Hub Address (TXHUBADDR)
1737
Transmit Hub Port (TXHUBPORT)
1737
Receive Function Address (RXFUNCADDR)
1738
Receive Hub Address (RXHUBADDR)
1738
Receive Hub Port (RXHUBPORT)
1738
CDMA Revision Identification Register (DMAREVID)
1739
CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)
1739
CDMA Emulation Control Register (DMAEMU)
1740
CDMA Transmit Channel N Global Configuration Registers (TXGCR[0]-TXGCR[3])
1740
CDMA Transmit Channel N Global Configuration Registers (Txgcr[N])
1740
CDMA Receive Channel N Global Configuration Registers (RXGCR[0]-RXGCR[3])
1741
CDMA Receive Channel N Global Configuration Registers (Rxgcr[N])
1741
CDMA Receive Channel N Host Packet Configuration Registers a (RXHPCRA[0]- RXHPCRA[3])
1742
Receive Channel N Host Packet Configuration Registers a (Rxhpcra[N])
1742
CDMA Receive Channel N Host Packet Configuration Registers B (RXHPCRB[0]- RXHPCRB[3])
1743
Receive Channel N Host Packet Configuration Registers B (Rxhpcrb[N])
1743
CDMA Scheduler Control Register (DMA_SCHED_CTRL)
1744
CDMA Scheduler Table Word N Registers (WORD[0]-WORD[63])
1744
CDMA Scheduler Table Word N Registers (Word[N])
1744
Queue Manager Queue Diversion Register (DIVERSION)
1746
Queue Manager Revision Identification Register (QMGRREVID)
1746
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)
1747
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)
1748
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)
1749
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)
1750
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE)
1750
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
1751
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
1751
Queue Manager Queue Pending Register 0 (PEND0)
1752
Queue Manager Queue Pending Register 1 (PEND1)
1752
Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]- QMEMRBASE[15])
1753
Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R])
1753
Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15])
1754
Queue Manager Memory Region R Control Registers (QMEMRCTRL[R])
1754
Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63])
1755
Queue Manager Queue N Control Register D (CTRLD[N])
1755
Queue Manager Queue N Status Register a (QSTATA[0]-QSTATA[63])
1756
Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63])
1756
Queue Manager Queue N Status Register a (QSTATA[N])
1756
Queue Manager Queue N Status Register B (QSTATB[N])
1756
Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63])
1757
Queue Manager Queue N Status Register C (QSTATC[N])
1757
35 Video Port Interface (VPIF)
1758
Introduction
1759
Overview
1759
Input and Output Channels of VPIF
1759
Features
1760
Features Not Supported
1760
Functional Block Diagram
1760
Video Port Interface (VPIF) Block Diagram
1760
VPIF Architecture Block Diagram
1761
Supported Formats on VPIF
1762
Architecture
1763
Clock Control
1763
Signal Descriptions
1763
Interlaced Video
1764
Memory Interface
1765
Progressive Video
1765
Memory Storage Modes for Interlaced Video
1766
SPRUH82C - April 2013 - Revised September 2016
1767
Video Transmit
1767
Video Receive
1768
Raw Data Capture
1769
Functional Image of Raw Data Capturing Mode
1769
Raw Capture Progressive Mode
1770
Raw Capture Interlaced Mode
1771
Stuffing Manner in Storage Memory
1771
VBI Ancillary Data
1772
VBI Result Data Transmit Image for Interlaced Image
1772
Reset Considerations
1774
Initialization
1775
Interrupt Support
1775
Module Performance with Emulation Suspend Signal
1777
Emulation Suspend Function on Channels 2 and 3 (Transmit)
1778
Method for Turning off Module Channel
1779
Clock Control on Video Input and Output with SDTV Encoding
1780
Clock Control on Video Input and Output with HDTV Encoding
1782
Clock Control on Video Input and Output with HDTV Encoding
1783
Registers
1784
Channel 0 Control Register (C0CTRL)
1787
VPIF Revision Register ID (REVID)
1787
VPIF Revision ID Register (REVID)
1787
Channel 1 Control Register (C1CTRL)
1789
Channel 2 Control Register (C2CTRL)
1790
Channel 3 Control Register (C3CTRL)
1792
Interrupt Enable Register (INTEN)
1794
Interrupt Enable Set Register (INTSET)
1795
Interrupt Enable Clear Register (INTCLR)
1796
Interrupt Status Register (INTSTAT)
1797
Interrupt Status Clear Register (INTSTATCLR)
1798
DMA Size Control Register (REQSIZE)
1799
Emulation Suspend Control Register (EMUCTRL)
1799
Channel N Bottom Field Luminance Address Register (Cnbluma)
1800
Channel N Top Field Luminance Address Register (Cntluma)
1800
Channel N Bottom Field Chrominance Address Register (Cnbchroma)
1801
Channel N Top Field Chrominance Address Register (Cntchroma)
1801
Channel N Bottom Field Horizontal Ancillary Address Register (Cnbhanc)
1802
Channel N Top Field Horizontal Ancillary Address Register (Cnthanc)
1802
Channel N Bottom Field Vertical Ancillary Address Register (Cnbvanc)
1803
Channel N Top Field Vertical Ancillary Address Register (Cntvanc)
1803
Channel N Bottom Field Vertical Ancillary Data Buffer Start Address Register (Cnbvanc)
1803
Channel N Horizontal Ancillary Address Offset Register (Cnhancoffset)
1804
Channel N Image Address Offset Register (Cnimgoffset)
1804
Channel N Horizontal Size Configuration Register (C0HCFG and C1HCFG)
1805
Channel N Horizontal Size Configuration Register (Cnhcfg)
1805
Channel N Vertical Size Configuration 0 Register (C0VCFG0 and C1VCFG0)
1806
Channel N Vertical Size Configuration 1 Register (C0VCFG1 and C1VCFG1)
1806
Channel N Vertical Size Configuration 0 Register (Cnvcfg0)
1806
Channel N Vertical Data Size Configuration 1 Register (Cnvcfg1)
1806
Channel N Vertical Image Size Register (C0VSIZE and C1VSIZE)
1807
Channel N Vertical Size Configuration 2 Register (C0VCFG2 and C1VCFG2)
1807
Channel N Vertical Size Configuration 2 Register (Cnvcfg2)
1807
Channel N Vertical Image Size Register (Cnvsize)
1807
Channel N Horizontal Size Configuration Register (C2HCFG and C3HCFG)
1808
Channel N Horizontal Size Configuration Register (Cnhcfg)
1808
Channel N Vertical Size Configuration 0 Register (C2VCFG0 and C3VCFG0)
1809
Channel N Vertical Size Configuration 1 Register (C2VCFG1 and C3VCFG1)
1809
Channel N Vertical Size Configuration 0 Register (Cnvcfg0)
1809
Channel N Vertical Size Configuration 1 Register (Cnvcfg1)
1809
Channel N Vertical Image Size Register (C2VSIZE and C3VSIZE)
1810
Channel N Vertical Size Configuration 2 Register (C2VCFG2 and C3VCFG2)
1810
Channel N Vertical Size Configuration 2 Register (Cnvcfg2)
1810
Channel N Vertical Image Size Register (Cnvsize)
1810
Channel N Top Field Horizontal Ancillary Position Register (C2THANCPOS and C3THANCPOS)
1811
Channel N Top Field Horizontal Ancillary Position Register (Cnthancpos)
1811
Channel N Top Field Horizontal Ancillary Size Register (C2THANCSIZE and C3THANCSIZE)
1812
Channel N Top Field Horizontal Ancillary Size Register (Cnthancsize)
1812
Channel N Bottom Field Horizontal Ancillary Position Register (C2BHANCPOS and C3BHANCPOS)
1813
Channel N Bottom Field Horizontal Ancillary Position Register (Cnbhancpos)
1813
Channel N Bottom Field Horizontal Ancillary Size Register (C2BHANCSIZE and C3BHANCSIZE)
1814
Channel N Bottom Field Horizontal Ancillary Size Register (Cnbhancsize)
1814
Channel N Top Field Vertical Ancillary Position Register (C2TVANCPOS and C3TVANCPOS)
1815
Channel N Top Field Vertical Ancillary Position Register (Cntvancpos)
1815
Channel N Top Field Vertical Ancillary Size Register (C2TVANCSIZE and C3TVANCSIZE)
1816
Channel N Top Field Vertical Ancillary Size Register (Cntvancsize)
1816
Channel N Bottom Field Vertical Ancillary Position Register (C2BVANCPOS and C3BVANCPOS)
1817
Channel N Bottom Field Vertical Ancillary Position Register (Cnbvancpos)
1817
Channel N Bottom Field Vertical Ancillary Size Register (Cnbvancsize)
1818
Revision History
1819
Important Notice
1820
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Texas Instruments AM1808 User Manual (265 pages)
arm microprocessor
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1.96 MB
Table of Contents
1 AM1808 ARM Microprocessor
1
Features
1
Applications
2
Description
3
Functional Block Diagram
4
Table of Contents
5
2 Revision History
6
3 Device Overview
7
Device Characteristics
7
Device Compatibility
8
ARM Subsystem
8
Memory Map Summary
11
Pin Assignments
14
Pin Multiplexing Control
17
Terminal Functions
18
Device Configuration
18
Unused Pin Configurations
58
4 Device Configuration
60
Boot Modes
60
SYSCFG Module
60
Pullup/Pulldown Resistors
63
5 Specifications
64
Absolute Maximum Ratings over Operating Junction Temperature Range (Unless Otherwise Noted)
64
Handling Ratings
64
Recommended Operating Conditions
65
Notes on Recommended Power-On Hours (POH)
67
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
68
6 Peripheral Information and Electrical Specifications
69
Parameter Information
69
Recommended Clock and Control Signal Transition Behavior
70
Power Supplies
70
Reset
71
Crystal Oscillator or External Clock Input
75
Clock Plls
76
Interrupts
81
Power and Sleep Controller (PSC)
87
Power Domain and Module Topology
89
Edma
92
External Memory Interface a (EMIFA)
98
Ddr2/Mddr Memory Controller
109
Memory Protection Units
122
MMC / Sd / Sdio (Mmcsd0, Mmcsd1)
125
Serial ATA Controller (SATA)
128
Multichannel Audio Serial Port (Mcasp)
133
Multichannel Buffered Serial Port (Mcbsp)
142
Serial Peripheral Interface Ports (SPI0, SPI1)
151
Inter-Integrated Circuit Serial Ports (I2C)
172
Universal Asynchronous Receiver/Transmitter (UART)
176
Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
178
Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
185
Ethernet Media Access Controller (EMAC)
186
Management Data Input/Output (MDIO)
193
Mdio Registers
193
LCD Controller (LCDC)
195
Host-Port Interface (UHPI)
210
Universal Parallel Port (Upp)
218
Video Port Interface (VPIF)
223
Enhanced Capture (Ecap) Peripheral
228
Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
231
Timers
236
Real Time Clock (RTC)
238
General-Purpose Input/Output (GPIO)
241
Programmable Real-Time Unit Subsystem (PRUSS)
245
Emulation Logic
248
7 Device and Documentation Support
256
Device Support
256
Community Resources
257
Documentation Support
257
Trademarks
257
Glossary
258
Mechanical Packaging and Orderable Information
258
Thermal Data for ZCE Package
258
Thermal Data for ZWT Package
259
Important Notice
265
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