Ramset Structure; Instruction Cache Operation - Texas Instruments OMAP5912 Reference Manual

3.2.4

Ramset Structure

½ Ramset Cache Structure
Figure 8.
TAG TAG
array
valid bit
3.2.5

Instruction Cache Operation

SPRU750A
Ramset memory uses the live valid bit (LVB) to indicate whether or not an
individual line in the memory block is valid like regular cache memory. In
addition, there is a TAG valid bit (TVB) associated with each ½ ramset memory
block that indicates whether the TAG entry is valid. The TVB is set to 0 when
the ½ ramset is enabled or flushed. Once the ramset data array is filled (all
LVB=1), the TAG valid bit is set. This field can be monitored for ramset load
completion. While the ramset data array is being loaded from external
memory, DSP requests have lower priority than ramset fill requests. Figure 8
shows the ½ ramset cache structure.
Ramset
Line
Data array
valid bit
The operation of the cache is initiated if an external program fetch is requested
by the DSP. The overall process follows these steps:
1) The CPU generates a program instruction fetch request.
2) The MIF decodes the program address to route the request to either the
I-cache or the internal memories.
3) The I-cache returns the requested instruction (hit), or, if not present (miss),
initiates an external memory access via the EMIF.
To determine if a cache hit or miss results, a control circuit parses the program
address into TAG, index number, and word number. The index number selects
the cache line(s) to test. If there is a match between the TAG number and the
TAG(s) stored in the TAG array, then the line valid bit is also verified to confirm
that the line matching the tag is valid. This is called a presence check. On a
DSP Memory
Set number Line number
0
1
0
256
DSP Subsystem 27