32-Khz Synchronized Timer; Functional Description; Reading The Timer - Texas Instruments OMAP5912 Reference Manual

32-kHz Synchronized Timer

5 32-kHz Synchronized Timer
5.1

Functional Description

Figure 10. 32-kHz SYNCH Timer
OCP
data in
OCP clock
CLK32K_IN
5.1.1

Reading the Timer

52 Timers
The 32-kHz synchronization counter is a 32-bit counter clocked by the falling
edge of the 32-kHz clock.
It is reset with external asynchronous power-up reset (PWRON_RESET).
When PWRON_RESET is released after three 32-kHz clock periods, the
counter starts counting up from the reset value of the counter register on the
falling edge of the 32-kHz clock.
When the highest value is reached, it wraps back to zero and starts running
again.
OCP bus interface
Synchronization
Read counter
Synchronization ensures the read transaction correctness by synchronizing
the counter register read access on the OCP clock signal. The
PWRON_RESET input pin resets the counter register (CR) and the inverted
CLK32K_IN clocks it.
The counter register is 32 bits wide and a 16-bit capture is done on the 16-bit
LSB first to allow LSB16 + MSB16 capture.
Internal synchronization logic allows the counter value to be read while the
counter is running. The time latency to read a synchronized register is one
OCP clock period.
Internal reset
Synchronization
+1
CR
OCP
data out
PWRON_RESET
SPRU759B