Layer 4 Interconnect - Texas Instruments OMAP5912 Reference Manual

Layer 4 Interconnect

Table 1. MPU/DSP Peripheral Access (Continued)
MPU Domain
Module MPU Start
Name
Die ID FFFE 1800
(test)
Test block FFFE
(PSA test) D400
DSP trace
Note: The SSI and the GDD modules are on the L3-OCP2 port and thus are seen as part of memory port interface.
2 Layer 4 Interconnect
20 Peripheral Interconnects
MPU End MPU TIPB
Bus Type
FFFE 1FFF Private
FFFE D4FF Private
The layer 4 interface manages accesses to OMAP5912 peripherals through
the MPU shared TIPB bridge, DSP shared TIPB bridge, MPU private TIPB
bridge, and DSP private TIPB bridge. DSP TIPB bridges are inside the C55x
DSP. It is composed of a set of dynamic and static switches and wrappers
dedicated to the access protocol of each peripheral. The MPU TIPB bridge is
already a merge of MPU and system DMA signals for peripheral accesses.
The DSP TIPB bridge is already a merge of DSP and system DMA signals for
peripheral accesses (see Figure 2).
Two different switches are implemented:
-
Static TIPB/OCP: OCP/TIPB switch (configuration register included)
-
Dynamic TIPB/OCP: OCP/TIPB switch with resynchronization on MPU
and DSP accesses
Two different wrappers are provided:
-
TIPB/VIA: VIA/TIPB wrapper with resynchronization
-
MPU (or DSP) TIPB/OCP: OCP/TIPB wrapper
The common protocol on the MPU/DSP side is the TIPB bus protocol. For each
TIPB bridge, a dedicated router is implemented to allow the multiplexing of all
the return paths from the peripherals.
-
MPU shared TIPB router to MPU shared TIPB bridge
-
DSP shared TIPB router to DSP shared TIPB bridge
DSP Domain
L4 Controler DSP Start
Switch
E100 4000
DSP End DSP TIPB
Bus Type
E100 Private
47FF
SPRU758A