Dual-Mode Timer Registers - Texas Instruments OMAP5912 Reference Manual

Dual-Mode Timer
4.15

Dual-Mode Timer Registers

Table 32. Dual-Mode Timer Registers
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7
Name Description
TIDR Timer identification
RESERVED Reserved
RESERVED Reserved
RESERVED Reserved
TIOCP_CFG Timer OCP configuration
TISTAT Timer system status
TISR Timer status
TIER Timer interrupt enable
TWER Timer wake-up enable
TCLR Timer control
TCRR Timer counter
TLDR Timer load
TTGR Timer trigger
TWPS Timer write pending status
TMAR Timer match
TCAR Timer capture
TSICR Timer synchronization interface control
42 Timers
Table 32 lists the 32-bit (or 2 x 16-bit) dual-mode timer registers. Table 33
through Table 46 describe the individual register bits. The registers are
accessible in 16-bit mode and use little-endian addressing.
Offset
LSB
R/W
R 0x00
0x04
0x08
0x0C
R/W 0x10
R 0x14
R/W 0x18
R/W 0x1C
R/W 0x20
R/W 0x24
R/W 0x28
R/W 0x2C
R/W 0x30
R 0x34
R/W 0x38
R 0x3C
R/W 0x40
SPRU759B
Offset
MSB
0x02
0x06
0x0A
0x0E
0x12
0x16
0x1A
0x1E
0x22
0x26
0x2A
0x2E
0x32
0x36
0x3A
0x3E
0x42