Table of Contents
Advertisement
System Test Enable (ST_EN)
Free Running Mode After Breakpoint (FREE)
Test Mode Select (TMODE)
SPRU760B
This register facilitates system-level tests by overriding some of the standard
functional features of the peripheral. It can permit the test of SCL counters,
control the signals that connect to I/O pins, or create digital loopback for
self-test when the module is configured in system test (SYSTEST) mode. It
also provides stop/no-stop functionality in debug mode.
This bit must be set to 1 to permit other system test registers bits to be set.
0: Normal mode
-
1: System test enabled
-
Value after reset is low.
This bit determines the state of the I
encountered in the HLL debugger.
This bit can be set independently of the ST_EN value.
2
FREE = 0: If the I
C controller is a master, it stops immediately after the
completion of the ongoing bit transfer. If the I
during the data phase transfer when one byte is completely transmitted/
received.
2
FREE = 1: The I
C runs free.
0: Stop mode (on breakpoint condition)
-
1: Free running mode
-
Value after reset is low.
In normal functional mode (ST_EN = 0), these bits are don't care. They always
read as 00 and a write is ignored.
In system test mode (ST_EN = 1), these bits can be set according to the
following table to permit various system tests (see Table 37).
I2C Multimaster Peripheral
2
C controller when a breakpoint is
2
C controller is a slave, it stops
Serial Interfaces
85
Advertisement
Chapters
Table of Contents
