Writing Timer Registers; Software Write Posting Synchronization Mode; Software Non-Write Posting Synchronization Mode - Texas Instruments OMAP5912 Reference Manual

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Dual-Mode Timer

Writing Timer Registers

This mode is used if TSCR (POSTED bit) is set to 1 in the timer control register.

It uses a posted write scheme for updating any internal register. This means

that the write transaction is immediately acknowledged on the OCP interface,

although the effective write operation occurs later, because of a

resynchronization in the timer clock domain. The advantage is that neither the

interconnect nor the CPU that requested the write transaction is stalled. For

each register, a status bit is provided that is set if there is a pending write

access to the register.

In this mode, it is mandatory that the CPU check this status bit prior to any write

access. In case a write is attempted to a register with a previous access

pending, the previous access is discarded without notice.

There is one status bit per register, accessible in the timer write-posted status

The timer module updates the timer counter register value synchronously with

the OCP clock. Consequently, any read access to the timer counter register

does not add any resynchronization latency; the current value is always

If a write access is pending for a register, reading from this register does not

yield a correct result. Software synchronization must be used to avoid

incorrect results.

The drawback of this automatic update mechanism is that it assumes a given

relationship between the timer interface frequency and the timer clock

Functional frequency range: freq(timer clock ) ≤ freq(host peripheral clock)/4

This mode is used if TSCR (POSTED bit) is set to 0 in the timer control register.

This mode uses a non-posted write scheme for updating any internal register.

This means that the write transaction is not acknowledged on the OCP

interface until the effective write operation occurs, after the resynchronization

in the timer clock domain. The drawback is that both the interconnect and the

CPU are stalled during this period.

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