Going To Sleep; Smart Idle Mode; Force Wake-Up Mode; Waking Up - Texas Instruments OMAP5912 Reference Manual

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Interrupt Controllers (MPU Level 2 and DSP Level 2.1)

Going to Sleep

The procedure used for going to sleep depends on the IDLE_MODE value.

In SMART_IDLE mode, when the IDLE_REQ signal is asserted (high level),

the interrupt handler goes into an idle state on the next functional clock cycle,

if no IRQ/FIQ is currently pending. If incoming interrupts are pending, they are

processed before going into idle state. As long as the interrupt controller is in

idle state, all incoming interrupts are ignored but still stored into the ITR

As soon as it is ensured that no IRQ/FIQ will be generated, the interrupt

controller asserts the IDLE_ACK signal.

Upon receiving the IDLE_ACK signal, the power management is aware that

no more interrupts are currently being processed and that clocks can safely

be turned off.

In force wake-up mode, when the IDLE_REQ signal is asserted, the interrupt

controller asserts IDLE_ACK on the next OCP clock cycle regardless of the

state of the current incoming interrupt and of any interrupt possibly being

processed. It immediately masks all incoming interrupts and deasserts the

IRQ/FIQ signal.

When the system wakes up, power management turns the clocks on again,

and then deasserts the IDLE_REQ signal. At that moment, the interrupt

controller becomes aware that its clocks are turned on. It deasserts IDLE_ACK

and comes out of idle state. From this point on, IRQ/FIQ generation becomes

possible again.

When the system is asleep, the interrupt controller functional clock is shut off,

the interrupt controller is in idle state, and IRQ/FIQ generation is no longer

possible. However, in this case, a dedicated asynchronous path is activated

in the interrupt controller to propagate interrupts to the clock manager.

Whenever the interrupt controller is idle, and an unmasked interrupt occurs,

the interrupt controller asynchronously asserts a wakeup signal. Basically, this

signal is an OR of all unmasked ITR bits. This signal notifies the clock manager

that an external wake-up event has occurred.

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