Functional Description - Texas Instruments OMAP5912 Reference Manual

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
2.1

Functional Description

20 Interrupts
The interrupt controller can be programmed to assign different priorities and
mask each interrupt independently. Each interrupt line can be programmed to
be either level sensitive or edge triggered. The interrupt handler also provides
an asynchronous signal to the host in order to have a way to wake up the
system, in case an interrupt occurs when the clocks are turned off (system in
idle state). See Figure 2 for the interrupt controller block diagram.
The interrupt controller provides prioritized and maskable interrupts to the
host.
One interrupt level register (ILR) is associated with each incoming interrupt.
It assigns a priority to the corresponding interrupt, determines whether it is to
be level or edge sensitive, and selects which interrupt (FIQ or IRQ) it is to
generate. If several interrupts have the same priority level, they are serviced
in a predefined order (see Table 13).
For test purposes, the interrupt controller provides a set of software interrupt
set registers (SISR). Each bit of these registers corresponds to an incoming
interrupt line. By writing a1 to the targeted bit, an interrupt is generated if the
corresponding ILR is set to edge sensitive. External interrupt requests and
internal software requests are merged before being sent to the interrupt
controller state machine.
Each incoming interrupt is routed either to the FIQ or the IRQ interrupt. The
IRQ or FIQ outputs from the interrupt controller are reset by writing a 1 to the
corresponding bit of the control register. Both the IRQ and FIQ are
synchronous to the interrupt controller functional clock.
The interrupt handler can wake up the host asynchronously even if the
functional clocks are turned off (host in idle state).
SPRU757B