Texas Instruments TMS320DM355 Instruction
Texas Instruments TMS320DM355 Instruction

Texas Instruments TMS320DM355 Instruction

Texas instruments digital media system-on-chip (dmsoc) product preview
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1 TMS320DM355 Digital Media System-on-Chip (DMSoC)

1.1 Features

High-Performance Digital Media
System-on-Chip
– 216- and 270-MHz ARM926EJ-S Clock Rate
– Fully Software-Compatible With ARM9
ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
– DSP Instruction Extensions and Single
Cycle MAC
– ARM Jazelle Technology
– EmbeddedICE-RT Logic for Real-Time
Debug
ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
– Little Endian
Video Processing Subsystem
– Front End Provides:
Hardware IPIPE for Real-Time Image
Processing
CCD and CMOS Imager Interface
14-Bit Parallel AFE (Analog Front End)
Interface Up to 67.5 MHz
Glueless Interface to Common Video
Decoders
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Histogram Module
Resize Engine
– Resize Images From 1/16x to 8x
– Separate Horizontal/Vertical Control
– Two Simultaneous Output Paths
– Back End Provides:
Hardware On-Screen Display (OSD)
Composite NTSC/PAL video encoder
output
8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Supports digital HDTV (720p/1080i)
output for connection to external
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
2
I
C-bus is a trademark of Texas Instruments.
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
encoder
External Memory Interfaces (EMIFs)
– DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
– Asynchronous16-/8-bit Wide EMIF (AEMIF)
Flash Memory Interfaces
– NAND (8-/16-bit Wide Data)
– OneNAND(16-bit Wide Data)
Flash Card Interfaces
– Two Multimedia Card (MMC) / Secure
Digital (SD/SDIO)
– SmartMedia
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY
that Supports
– USB 2.0 Full and High-Speed Device
– USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and
CTS Flow Control)
Three Serial Port Interfaces (SPI) each with
two Chip-Selects
One Master/Slave Inter-Integrated Circuit
2
(I
C) Bus™
Two Audio Serial Port (ASP)
– I2S and TDM I2S
– AC97 Audio Codec Interface
– S/PDIF via Software
– Standard Voice Codec Interface (AIC12)
– SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically
24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
Copyright © 2007–2007, Texas Instruments Incorporated
TMS320DM355

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  • Page 1: Features

    All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Digital Media System-on-Chip (DMSoC) SPRS463A –...
  • Page 2 Boundary-Scan-Compatible – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory – Device Revision ID Readable by ARM TMS320DM355 Digital Media System-on-Chip (DMSoC) 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch 90nm Process Technology 3.3-V and 1.8-V I/O, 1.3-V Internal Submit Documentation Feedback www.ti.com...
  • Page 3: Description

    Windows™ debugger interface for visibility into source code execution. Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 TMS320DM355 Digital Media System-on-Chip (DMSoC) TMS320DM355...
  • Page 4: Functional Block Diagram

    VPBE VPSS Enhanced MPEG/JPEG Coprocessor channels 3PCC /TC (100 MHz 64bit DMA/Data Bus 32bit Configuration Bus TMS320DM355 Digital Media System-on-Chip (DMSoC) IPIP LD / Enhanced Enhanced DMA 64 channels channels 3PCC /TC (100 MHz / Data and configuration bus DMA/Data and configuration bus...
  • Page 5: Table Of Contents

    TMS320DM355 Digital Media System-on-Chip (DMSoC) Features Description Functional Block Diagram Device Overview Device Characteristics Memory Map Summary Pin Assignments Pin Functions Pin List Device Support Detailed Device Description ARM Subsystem Overview ARM926EJ-S RISC CPU Memory Mapping ARM Interrupt Controller (AINTC)
  • Page 6: Device Characteristics

    Production Data (PD) (1) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Device Overview www.ti.com...
  • Page 7: Memory Map Summary

    DDR EMIF 1792M Reserved Address Start 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 9FFF 0x01C1 FFFF 0x01C2 03FF TMS320DM355 Digital Media System-on-Chip (DMSoC) Table 2-3 depicts the expanded map of EDMA Mem Map Mem Map Reserved Reserved ARM RAM0 ARM RAM0...
  • Page 8 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) UART1 0x01C2 0400 Timer4/5 0x01C2 0800 Real-time out 0x01C2 0C00 0x01C2 1000 Timer0/1 0x01C2 1400 Timer2/3 0x01C2 1800...
  • Page 9: Pin Assignments

    COUT2 SS_USB USB_ID SS_USB USB_DRV DDD13_USB VBUS DDA33_USB_ YOUT5 YOUT6 USB_DM Figure 2-1. Pin Map [Quadrant A] TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 VREF DDA33_USB SSA_PLL2 DDA13_USB DDA_PLL2 DD_VOUT DD_VOUT EMU1 EMU0 USB_R1...
  • Page 10 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DDR_A02 DDR_A03 DDR_A00 DDR_A01 MXO2 PCLK MXI2 YIN3 YIN1 YIN4 SS_MX2 RSV05 CIN7 RSV04 RSV06 CIN5 RSV03 CIN1 RSV02 RSV07 Device Overview DDR_A05 DDR_A08 DDR_A09 DDR_A11 DDR_A04...
  • Page 11 DDR_DQ08 DD_DDR UART1_RXD I2C_SDA I2C_SCL EM_A04 DD_DDR DD_DDR EM_A02 EM_D13 EM_D04 Figure 2-3. Pin Map [Quadrant C] TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DDR_DQ13 DDR_DQ15 DDR_GATE0 DDR_DQ14 DDR_GATE1 EM_A13 DDR_DQ12 UART0_RXD EM_A12 UART0_TXD...
  • Page 12 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SSA_PLL1 DDA_PLL1 RTCK SPI1_SDO RESET CLKOUT1 SPI0_SCLK CLKOUT3 SS_MX1 SPI0_ SPI0_SDO SDENA[0] SPI0_SDI CLKOUT2 Device Overview EM_WE EM_CE0 ASP0_DX EM_ADV GIO003 ASP0_FSR GIO002 SPI1_ ASP1_FSX GIO001 SDENA[0]...
  • Page 13: Pin Functions

    SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 through Table 2-22) identify the external signal names, the associated Section 2.5 16-BIT YCbCr Cb7,Cr7 Cb6,Cr6 Cb5,Cr5 Cb4,Cr4 Cb3,Cr3 Cb2,Cr2 Cb1,Cr1 Cb0,Cr0 TMS320DM355 8-BIT YCbCr Y7,Cb7,Cr7 Y6,Cb6,Cr6 Y5,Cb5,Cr5 Y4,Cb4,Cr4 Y3,Cb3,Cr3 Y2,Cb2,Cr2 Y1,Cb1,Cr1 Y0,Cb0,Cr0 Y7,Cb7,Cr7 Y6,Cb6,Cr6 Y5,Cb5,Cr5 Y4,Cb4,Cr4...
  • Page 14 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL TYPE OTHER NAME CIN7/ GIO101/ I/O/Z SPI2_SCLK CIN6/ GIO100/ I/O/Z SPI2_SDO CIN5/ GIO099/ I/O/Z SPI2_SDEN A[0] CIN4/ GIO098/ I/O/Z...
  • Page 15 CCDC handles 1- or 2-field sensors in DD_VIN hardware. GIO: GIO[083] Pixel clock input (strobe for lines C17 through Y10) GIO: GIO[0082] DD_VIN Table 2-7 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Device Overview...
  • Page 16 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 HSYNC HSYNC GIO073 VSYNC VSYNC GIO072 LCD_OE As needed GIO071 FIELD As needed GIO070 PWM3C EXTCLK As needed...
  • Page 17 Digital Video Out: B2 PWM3D Video Encoder: Video Output Clock DD_VOUT GIO: GIO[068] Section 5.3, Power Supplies for more detail. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to 50 damping resistors are recommend on the Device Overview...
  • Page 18 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE OTHER NAME VREF A I/O/Z IOUT A I/O/Z IBIAS A I/O/Z A I/O/Z TVOUT A I/O/Z DDA18_DAC SSA_DAC (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply voltage for each signal.
  • Page 19 GIO: GIO[041] Async EMIF: Data bus bit 02 GIO: GIO[040] Async EMIF: Data bus bit 01 GIO: GIO[039] Async EMIF: Data bus bit 00 GIO: GIO[038] TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 20 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE OTHER NAME EM_CE0/ I/O/Z GIO037 EM_CE1/ I/O/Z GIO036 EM_WE/ I/O/Z GIO035 EM_OE/ I/O/Z GIO034 EM_WAIT/ I/O/Z GIO033 EM_ADV/...
  • Page 21 DD_DDR DDR: Reference output for drive strength calibration of N and P channel outputs. DD_DDR Tie to ground via 50 ohm resistor @ 0.5% tolerance. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 22 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.5 GPIO The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions. TERMINAL TYPE OTHER NAME...
  • Page 23 (example: flash), OneNand or NAND memory. Used for the default boot and ROM boot modes. GIO: GIO[037] Async EMIF: Data Bus bit[00] GIO: GIO[038] TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 24 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE OTHER NAME EM_D01 / I/O/Z GIO039 EM_D02 / I/O/Z GIO040 EM_D03 / I/O/Z GIO041 EM_D04 / I/O/Z GIO042 EM_D05 /...
  • Page 25 RTO3 Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C DD_VOUT RTO2 Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B DD_VOUT RTO1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 26 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE OTHER NAME COUT5- G2 / GIO079 / I/O/Z PWM2A / RTO0 COUT6- G3 / I/O/Z GIO080 / PWM1 COUT7-...
  • Page 27 DD_VIN the upper channel. Y/CB/CR[07] SPI: SPI2 Clock GIO: GIO[101] SPI0: Data In GIO: GIO[102] SPI0: Chip Select 0 GIO: GIO[103] TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 28 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol. TERMINAL TYPE OTHER...
  • Page 29: Universal Serial Bus (Usb) Interface

    Table 2-14. ASP Terminal Functions (2) (3) OTHER DESCRIPTION ASP0: Receive Clock GIO: GIO[026] Section 5.3, Power Supplies for more detail. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SS_USB SS_USB SS_USB SS_USB SS_USB SS_USB...
  • Page 30: Uart Interface

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-14. ASP Terminal Functions (continued) TERMINAL TYPE OTHER NAME ASP0_CL KX / I/O/Z GIO029 ASP0_DR I/O/Z GIO027 ASP0_DX I/O/Z GIO030 ASP0_FS I/O/Z GIO025 ASP0_FS I/O/Z GIO028...
  • Page 31: Serial Interface

    MMC/SD power control) SPI1: Data in or I/O/Z SPI1: Chip select GIO: GIO[09] SPI1: Data out I/O/Z GIO: GIO[008] Section 5.3, Power Supplies for more detail. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 32: Clock Interface

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-17. SPI Terminal Functions (continued) TERMINAL TYPE NAME CIN7/ GIO101/ SPI2_SCLK CIN5/ GIO099/ SPI2_SDENA[0] CIN4/ GIO098/ SPI2_SDI/ SPI2_SDENA[1] CIN6/ GIO100/ SPI2_SDO/ 2.4.12 Clock Interface The provides interface with the system clocks.
  • Page 33 Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A DD_VOUT RTO0 Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B DD_VOUT RTO1 Section 5.3, Power Supplies for more detail. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 34: System Configuration Interface

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-20. PWM Terminal Functions (continued) TERMINAL TYPE OTHER NAME COUT3- B6 / GIO077 / I/O/Z PWM2C / RTO2 COUT2- B5 / GIO076 / I/O/Z PWM2D /...
  • Page 35 EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected) EMU[1:0] = 11 - Normal Scan chain (ICEpick only) Section 5.3, Power Supplies for more detail. TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Device Overview...
  • Page 36: Pin List

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.5 Pin List Table 2-23 provides a complete pin description list in pin number order. Name Type Group CIN7 / GIO101 / CCDC SPI2_SCLK / GIO /...
  • Page 37 YCC 16-bit: time multiplexed between luma: Y[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[092] TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX0[8].CIN_32 PINMUX0[8].CIN_32 PINMUX0[9].CIN_10 PINMUX0[9].CIN_10...
  • Page 38 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group YIN5 / GIO091 CCDC / GIO YIN4 / GIO090 CCDC / GIO YIN3 / GIO089 CCDC / GIO...
  • Page 39 Digital Video Out: VENC settings determine DD_VOUT function GIO: GIO[081] PWM0 Digital Video Out: VENC settings determine DD_VOUT function GIO: GIO[080] PWM1 TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX0[12].CAM_ PINMUX0[13].CAM_ plus CCDC.MODE[7].CC DMD & CCDC.MODE[5].SW PINMUX1[1:0].COU PINMUX1[3:2].COU...
  • Page 40 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group COUT5-G2 / VENC GIO079 / / GIO / PWM2A / RTO0 PWM2 / RTO COUT4-B7 / VENC GIO078 /...
  • Page 41 Data strobe input/outputs for each byte of DD_DDR the 16 bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DQS1: For DDR_DQ[15:8] TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX1[19:18].FI PINMUX1[21:20].EX PINMUX1[22].VCLK...
  • Page 42 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group DDR_DQS[0] DDR_BA[2] DDR_BA[1] DDR_BA[0] DDR_A13 DDR_A12 DDR_A11 DDR_A10 DDR_A09 DDR_A08 DDR_A07 DDR_A06 DDR_A05 DDR_A04 DDR_A03 DDR_A02 DDR_A01 DDR_A00...
  • Page 43 Async EMIF: Address Bus bit[10] GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 Definition (00: EM_BA0, 01: EM_A14, 10:GIO[054], 11:rsvd) TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX2[0].EM_A1 3_3, default set by AECFG[0] PINMUX2[0].EM_A1...
  • Page 44 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group EM_A09 / AEMI GIO063 / AECFG[1] GIO / syste EM_A08 / AEMI GIO062 / AECFG[0] GIO / syste...
  • Page 45 Async EMIF: Data Bus bit[13] GIO: GIO[051] Async EMIF: Data Bus bit[12] GIO: GIO[050] Async EMIF: Data Bus bit[11] GIO: GIO[049] Async EMIF: Data Bus bit[10] GIO: GIO[048] TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX2[1].EM_A0 _BA1, default set by AECFG[0] PINMUX2[1].EM_A0...
  • Page 46 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group EM_D09 / AEMI GIO047 EM_D08 / AEMI GIO046 EM_D07 / AEMI GIO045 EM_D06 / AEMI GIO044 EM_D05 /...
  • Page 47 GIO: GIO[028] ASP0: Receive Data GIO: GIO[027] ASP0: Receive Clock GIO: GIO[026] ASP0: Receive Frame Synch GIO: GIO[025] MMCSD1: Clock GIO: GIO[024] MMCSD1: Command GIO: GIO[023] TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX2[8].EM_W E_OE PINMUX2[8].EM_W E_OE PINMUX2[9].EM_W PINMUX2[10].EM_A PINMUX2[11].EM_C PINMUX3[0].GIO30...
  • Page 48 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group MMCSD1_DAT A3 / GIO022 / SD / UART2_RTS GIO / UART MMCSD1_DAT A2 / GIO021 / SD /...
  • Page 49 For Host mode operation only, pull down this pin to ground (VSS) with a 1.5K ohm resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control PINMUX3[24].GIO1 PINMUX3[26:25].GI PINMUX3[27].GIO8...
  • Page 50 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group USB_VBUS A I/O USBP USB_DRVVBU USBP GND USBP SS_USB_REF PWR USBP DDA33_USB GND USBP SS_USB PWR USBP DDA33_USB_PLL...
  • Page 51 EMU[1:0] = 11 - Normal Scan chain (ICEpick only) Reserved. This signal should be left as a No Connect or connected to V Reserved. This signal should be left as a No Connect or connected to V TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control Device Overview...
  • Page 52 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group RSV03 I/O/Z RSV04 I/O/Z RSV05 I/O/Z RSV06 RSV07 DD_VIN DD_VIN DD_VIN DD_VOUT DD_VOUT DD_VOUT DD_DDR DD_DDR DD_DDR DD_DDR...
  • Page 53 Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground TMS320DM355 Digital Media System-on-Chip (DMSoC) Description Mux Control Device Overview...
  • Page 54 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Type Group Device Overview Power Reset Supply State Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground...
  • Page 55: Device Support

    DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., ). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
  • Page 56 (for example, ZCE), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The following figure provides a legend for reading the complete device name for any TMS320DM355 DMSoC platform member.
  • Page 57 When configured as an output, you can write to an internal register to control the state driven on the output pin. Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DMSoC Universal Asynchronous general-purpose input/output TMS320DM355 Receiver/Transmitter (UART) (GPIO) peripheral Device Overview...
  • Page 58 System-on-Chip (DMSoC). SPRUFC8 TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are not available by literature number. Copies of these documents are available (by title only) on the internet at www.ti.com.
  • Page 59: Detailed Device Description

    Audio Serial Port (ASP) Universal Serial Bus Controller (USB) Serial Port Interface (SPI) Video Processing Front End (VPFE) – CCD Controller (CCDC) Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Detailed Device Description...
  • Page 60: Arm926Ej-S Risc Cpu

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – Image Pipe (IPIPE) – H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure) Video Processing Back End (VPBE) – On Screen Display (OSD) –...
  • Page 61: Caches And Write Buffer

    Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Detailed Device Description...
  • Page 62 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines.
  • Page 63: External Memories

    VPSS - INT0, Configurable via VPSSBL register: INTSEL VPSS - INT1 VPSS - INT2 VPSS - INT3 VPSS - INT4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Acronym Source TINT0 Timer 0 - TINT12 TINT1...
  • Page 64 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-1. AINTC Interrupt Connections (continued) Interrupt Acronym Number VPSSINT5 VPSSINT6 VPSSINT7 VPSSINT8 Reserved Reserved Reserved USBINT RTOINT or TINT4 UARTINT2 or TINT5 TINT6 CCINT0 SPINT1-0 or...
  • Page 65: Device Clocking

    PLL2 generates the clock required by the DDR PHY. A block diagram of DM355's clocking architecture is shown in Figure Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5-1. The PLLs are described further in TMS320DM355 Section 3.6. Detailed Device Description...
  • Page 66 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 BPDIV (/3) Reference clock (MXI/MXO) AUXCLK (/1) 24 MHz or 36 Mhz PLLDIV1 (/2) PLLDIV2 (/4) PLLDIV3 (/n) PLLDIV4 (/4 or /2) PLL controller 1 PCLK EXTCLK...
  • Page 67 74.25 67.5 121.5 60.75 94.5 47.25 40.5 POSTDIV PLL2 VCO (/1 fixed) (MHz) bypass bypass TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Venc VPSS PLLDIV3 SYSCL PLLDIV4 (/4 or /2 programma (MHz) programmable ble)
  • Page 68 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.2.2 Supported Clocking Configurations for DM355-216 (36 MHz reference) 3.5.2.2.1 DM355-216 PLL1 (36 MHz reference) All supported clocking configurations for DM355-216 PLL1 with 36 MHz reference clock are shown in Table 3-4 Table 3-4.
  • Page 69 74.25 67.5 121.5 60.75 94.5 47.25 40.5 POSTDIV PLL2 VCO (/1 fixed) (MHz) bypass bypass TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Venc VPSS PLLDIV3 SYSCLK PLLDIV4 (/2 fixed) programmable) (MHz) DDR PHY PLLDIV1...
  • Page 70 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-7. PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference) (continued) PREDIV PLLM 3.5.3.2 Supported Clocking Configurations for DM355-270 (36 MHz reference) 3.5.3.2.1 DM355-270 PLL1 (36 MHz reference)
  • Page 71 PLL1 SYSCLK3 EXTCLK pin (external VPBE clock input pin) PCLK pin (VPFE pixel clock input pin) See the TMS320DM355 DMSoC Video Processing Back End (VPBE) User's Guide for complete information on VPBE clocking. 3.5.4.2 USB Clocking The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of the USB PHY.
  • Page 72 USB PHY. The USB PHY is capable of accepting only 24 MHz and 12 MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM355 DMSoC Univeral Serial Bus (USB) Controller User's Guide (SPRUED2) for more information. See the TMS320DM355 DMSoC ARM Subsystem User's Guide for more information on the System Control Module.
  • Page 73: Pll Controller (Pllc)

    3.6 PLL Controller (PLLC) This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM355 Digital Media System-on-Chip ARM Subsystem User's Guide for more information on the PLL controllers. 3.6.1 PLL Controller Module The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller 1 (PLLC1) provides clocks to most of the components of the chip.
  • Page 74 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.6.2 PLLC1 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, DM355. Provides primary DM355 system clock Software configurable...
  • Page 75 OSCIN Submit Documentation Feedback PLLEN Post-DIV (/2 or /1) PLLM (programmable) Figure 3-3. PLLC1 Configuration In DM355 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SYSCLK1 (ARM and MPEG/JPEG PLLDIV1 (/2) Coprocessor) SYSCLK2 PLLDIV2 (/4)
  • Page 76 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.6.3 PLLC2 PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the PLLC2 registers. The following list, the DM355. Provides DDR PHY clock and CLKOUT3...
  • Page 77: Power And Sleep Controller (Psc)

    – DDR VTP control – Clockout circuitry – GIO de-bounce control Submit Documentation Feedback SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC clks Interrupt Always on domain TMS320DM355 Digital Media System-on-Chip (DMSoC) Figure 3-5. Many of DMSoC arm_clock arm_mreset arm_power AINTC MODx...
  • Page 78: Pin Multiplexing

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Power management – Deep sleep and fast NAND boot control Bandwidth Management – Bus master DMA priority control For more information on the System Control Module refer to the ARM Subsystem User's Guide.
  • Page 79: Device Reset

    Same effect as warm reset. Resets all modules except memory and ARM emulation. It is a soft reset that maintains memory contents and does not affect or reset clocks or power states. TMS320DM355 0010 (16-bit SRAM) 0000 EM_A[14] EM_BA[0] EM_BA[1]...
  • Page 80: Default Device Configurations

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Type Initiator Module Reset ARM software 3.11 Default Device Configurations After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.
  • Page 81: Pll Configuration

    Subsystem User's Guide. Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16 as shows that the following modules are enabled depending on the TMS320DM355 Section 3.5 shows which modules are Detailed Device Description...
  • Page 82 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Module Module Name Number VPSS Master VPSS Slave EDMA (CC) EDMA (TC0) EDMA (TC1) Timer3 SPI1 MMC/SD1 ASP1 PWM3 SPI2 DDR EMIF AEMIF MMC/SD0 Reserved UART0 UART1...
  • Page 83: Device Boot Modes

    SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn AlwaysOn Reserved Reserved Always On NOTE Section 3.12. TMS320DM355 Default States Enable Enable Enable Enable Enable Enable Enable Enable Reserved SyncRst Section 3.9. Detailed Device Description...
  • Page 84 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0] = 01, indicating AEMIF (AEMIF/OneNand) boot.
  • Page 85: Power Management

    3-6. For more information, refer to the ARM Subsystem Reset Boot mode Internal ROM Boot mode Boot from NAND flash Boot OK ? Boot from MMC/SD Boot OK ? Invoke loaded Program TMS320DM355 Digital Media System-on-Chip (DMSoC) Boot from UART Boot OK ? Detailed Device Description...
  • Page 86 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be avoided by removing power completely from a device or subsystem.
  • Page 87: 64-Bit Crossbar Architecture

    – MMC/SD Submit Documentation Feedback SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-18 Table 3-18. Crossbar Connection Matrix Slave Module MPEG/JPEG Config Bus Registers and Co-processor Memory Memory TMS320DM355 Digital Media System-on-Chip (DMSoC) DDR EMIF Memory Detailed Device Description...
  • Page 88 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event interface for the EDMA system.
  • Page 89 ASP1 Receive Event or Timer 2 interrupt (TINT5) Event SPI2 Transmit Event SPI2 Receive Event SPI1 Transmit Event SPI1 Receive Event SP0I Transmit Event SPI0 Receive Event UART 0 Receive Event UART 0 Transmit Event UART 1 Receive Event Detailed Device Description TMS320DM355...
  • Page 90: Mpeg/Jpeg Overview

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-19. EDMA Channel Synchronization Events (continued) EDMA EVENT NAME CHANNEL UART1: UTXEVT1 UART2: URXEVT2 UART2: UTXEVT2 Reserved GPIO: GPINT9 MMC0RXEVT or MEMSTK: MSEVT MMC0TXEVT I2CREVT I2CXEVT...
  • Page 91: Sprs463A – September 2007 – Revised September

    All analog 1.8 V supplies All 3.3 V supplies All 1.8 V I/Os All 3.3 V I/Os VBUS clamp TMS320DM355 Digital Media System-on-Chip (DMSoC) -0.5 V to 1.7 V -0.5 V to 2.5 V -0.5 V to 1.89 V -0.5 V to 4.4 V -0.5 V to 2.3 V...
  • Page 92: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 4.2 Recommended Operating Conditions DDA_PLL1 DDA_PLL2 DDD13_USB DDA13_USB DDA33_USB Supply Voltage DDA33_USB_PLL DD_DDR DDA33_DDRDLL DD_VIN DD_VOUT DDA18_DAC SSA_PLL1 SSA_PLL2 SS_USB Supply Ground SSA_DLL SSA_DAC SS_MX1 SS_MX2 Voltage Input High...
  • Page 93: Ranges Of Supply Voltage And Operating Case Temperature (Unless Otherwise Noted)

    = VSS to VDD = VDD or VSS; internal pull disabled RLOAD = 499 , Video buffer disabled RLOAD = 499 , Video buffer disabled IFS = 1.4 mA, RLOAD = 499 TMS320DM355 UNIT -190 -100 4000 Bits 0.700 1.55 0.470 Section 2.4 Section 2.5...
  • Page 94: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5 Peripheral Information and Electrical Specifications Parameter Information Device-Specific Information 42 Ω 3.5 nH 4.0 pF 1.85 pF The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
  • Page 95: Submit Documentation Feedback

    Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Peripheral Information and Electrical Specifications...
  • Page 96: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals should transition between V monotonic manner. 5.3 Power Supplies The power supplies of DM355 are summarized in...
  • Page 97: Submit Documentation Feedback

    DDA33_USB DDA33_USB_PLL DDA33_DDRDLL DDA33_USB DDA33_USB_PLL DDA18 DDA18_DAC DDA_PLL1/2 DDD13_USB DDA13_USB Section 5.5.2 for additional recommendations on power supplies Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DD_VIN DD_VOUT DD_VIN DD_VOUT...
  • Page 98: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.4 Reset 5.4.1 Reset Electrical Data/Timing Table 5-2. Timing Requirements for Reset Active low width of the RESET pulse w(RESET) Setup time, boot configuration pins valid before RESET rising edge...
  • Page 99: Submit Documentation Feedback

    5-5. The external crystal load capacitors must be ). Do not connect to board ground (V SS_MX1 MXO1 SS_MX1 DDA_PLL1 Figure 5-5. MXI1 (24-MHz) Oscillator pin. SS_MX1 Peripheral Information and Electrical Specifications TMS320DM355 ). Also, the PLL SSA_PLL1 0.1 F...
  • Page 100: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-3. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System PARAMETER Start-up time (from power up until oscillating at stable frequency) Oscillation frequency Frequency stability 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) The MXI2 (27 MHz) oscillator provides an optional reference clock for the 's VPSS module.
  • Page 101: Submit Documentation Feedback

    SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (1) (2) MAX and V Figure 5-7. MXI1/CLKIN1 Timing (1) (2) 37.037 MAX and V Figure 5-8. MXI2/CLKIN2 Timing Peripheral Information and Electrical Specifications TMS320DM355 (see Figure 5-7) DM355 27.7 41.6 0.45C 0.55C 0.45C...
  • Page 102: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 PARAMETER Cycle time, CLKOUT1 C(CLKOUT1) Pulse duration, CLKOUT1 high w(CLKOUT1H) Pulse duration, CLKOUT1 low w(CLKOUT1L) Transition time, CLKOUT1...
  • Page 103: Submit Documentation Feedback

    MXI/CLKIN CLKOUT3 Submit Documentation Feedback SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-11) MAX and V Figure 5-11. CLKOUT3 Timing Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) (1) (2) DM355 c(MXI1) 0.45P 0.55P 0.45P 0.55P 0.05P...
  • Page 104: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.6 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin.
  • Page 105: Submit Documentation Feedback

    EXT_INTx Submit Documentation Feedback Figure 5-12. GPIO Port Timing Figure 5-13. GPIO External Interrupt Timing Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (see Figure 5-13)
  • Page 106: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7 External Memory Interface (EMIF) supports several memory and external device interfaces, including: Asynchronous EMIF (AEMIF) for interfacing to SRAM. OneNAND flash memories NAND flash memories 5.7.1 Asynchronous EMIF (AEMIF) The EMIF supports the following features: SRAM, etc.
  • Page 107: Submit Documentation Feedback

    MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more information.
  • Page 108: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see PARAMETER Output setup time, EM_BA[1:0] valid to su(EMBAV-EMOEL) EM_OE low Output hold time, EM_OE high to...
  • Page 109: Submit Documentation Feedback

    EM_A[13:0] EM_WE EM_D[15:0] EM_OE Figure 5-15. Asynchronous Memory Write Timing for EMIF Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-14 Figure 5-15) (continued) DM355 (WH)*E Peripheral Information and Electrical Specifications TMS320DM355...
  • Page 110: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SETUP EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_OE EM_WAIT Figure 5-16. EM_WAIT Read Timing Requirements SETUP EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_WE EM_WAIT Figure 5-17. EM_WAIT Write Timing Requirements Peripheral Information and Electrical Specifications...
  • Page 111: Submit Documentation Feedback

    EM_A[13:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT Figure 5-18. Synchronous OneNAND Flash Read Timing Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Da+1 Da+2 Da+3 Peripheral Information and Electrical Specifications TMS320DM355 Da+n+1 Da+4 Da+5 Da+n...
  • Page 112: Submit Documentation Feedback

    TI only supports DDR2/mDDR board designs that follow the guidelines described in the application note titled TMS320DM355 DDR2 / mDDR Board Design Application Note. Refer to this application note for information on board design recommendations and guidelines for DDR2 and mDDR.
  • Page 113: Submit Documentation Feedback

    Submit Documentation Feedback (see Figure 5-20 Figure (see Figure 5-19 through Figure PARAMETER Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5-22) DM355 FAST MODE STANDARD MODE 5-22) DM355 STANDARD...
  • Page 114: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SD_CLK START SD_CMD Figure 5-19. MMC/SD Host Command Timing SD_CLK START XMIT SD_CMD Figure 5-20. MMC/SD Card Response Timing SD_CLK START SD_DATx SD_CLK Start SD_DATx Figure 5-22. MMC/SD Host Read and Card CRC Status Timing...
  • Page 115: Submit Documentation Feedback

    Fault pixel correction based on a lookup table that contains row and column position of the pixel to be corrected. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Peripheral Information and Electrical Specifications...
  • Page 116: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Support for program lens shading correction. Support for 10-bit to 8-bit A-law compression. Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output.
  • Page 117: Submit Documentation Feedback

    Separate vertical start co-ordinate and height for a black row of paxels that is different than the remaining color paxels. Programmable Horizontal Sampling Points in a window Programmable Vertical Sampling Points in a window Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Peripheral Information and Electrical Specifications...
  • Page 118: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.4 VPFE Electrical Data/Timing Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Cycle time, PCLK c(PCLK) Pulse duration, PCLK high w(PCLKH) Pulse duration, PCLK low...
  • Page 119: Submit Documentation Feedback

    Figure 5-25. VPFE (CCD) Master Mode Input Data Timing Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 8, 10 7, 9 11, 13 12, 14 Peripheral Information and Electrical Specifications TMS320DM355 (see Figure 5-25) DM355 UNIT...
  • Page 120: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Delay time, PCLK edge to HD invalid d(PCLKL-HDIV) Delay time, PCLK edge to VD invalid...
  • Page 121: Submit Documentation Feedback

    – ITU-R BT. 656 – Parallel RGB 16-bit/18-bit – Serial 8-bit RGB Low Pass Filter for Digital RGB Output Master/Slave Operation Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Peripheral Information and Electrical Specifications...
  • Page 122: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Internal Color Bar Generation (100%/75%) YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input 5.9.2.3 VPBE Electrical Data/Timing Table 5-21. Timing Requirements for VPBE CLK Inputs (see...
  • Page 123: Submit Documentation Feedback

    Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (1) (2) (3) PARAMETER Peripheral Information and Electrical Specifications TMS320DM355 (see Figure 5-29) DM355 UNIT 13.3...
  • Page 124 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK Cycle time, VCLK c(VCLK) Pulse duration, VCLK high w(VCLKH)
  • Page 125: Submit Documentation Feedback

    Configure the VDAC_CONFIG register in the system control module as follows: DINV = 0, PWD_GBZ = 1, PWD_VBUFZ = 0, ACCUP_EN = X. See theTMS320DM355 ARM Subsystem Reference Guide and the TMS320DM355 DMSoC Video Processing Back End (VPBE) User’s Guide for more information on VDAC_CONFIG. Figure 5-31. DAC Only Application Example...
  • Page 126: Submit Documentation Feedback

    1 (power up VREF), SPEED = 1 (faster), TVINT = don't care, PWD_VBUFZ = 1 (power up video buffer), VREFSET = don't care, ACCUP_EN = 0 (no A/C coupling), DINV = 1 (invert). See the TMS320DM355 ARM Subsystem Reference Guide and the TMS320DM355 DMSoC Video Processing Back End (VPBE) User's Guide for more information on the VDAC_CONFIG register and Video Buffer.
  • Page 127: Submit Documentation Feedback

    SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-33) LOW SPEED 1.5 Mbps 1250 – = 50 pF, High Speed: C = 50 pF Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) DM355 FULL SPEED HIGH SPEED 12 Mbps 480 Mbps 111.11 1500 –...
  • Page 128: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 USB_DM 10% V USB_DP Figure 5-33. USB2.0 Integrated Transceiver Interface Timing Figure 5-34. USB Reference Resistor Routing Peripheral Information and Electrical Specifications per − 90% V SS_USB_REF...
  • Page 129: Submit Documentation Feedback

    (1) U = UART baud time = 1/programmed baud rate. Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (see Figure 5-35) PARAMETER Peripheral Information and Electrical Specifications TMS320DM355 Figure 5-35) DM355 UNIT 0.99U 1.05U 0.99U 1.05U...
  • Page 130: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 UART_TXDn UART_RXDn Figure 5-35. UART Transmit/Receive Timing Peripheral Information and Electrical Specifications Start Data Bits Start Data Bits www.ti.com Submit Documentation Feedback...
  • Page 131: Submit Documentation Feedback

    (Clock Polarity = 0) SPIx_CLK (Clock Polarity = 1) Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-36. SPI_CLK Timing Peripheral Information and Electrical Specifications TMS320DM355 (see Figure 5-36) DM355 UNIT 37.037 ns 0.45*T 0.55*T...
  • Page 132: Submit Documentation Feedback

    Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge d(CLKH/L-ENH) (1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (SPRUED4). (2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (SPRUED4).
  • Page 133: Submit Documentation Feedback

    Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance d(CLKL/H-DOHz) (1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (SPRUED4). (2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (SPRUED4).
  • Page 134: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with Philips Semiconductors Inter-IC bus (I C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DM355 through the I2C module.
  • Page 135: Submit Documentation Feedback

    Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 C bus™ devices) C-bus™ system, but the requirement t Repeated Start Figure 5-39. I2C Receive Timings Peripheral Information and Electrical Specifications TMS320DM355 (see Figure 5-39) DM355 STANDARD FAST MODE MODE 1000 20 + 0.1C...
  • Page 136: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-34. Switching Characteristics for I2C Timings Cycle time, SCL c(SCL) Delay time, SCL high to SDA low (for a repeated START d(SCLH-SDAL) condition) Delay time, SDA low to SCL low (for a START and a repeated...
  • Page 137: Submit Documentation Feedback

    For more detailed information on the ASP peripheral, see the Documentation Support section for the Audio Serial Port (ASP) Reference Guide. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Peripheral Information and Electrical Specifications...
  • Page 138: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.14.1 ASP Electrical Data/Timing 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP tc(CLK) Cycle time, CLK OTG(CLKS) Pulse duration, CLKR/X high or CLKR/X low...
  • Page 139: Submit Documentation Feedback

    FSX ext Section 3.5) . Bit(n-1) Bit 0 Bit(n-1) Figure 5-41. ASP Timing Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 (3) (4) 38.5 or 2P C - 1 (n-2)
  • Page 140: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-37. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 0 (see Figure Setup time, DR valid before CLKX low su(DRV-CKXL) Hold time, DR valid after CLKX low h(CKXL-DRV) Table 5-38.
  • Page 141: Submit Documentation Feedback

    Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0 Submit Documentation Feedback 5-43) PARAMETER Section 3.5) . Bit(n-1) Bit(n-1) Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 MASTER (1) (2) MASTER 38.5 or (1) (3) C – 2 C + 3 T –...
  • Page 142: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-41. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 1 (see Figure Setup time, DR valid before CLKX high su(DRV-CKXH) Hold time, DR valid after CLKX high h(CKXH-DRV) Table 5-42.
  • Page 143: Submit Documentation Feedback

    Submit Documentation Feedback 5-45) 5-45) PARAMETER Section 3.5) . Bit(n-1) Bit(n-1) Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 MASTER (1) (2) MASTER 38.5 or (3) (3) D – 1 D + 3 T –...
  • Page 144: Submit Documentation Feedback

    Transition time, TIM_IN t(TIN) (1) GPIO000, GPIO001, GPIO002, and GPIO003 can be used as external clock inputs for Timer 3. See the TMS320DM355 DMSoC 64-bit Timer User's Guide for more information (SPRUEE5). (2) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
  • Page 145: Submit Documentation Feedback

    (1) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns. PWM0/1/2/3 Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (see Figure 5-47 Figure PARAMETER Figure 5-47. PWM Output Timing Peripheral Information and Electrical Specifications TMS320DM355 5-48) DM355 UNIT .05P...
  • Page 146: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 VD(CCDC) INVALID PWM0 PWM1 INVALID INVALID PWM2 INVALID PWM3 Peripheral Information and Electrical Specifications Figure 5-48. PWM Output Delay Timing www.ti.com VALID VALID VALID VALID Submit Documentation Feedback...
  • Page 147: Submit Documentation Feedback

    Figure 5-49 Figure 5-50) PARAMETER Figure 5-49. RTO Output Timing INVALID Figure 5-50. RTO Output Delay Timing Peripheral Information and Electrical Specifications TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 VALID VALID VALID VALID...
  • Page 148: Submit Documentation Feedback

    JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
  • Page 149: Submit Documentation Feedback

    Hold time, TMS valid after RTCK high h(RTCKH-TMSIV) RTCK Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-51. JTAG Input Timing Peripheral Information and Electrical Specifications TMS320DM355 Figure 5-51) DM355 UNIT...
  • Page 150: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port Cycle time, RTCK c(RTCK) tw(RTCKH) Pulse duration, RTCK high tw(RTCKL) Pulse duration, RTCK low Rise time, all JTAG outputs...
  • Page 151: Submit Documentation Feedback

    Changed V to V SSA_USB SS_USB Removed V (Supply ground, Analog) Updated descriptions of V and V SS_MX1 Submit Documentation Feedback SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ADDS/CHANGES/DELETES SSA_DLL DDA33_DDRDLL SS_MX2 TMS320DM355 Digital Media System-on-Chip (DMSoC) Revision History...
  • Page 152: Submit Documentation Feedback

    TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Updated Section 5.9.1, Video Processing Front-End (VPFE) Updated Section 5.9.1.1, CCD Controller (CCDC) Updated Section 5.9.1.2, IPIPE - Image Pipe Removed "CFALD – CFA Multiply Mask / Lens Distortion Module" section Removed "Auto Exposure (AE) and Auto White Balance (AWB) Engine"...
  • Page 153: Submit Documentation Feedback

    This data is subject to change without notice and without revision of this document. Note that micro-vias are not required for this package. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 μC/W...
  • Page 155: Important Notice

    TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...

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