Pulse-Width Modulation - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Table 29. Prescaler/Timer Reload Values Versus Contexts

Pulse-Width Modulation

Overflow (when autoreload on)

The timer can be configured to provide a programmable pulse-width

modulation (timer PWM) output. The timer PWM output pin can be configured

to toggle on an event. TCLR (TRG bits) determine on which register value the

timer PWM pin toggles. Either overflow or match can be used to toggle the

timer PWM pin when a compare condition occurs. The TCLR (SCPWM bit) can

only be programmed to set or clear the timer PWM output signal while the

counter is stopped or the trigger is off. This allows the output pin to be set to

a known state before modulation starts. The modulation is synchronously

stopped when TRG bit is cleared and overflow occurred. This allows the output

pin to be set to a known state when modulation is stopped.

In Figure 6, the internal overflow pulse is set each time the (0xFFFF FFFFF

– TLDR +1) value is reached, and the internal match pulse is set when the

counter reaches TMAR register value. According to TCLR (TRG and PT bits)

value, the timer provides pulse or PWM on the output pin (timer PWM).

In Figure 6 TCLR (SCPWM bit) is set to 0.

The TLDR and TMAR registers must keep values smaller than the overflow

value (0xFFFFFFFF) with at least two units. In case the PWM trigger events

are both overflow and match, the difference between the values kept in TMAR

is used, the compare mode TCLR (CE) must be set.

Dual-Mode Timer

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