Introduction; Sdram Interface - Texas Instruments OMAP5912 Reference Manual

1

Introduction

1.1

SDRAM Interface

SPRU756A
This document describes the memory interfaces of the OMAP5912
multimedia processor.
This document describes the following interfaces:
-
SDRAM (external memory interface fast, or EMIFF)
-
Asynchronous and synchronous burst memory (external memory
interface slow, or EMIFS)
-
NAND flash (hardware controller or software controller)
-
CompactFlash on EMIFS interface
-
Internal static RAM
The following serves to give a brief overview of the EMIFF. Please see
Chapter 2 for a detailed description of the EMIFF. The OMAP EMIFF is an
SDRAM controller that manages access by the various initiators of an
OMAP-based system. It can support one 16-bit device or two 8-bit devices.
The external interface data bus width is always 16 bits.
The EMIFF supports the following devices:
-
Standard single-data-rate SDRAM
-
Low-power single-data-rate SDRAM
-
Standard double-data-rate SDRAM
-
Mobile double-data-rate SDRAM
In terms of capacity and organization of memory components, the EMIFF can
handle:
-
1G-bit, 512M-bit, 256M-bit, 128M-bit, 64M-bit, and 16M-bit devices
-
Two-bank 16M-bit devices, two-bank or four-bank devices for 64M-bit
devices, four-bank devices only for any other capacity
-
x8 (two devices) or x16 (single device) data bus configuration, except for
the 1G-bit device: the EMIFF supports only a x16-1G-bit device (single
device). The maximum external SDRAM configuration is 128 megabytes.
Memory Interfaces
Memory Interfaces 15