Flush Cache Line; Flush The N-Way I-Cache; Flush A Ramset - Texas Instruments OMAP5912 Reference Manual

DSP Memory
3.5.4

Flush Cache Line

3.5.5

Flush the n-Way I-Cache

Flush a ½ Ramset
3.5.6
36 DSP Subsystem
2) Write CACLR = 1 in DSP CPU ST3 register.
Once the I-cache has been flushed, the CACLR bit is automatically reset to 0.
This operation flushes a single line in the cache (for example, when an
instruction is directly modified in the external memory by the software):
1) Write the address, which identifies the flush line (see the flush line address
register: FLAR).
2) Set the flush line bit in GCR.
Once the line is flushed, the flush line bit in GCR is reset by the I-cache.
When the flush line is activated, the I-cache searches the flush line in its data
array. Three cases are possible:
-
This line is found in its two-way (or direct-mapped) data array, and then
the corresponding line valid bit is invalidated. Consequently, for the next
access at the same address, a miss and a new line is loaded from the
external memory.
-
This line is found in one of the ramset data arrays, and then the
corresponding line valid bit is invalidated. Consequently, for the next
access at the same address, a hit/miss and a new line is loaded from the
external memory.
-
This line is not found. In this case, no action is performed and the flush line
is terminated.
To flush the n-way I-cache:
1) Reset the global flush bit (see the global control register). See Table 17.
2) Set the n-way-flush bit.
3) Write CACLR = 1 in DSP CPU ST3 register.
All of the line valid bits of the n-way I-cache are then invalidated.
To flush a ½ ramset, do the following:
1) Reset the global flush bit (see the global control register). See Table 17.
2) Set the ½ ramset flush bit of the corresponding RCR register.
3) Write CACLR = 1 in DSP CPU ST3 register.
SPRU750A