Checking The Synchronization Status; Dropped Synchronization Events; Monitoring Channel Activity - Texas Instruments OMAP5912 Reference Manual

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Checking the Synchronization Status

Each channel has a synchronization flag (synchronization) in its status

controller sets the flag (SYNCHRONIZATION = 1). The flag is cleared

(SYNCHRONIZATION = 0) when the DMA controller has completed the first

read access (transfer from source port to channel buffer) after receiving

synchronization.

If synchronization events occur before the DMA controller is done servicing a

currently active one (before the DMA controller clears the synchronization bit

in DMA_CSR), the second new synchronization event is dropped. The DMA

controller responds to an event drop as follows:

After the current element transfer, the DMA controller disables the channel

(EN = 0 in DMA_CCR); activity in the channel stops after the current

element transfer.

If the corresponding interrupt enable bit is set (DROP_IE = 1 in

DMA_CICR), the DMA controller also sets the event drop status bit

(DROP = 1 in DMA_CSR ) and sends an interrupt request to the CPU.

The DMA controller can send an interrupt to the CPU in response to the

operational events listed in Table 106. Each channel has interrupt enable (IE)

bits in the interrupt control register (DMA_CICR) and some corresponding

status bits in the status register (DMA_CSR). If one of the operational events

in the table occurs, the DMA controller checks the corresponding IE bit and

acts accordingly:

If the IE bit is 1 (the interrupt is enabled), the DMA controller sets the

corresponding status bit and sends the associated interrupt request to the

CPU. DMA_CSR is automatically cleared if the program reads the

If the IE bit is 0, no interrupt is sent and the status bit is not affected.

DMA_CSR also has a synchronization bit that is used when a synchronization

event is chosen for the channel. This bit indicates when the selected

synchronization event has occurred (SYNCHRONIZATION = 1) and when it

has been serviced (SYNCHRONIZATION = 0). For details, see Section 4.13,

Synchronizing Channel Activity.

Direct Memory Access (DMA) Support

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