Mpu Interrupt Mapping - Texas Instruments OMAP5912 Reference Manual

Interrupt Overview
Table 3. DSP Level 2.1 Interrupt Mapping (Continued)
1.1.3

MPU Interrupt Mapping

Table 4. MPU Level 1 Interrupt Mapping
Level 1 Interrupt Line
IRQ_0
IRQ_1
IRQ_2
IRQ_3
†
These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-
dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
‡
These IRQs are available only when the DMA is in OMAP3.1 compatibility mode. See the Multimedia Processor Direct
Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
14 Interrupts
Level 2.1 Interrupt
Line
IRQ_7
IRQ_8
IRQ_9
IRQ_10
IRQ_11
IRQ_12
IRQ_13
IRQ_14
IRQ_15
IRQ_16−
IRQ_47
IRQ_48 ... IRQ_63
For each interrupt, the user must configure the SENS_nEDGE bit in the
corresponding interrupt level register (ILR) according to whether the interrupt
is edge- or level-sensitive. See Table 13 for more details.
The interrupt priority is not hard-coded on the MPU side. Thus, the software
must define all interrupt priorities for both level interrupt handlers. (See
Table 4.)
OMAP 5912 Mapping
Level 2 interrupt handler IRQ
Camera IF
Level 2 interrupt handler FIQ
External FIQ
Mapping
GPTIMER7
GPTIMER8
Reserved
McBSP2 TX
McBSP2 RX
MCSI1_RST_INT
MCSI2_RST_INT
MMC/SDIO2
SPI
Reserved
Free
Default Sensitivity
Configuration
Level
Level
−−−−−
Level
Level
Level
Level
Level
Level
−−−−−
−−−−−
Sensitivity
Level
Level
Level
User-defined
SPRU757B