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DSP Memory Management Unit
Figure 11.
DSP MMU Architecture
0
Search/RW
access
MPU TIPB
data
D/P Logical address tag
Logical address
(LA)+ page
descriptor
from table
walking logic
(TWL)
31
LA
ST_DATA_IN
MPU
Translation Table
TIPB
Base (TTB)
Table walking
MPU
logic
disable
7.2
Address Translation
60
DSP Subsystem
Preserved entry status
Content addressable
memory (CAM)
P
14
Translation lookaside
buffer (TLB) hit / miss
FAULT_STATUS
23
FAULT_ADDRESS
The address translation from logical address to physical address is made
using the translation lookaside buffer (TLB) contained in the MMU.
0
0 0 Not valid
1
0 0 Section (1MB)
1
0 1 Large page (64KB)
1
1 0 Small page (4KB)
1
1 1 Tiny page (1KB)
MPU
TI Peripheral
Bus (TIPB)
add
TWL
entry
select
E
n
c
V
SLST
o
d
e
r
4
AP
check
Fault signal
0
AP (Access Permission)
Page descriptor from:
MPU
Physical address
(PA)
TIPB
from
data
TWL
Random access
memory (RAM)
MSB physical address
22
LA
LSB
Physical page address
SPRU750A
AP
2
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