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Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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OMAP5912 Multimedia Processor

Device Overview and Architecture

Reference Guide

Literature Number: SPRU748A

March 2004

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Summary of Contents for Texas Instruments OMAP5912

Page 1 OMAP5912 Multimedia Processor Device Overview and Architecture Reference Guide Literature Number: SPRU748A March 2004...
Page 2 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 3 Preface Read This First About This Manual This document introduces the setup, components, and features of the OMAP5912 multimedia processor and provides a high-level view of the device architecture. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
Page 4 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 5 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU748A...
Page 6 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 7 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 8 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 9 ......... OMAP5912 Clock and Reset Architecture .
Page 10 ........OMAP5912 Wake-up Capabilities .
Page 11: Table Of Contents
............OMAP5912 Top-Level Detailed Diagram .
Page 12 ........OMAP5912 Dedicated Modules .
Page 13 Introduction This document introduces the setup, components, and features of the OMAP5912 multimedia processor and provides a high-level view of the device architecture. Overview OMAP5912 is the next generation of OMAP processors and succeeds the Texas Instruments OMAP5910 processor. It is built with TI 130-nm process technology and has dual input/output voltage (1.8 V−3.3 V) capability.
Page 14: Top-Level Omap5912
(SDMA), and part of the L3 and L4 interconnects. All other components of OMAP5912 are associated with the OMAP gigacell revision 3.2. The OMAP5912 device provides a secure environment to run secure applications. The security hardware components include: OMAP3.2 gigacell security state machine...
Page 15 The memory interfaces define the system memory access organization of OMAP5912. The peripheral subsystem defines all of the components used to interface OMAP5912 with specific external devices, such as compact camera port (CCP), keyboard, and smart display. The security modules include ROM, a single port SRAM, eFuse cells, and secure peripherals, which enable the system to support secure applications.
Page 16 OMAP5912 supports CompactFlash with a dedicated compact flash controller. Other Memory Types OMAP5912 includes multiple serial interfaces that can be used to connect multiple types of memories, including: Up to two multimedia cards through the multimedia memory card interfaces (MMC/SDIO)
Page 17 Overview Serial Interfaces OMAP5912 provides several serial interfaces: A master/slave serial port interface (SPI), enabling serial data transfer compatible with common SPI protocol Three multichannel buffered serial port (McBSP) peripherals, enabling emulation of the following serial protocols: Serial port interface...
Page 18 General-purpose input/output (GPIO) modules allow the monitoring and control of OMAP5912 device input/output pins with event detection for external interrupts support. The pulse width tone (PWT) module provides OMAP5912 output pins with waveform control for tone generation. The pulse width light (PWL) module allows OMAP5912 output pins waveform control for brightness light control.
Page 19 The power interface is the clock request pins. 1.11.3 Modem Connection Two examples propose ways to connect a modem to the OMAP5912 device: Using a CMT-APE interface: the SSI exchanges data between the modem and OMAP5912. The control uses GPIO pins.
Page 20: Omap5912 Top-Level Detailed Diagram
OMAP5912 Description Figure 2. OMAP5912 Top-Level Detailed Diagram DSP DMA handler Test (ETLM, BOM, SCM, DSP Inth L2.1 ULPD APLL Die ID, JTAG, production ID, eFUSE ctl) System DMA handler MCSI1 MPU private bus MPU Inth L2 CompactFlash ctrl MCSI2...
Page 21: Mpu Private Peripherals
OMAP5912 Description Table 1 through Table 8 describe the OMAP5912 top-level partitioning. For more detail on the OMAP5912 core, see Chapter 2, OMAP3.2 Subsystem. Table 1. MPU Private Peripherals Peripheral Name General Description MPU level 2 interrupt handler There is one MPU interrupt handler outside the OMAP 3.2 gigacell. It supports up to 128 interrupt lines.
Page 22: Mpu Shared Peripherals
OMAP5912 Description Table 3. MPU Shared Peripherals Peripheral Name General Description USB On-The-Go A combination of the USB client and USB host used in OMAP5910, including an additional module (OTG module) An embedded real-time clock module µWire A serial interface that connects external devices such as EEPROM or LCD with µWire standard...
Page 23: Mpu/Dsp Statically Shared Peripherals
This is a simple upward counter clock used by the 32-kHz input clock to counter enable synchronization between modem and application chips when OMAP5912 is used in conjunction with a modem having the same clock input. As soon as the power-up reset input is released, the counter starts counting.
Page 24: Omap5912 Dedicated Modules
Transmit part of the SSI The OMAP5912 SST can process up to 8 channels. A generic distributed DMA attached to the SSI modules in OMAP5912. It performs DMA transfer between the SSI and the various subsystems (internal memory or external memory).
Page 25: Omap5912 Test Modules
Each die ID is unique, as it is created from the wafer, lot, and factory numbers, plus the die x/y coordinates in the wafer. Production ID An additional 64-bit register of eFuse cells used to include specific OMAP5912 needs. One R&D eFuse to distinguish the OMAP5912 production version from the prototype version.
Page 26 OMAP5912 Description TMS320C55xt (C55xt) DSP including: Embedded ICE emulator interface through JTAG port C55xt DSP rev 2.11 L1 cache (24K bytes) 16K-byte, two-way set-associative instruction cache 2x 4K-byte RAM set for instruction DARAM 64K-byte, zero wait state, 32-bit organization SARAM 96K-byte, zero wait state, 32-bit organization...
Page 27 Endianism conversion for DSP The DSP uses big-endian format, whereas the MPU uses little-endian format. Also, as a rule, the OMAP5912 chip works in little endian. Thus, the endianism conversion is useful for all memory or peripheral accesses from on-chip peripherals or all shared memories to the C55x DSP.
Page 28: Omap3.2 Gigacell
OMAP5912 Description Figure 3. OMAP3.2 Gigacell DSP timer 1 DSPINT Mailbox (32) Endianism DSP timer 2 STIO DSP WD (32) conversion timer DSP timer 3 (32) INTH TIPB (private) TIPB ports DSP TIPB TIPB (shared) MPUI port CLKIN DPLL 1...
Page 29 The ULPD can handle the high-frequency oscillator on/off sequences, when used, and provides the resets to OMAP. It also allows configuration of the clock sources of the OMAP5912 device and management of the APLL interface. OMAP5912 Clock and Reset Architecture The global clock distribution and the reset distribution scheme are described in Chapter 5.
Page 30: Ldconv Integration
OMAP5912 Description 2.2.2 Peripherals Subsystem LDCONV This module provides 16-bit to 18-bit LCD data conversion to the OMAP3.2 LCD interface. It supports two operating modes: The 16-bit LCD The 18-bit LCD Figure 4. LDCONV Integration LCD pixel 16-bit LCD external interface OMAP3.2...
Page 31: Compactflash Interface
OMAP5912 Description CompactFlash Controller The CompactFlash controller interfaces a CompactFlash module and a classical memory interface. Control signals from the memory interface are processed through the CompactFlash controller to drive the CompactFlash module, and control signals from CompactFlash are processed to perform a data transfer to the memory interface.
Page 32 OMAP5912 Description DES_3DES Accelerator DES_3DES module provides hardware-accelerated data encryption/decryption functions. It can run either the single DES algorithm or the triple DES algorithm in compliance with the FIPS 46−3 standard. It supports the electronic codebook (ECB) and cipher block chaining (CBC) modes of operation.
Page 33: Hdq/1-Wire Overview
OMAP5912 Description Pulse Width Time (PWT) This module generates a modulated frequency signal for the external buzzer. Frequency is programmable between 349 Hz and 5276 Hz with 12 half-tone frequencies per octave. The volume is also programmable. Pulse Width Length (PWL) This module allows the control of the backlight of the LCD and the keypad by employing a 4096-bit random sequence.
Page 34: Mcsi1 Interface
MCSI1 The MCSI1 is a multichannel serial interface, half-duplex, master/slave. MCSI1 can be used in OMAP5912 to interface the Bluetooth voice module. In this case, the interface is an 8-kHz frame serial port, 8-bit data transfer. It is a 4-wire interface with a bidirectional serial clock and frame synchronization.
Page 35: Mcsi2 Interface
MCSI2 The MCSI2 is a multichannel serial interface, half-duplex, master/slave. MCSI2 can be used in OMAP5912 to interface the modem voice module. In this case, it is an 8-kHz frame serial port, 8-bit data transfer. Clock and frame synchronization are bidirectional.
Page 36 OMAP5912 Description µWire The µWire module is a serial interface to drive external devices like EEPROM or LCD with µWire standard. µWire Interface Figure 9. OMAP5912 µWire UWIRE.SDI MPU TIPB (public) UWIRE.SDO DMA request SCLK UWIRE_SCLK CSO, 1, 2, 3 UWIRE.CS1, 2, 3...
Page 37: 6X5 Keyboard Connection
OMAP5912 Description Keyboard The keyboard interface is a 6 x 5 or 8 x 8 interface. Figure 10 shows the 6 x 5 interface. The keyboard is connected to the chip using: KBR (7:0) input pins for row lines KBC (7:0) output pins for column lines Figure 10.
Page 38: Uart Clock Scheme
The clock source for UART2 can be: The system clock or the sleep clock The APLL output Selection of the clock source is done statically from the OMAP5912 configuration register, which is accessible by software through a normal MPU peripheral access.
Page 39: Available I/Os Per Uart
OMAP5912 Description Available I/Os per UART Table 9. Available I/Os per UART Signal UART1 UART2 UART3 By mux By mux By mux By mux By mux By mux SD_IRDA By mux BD_CLK For more detail on I/Os, see Appendix B, Inputs/Outputs.
Page 40: Mcbsp Interface With I2S-Compliant External Codec
McBSP1 McBSP1 is an instance of the McBSP module. The McBSP1 can be used in OMAP5912 to interface with an audio codec compliant with the I2S protocol (5-pin interface). The codec can provide the reference clock. The serial clock and the frame synchronization can be either inputs or outputs. When outputs, they are derived from the reference clock.
Page 41: Mcbsp Interface With Communication Processor
SPI mode or to emulate an I2S serial link. The McBSP2 interface differs slightly from the McBSP1 interface in that there is no capability to connect an OMAP5912 external reference clock to it. Figure 13. McBSP Interface With Communication Processor...
Page 42: Mcbsp3 Interface Connected To Optical Device
OMAP5912 Description Figure 14. McBSP3 Interface Connected to Optical Device OMAP5912 Optical audio McBSP3 interface device DSP peripheral (LC89051V) programmable CLKS clock MCBSP3.FSX FSX_OUT (multiplexed) FSX_OE FSX_IN MCBSP3.CLKX Optical clock CLKX_OUT Configuration CLKX_OE register CLKX_IN MCBSP3.DX DX_OUT Optical data out...
Page 43 OMAP5912 Description Serial Port Interface (SPI) The serial port interface is a bidirectional, four-line interface dedicated to the transfer of data to and from external devices offering a four-line serial interface. Inter-Integrated Circuit (I The multimaster I C peripheral provides an interface between a local host (LH)
Page 44: Usb Otg Integration At System Level
Note: OTG functionality requires a special transceiver external to OMAP5912. The communication between the transceiver and the controller is done through an I 2 C communication channel. In this case, the USB OTG module port 2 is connected to an external USB OTG transceiver, port 1 is connected to a USB transceiver, and port 0 is connected to the integrated USB transceiver.
Page 45 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunction with the SSI to provide a CMT-APE interface to the OMAP5912.
Page 46 Watchdog In addition to the two OMAP3.2 watchdogs, there are two instances of the watchdog module in OMAP5912. One is clocked at 32 kHz and the other by a 192-MHz clock (secure watchdog). The secure watchdog is used in conjunction with OMAP5912 security features.
Page 47: Ccp Internal Block Diagram
OMAP5912 Description Compact Camera Port (CCP) The CCP is a serial interface from a camera. The CCP block combines the camera and the host through the VIA bus. The input data signal from the camera is expanded to 32 bits, which is the width of the VIA bus. The inputs are the serial input data (CCPDa) and a clock signal (CCPClk).
Page 48: Cmt-Ape Interchip Communication
OMAP5912 Description Synchronous Serial Interconnect The synchronous serial interconnect (SSI) peripheral enables OMAP5912 to exchange information with an external modem. It enables a full duplex interface, using a synchronous serial interconnect protocol (SSI). This protocol consists of a transmitter and a receiver.
Page 49: Sossi Internal Block Diagram
1*32 Bit 1*32 Bit MMC/SDIO There are two instances of the MMC/SDIO module in OMAP5912. This module is a superset of the MMC/SD module from OMAP5910, including I/O interfacing capability to support an SDIO card. The MMC/SDIO1 replaces the MMC/SD from OMAP5910, whereas the MMC/SDIO2 is an additional peripheral.
Page 50: Mmc/Sdio Block Connection
SDIO card specification v1.0 OMAP5912 also supports control signals to external level shifters in case the voltage for OMAP5912 I/O is set to 1.8 V. These signals are derived from the direction control of the MMC_DAT0 and MMC_CMD I/O pads (one direction control per data bit line and one direction control for the command line).
Page 51 Whereas the MMC/SDIO1 interface includes all of the MMC/SDIO pins except the direction controls (data and control), the full MMC/SDIO2 is routed at the OMAP5912 level. The OMAP5912 configuration selects only the part of the interface that is required. VLYNQ...
Page 52 System software controls the C55x DSP boot option by programming registers via the MPUI interface when the DSP is being held in reset. Boot ROM The OMAP5912 configuration is 16384 x 32 bits. For more detail, see Chapter 5, Initialization. Security Layer The OMAP 3.2 gigacell includes special-purpose security hardware that is...
Page 53: Event Captures For Peripheral Wake-Up Capability
1) When the wake-up is done through the GPIO, the programmer must ensure that the GPIO direction is set up as input. 2) Depending on the OMAP5912 configuration before entering into power-down mode, the GPIO can wake either the entire system or only a specific subsystem.
Page 54 1) When the wake-up is done through the GPIO, the programmer must ensure that the GPIO direction is set up as input. 2) Depending on the OMAP5912 configuration before entering into power-down mode, the GPIO can wake either the entire system or only a specific subsystem.
Page 55 19 Communication system tasks 13 Bluetooth interface 19 modem connection 19 Compact camera port 47 Interfaces multiplexing 18 CompactFlash controller 31 JTAG TAP controller 51 DES_3DES accelerator 32 DSP private peripherals 21 DSP shared peripherals 22 Keyboard 37 SPRU748A OMAP5912...
Page 56 MPU/DSP statically shared peripherals 23 Peripherals DSP private 21 MPU private 21 MPU shared 22 MPU/DSP dynamically shared 23 OMAP5912 dedicated modules 24 MPU/DSP statically shared 23 OMAP5912 processor Peripherals subsystem camera and display interfaces 17 32 bit dual−mode timer 45 communication system tasks 13 32−kHz synchronization counter 46...
Page 57 I/Os 39 clocking scheme 38 Pulse width time 33 UARTs 38 ULPD 29 USB OTG 44 uWire 36 Random number generator 32 Real time counter 32 Wake up capabilities 53 pin description 54 Security layer 52 Watchdog 46 SPRU748A OMAP5912...
Page 58 OMAP5912 SPRU748A...
Page 59 OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide Literature Number: SPRU749A March 2004...
Page 60 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 61 OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
Page 62 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 63 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU749A...
Page 64 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 65 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 66 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 67 ..........3.2.14 Bus Turn-Around and CS Negation Time Control ......SPRU749A OMAP5912...
Page 68 ......... . OMAP5912...
Page 69 ..............SPRU749A OMAP5912...
Page 70 Asynchronous 16-Bit Write Operation on a Multiplexed Address/16-Bit Data Bus (WRWST = 1, WELEN = 3, FCLKDIV = 00 and ADVHOLD = 0) ..... . OMAP5912 SPRU749A...
Page 71 ............. . . SPRU749A OMAP5912...
Page 72 ......... OMAP5912...
Page 73 ......... SPRU749A OMAP5912...
Page 74 ............. . . DSP Clock Control Prescaler Selection Register (DSP_CKCTL) ....OMAP5912 SPRU749A...
Page 75 ......... . SPRU749A OMAP5912...
Page 76 ........OMAP5912 SPRU749A...
Page 77: Introduction
OMAP3.2 Subsystem This document introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. Introduction Figure 1 shows the OMAP5912 OMAP3.2 gigacell. SPRU749A OMAP3.2 Subsystem...
Page 78 Introduction Figure 1. OMAP3.2 Gigacell DSP timer 1 DSPINT Mailbox (32) Endianism STIO DSP timer 2 conversion DSP WD (32) timer DSP timer 3 (32) INTH TIPB (private) TIPB ports DSP TIPB TIPB (shared) MPUI port CLKIN DPLL 1 Endianism conversion DSP bus MPUI...
Page 79: Omap3.2 Features
TMS320C55x (C55x) DSP rev 2.1, running at a maximum of 192 MHz L1 cache (24K bytes) 16K-byte, two-way, set-associative instruction cache (on the OMAP5912 prototype, one wait state is introduced in case of discontinuity) 2 X 4K-byte RAM set for instruction...
Page 80 It supports connection to a128M-byte maximum of SDRAM. The address width is 16 bits, and two bank selection bits are also provided. The OMAP5912 chip requires interfacing with a maximum of four banks of 64M x 16-bit SDRAM memory with DDR capability.
Page 81 64M bytes of address space through a 25-bit address bus. Note: At the OMAP5912 level, two chip-selects can be split in half by configuration to provide four chip-selects. This enables OMAP5912 to provide up to six chip-selects supporting up to 32M bytes of address space on four chip-selects and up to 64M bytes on two chip-selects.
Page 82 OMAP3.2 Features Constant Post-increment Single indexing Double indexing Different indexing for source-respective destination Logical channel chaining Software enabling Hardware enabling Logical channel interleaving Logical channel preemption Two choices of logical channel arbitration of physical resources, round robin or fixed Two levels of logical channel priority Constant fill Transparent copy Rotation 0, 90, 180, and 270...
Page 83: Traffic Controller
Endianism conversion for DSP The DSP uses big-endian format, whereas the MPU uses little-endian format. Also, as a rule, the OMAP5912 chip works in little endian. Thus, the endianism conversion is useful for all memory or peripheral accesses from on-chip peripherals or all shared memories to the DSP megacell.
Page 84 Traffic Controller OCP-T2, EMIFF, and EMIFS. Selection of the destination target is based on address decoding within the TC. DSP. The DSP is connected to the TC via the DSP bus. The DSP can access memory devices or other types of targets connected to OCP-T1, OCP-T2, EMIFF, and EMIFS.
Page 85: Ocp-T1/Ocp-T2
Traffic Controller Figure 2. Traffic Controller Functional Block Diagram Slow bus I/F arbiter Slow 16,32 memory Slow bus DSP bus Fast bus I/F arbiter Fast memory Fast bus Multi- OCP-T1 I/F banks EMIFS DMA arbiter EMIFS DMA System EMIFF DMA EMIFF DMA control OCP-T1 DMA...
Page 86: Emifs Programming
Traffic Controller Once granted, the selected request is converted from an OMAP internal protocol into an OCP-compliant transaction. As seen at the OMAP boundary, the OCP-TX is an OCP master. OCP-T1 and OCP-T2 have their own addressing spaces within the OMAP memory map (256M bytes accessible by OCP-T1 and 1.2 gigabytes accessible by OCP-T2) plus an additional common address range called the multibank address space (256M bytes).
Page 87: General Description
Traffic Controller Each chip-select controls an address range of 64M bytes with dedicated configuration registers to fulfill the protocol and the timing constraints compliant with the external device associated with it. Each chip-select configuration register supports dynamic configuration. CS0 and CS3 address mapping can be swapped with the BM bit in the EMIFS configuration (EMIFS_CONFIG) register.
Page 88: Emifs Memory Timing Control
Traffic Controller Mode 0. Asynchronous read. Used for any asynchronous memory, including flash devices. Mode 1−2−3. Asynchronous page mode read with control of 4 (mode1), 8 (mode 2), 16 (mode 3) words (device width) per page. These modes are mainly used for page mode flash devices. Mode 4−5.
Page 89 Traffic Controller (synchronous flash or ASIC). The frequency must be set to comply with the attached device’s timing constraints in combination with the others EMIFS timing controls. In synchronous mode 4 −5, a retiming mode enables read data to be latched by a delayed REF_CLK.
Page 90: Emifs Cs0 And Cs3 Decoding Control
Traffic Controller pin (FLASH.RDY on ball V2) can also be used in combination with internal wait state (full-handshaking mode). In non-full-handshaking mode, the RDWST and PGWST (mode 1−2−3 only) bit field in CS configuration register are used to control internal read wait state generation. In non-full-handshaking, the WELEN bit field in CS configuration register is used to control internal write wait state generation.
Page 91: Emifs Miscellaneous Memory Signal Control
Traffic Controller the device type is emulation then BM resets to 1. Otherwise, BM resets to 0. Thus, the boot is executed from CS0 or from CS3 attached memories. During normal execution, BM can be changed dynamically but obvious software precautions are required to prevent system crash.
Page 92: Mode 0-Asynchronous Read Operation
Traffic Controller Mode 4 & mode 5 synchronous burst read 3.2.8 Mode 0—Asynchronous Read Operation Basic Programming Model The asynchronous read mode 0 is selected by setting RDMODE = 0 in the corresponding EMIFS chip-select configuration register. Figure 3 shows a typical timing diagram. Figure 3.
Page 93 Traffic Controller The CS pulse width depends on RDWST bit field of the CS configuration register. CS pulse width equals: (RDWST + 2) REF_CLK (N cycles in Figure 3) CS minimum pulse width is 2 REF_CLK. The ADV pulse width depends on ADVHOLD bit field of the CS configuration register.
Page 94 Traffic Controller Figure 4. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=4 FCLKDIV=1 OESETUP=0 OEHOLD=0 ADVHOLD=1. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:1) FLASH.D(15:0) FLASH.OE FLASH_DIR_O FLASH.BE(1:0) FLASH.RDY OMAP3.2 Subsystem SPRU749A...
Page 95: Advanced Oe Control
Traffic Controller Figure 5. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=0 FCLKDIV=0 OESETUP=0 OEHOLD=0 ADVHOLD=0. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A(25:1) Valid address FLASH.D(15:0) Valid data D0 OESETUP cycles FLASH.OE FLASH_DIR_O...
Page 96 Traffic Controller Figure 6. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=4 FCLKDIV=1 OESETUP=3 OEHOLD=0 ADVHOLD=0. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A(25:1) Valid address FLASH.D(15:0) Valid data D0 OESETUP cycles FLASH.OE FLASH_DIR_O...
Page 97 Traffic Controller Figure 7. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=4 FCLKDIV=1 OESETUP = 2 OEHOLD = 1 ADVHOLD = 0. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A(25:1) Valid address...
Page 98: Read Access Size Adaptation And Cs Pulse Width High Control
Traffic Controller Read Access Size Adaptation and CS Pulse Width High Control In read mode 0, the EMIFS splits the Word32 access into two Word16 accesses in case of 16-bit device width. 4xWord32 burst read are split into eight successive Word16 accesses. The split process follows the little endian protocol (Word32 LSB part at lower Word16 address).
Page 99: Full-Handshaking And Ready Pin Usage In Asynchronous Read Mode
Traffic Controller Figure 9. Asynchronous 32-Bit Read Operation on a 16-Bit Width Device. RDWST=4 FCLKDIV=0 OESETUP = 1 OEHOLD = 1 ADVHOLD = 0 BTWST=0 BTMODE=0. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK N cycles N cycles BTWST +1 FLASH.CSx M cycles...
Page 100: Asynchronous Read With Multiplexed Address And Data Memory
As an example, a minimum of RDWST = 2 is needed for a nonready device that drives FLASH.RDY low with 0 time delay from CS low and for a CS configuration FCLKDIV = 0. See the OMAP5912 Data Manual (SWPS012) for timing information regarding FLASH.RDY assertion timing constraint. Figure 10.
Page 101 Traffic Controller Figure 11. Asynchronous 16-Bit Read Operation With Multiplexed Address/Data Bus Memory. RDWST=2 FCLKDIV=0 OESETUP=2 OEHOLD=0 ADVHOLD=0. Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A/D(15:0)/ Valid address Valid data (D0) (D0) FLASH.A(25:16) OESETUP...
Page 102 Traffic Controller Figure 12. Asynchronous 32-Bit Read Operation on a 16-Bit Multiplexed Address and Data Memory. RDWST=2 FCLKDIV=0 OESETUP=2 OEHOLD = 0 ADVHOLD = 0 TC_CLK REF_CLK FLASH.CLK BTWST+1 TC cycles N cycles N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A/D(15:0)/ Valid add1 Data valid Valid add2...
Page 103: Asynchronous Write Operation
Traffic Controller Figure 13. Asynchronous 16-Bit Read Operation with Ready on 16-Bit Multiplexed Address and Data Memory. RDWST=2 FCLKDIV=0 OESETUP=2 OEHOLD = 0 ADVHOLD = 0 BTWST = 0, BTMODE = 0 TC_CLK REF_CLK FLASH.CLK FLASH.CSxx FLASH.ADV FLASH.A(25:16) Valid address FLASH.A/D(15:0) FLASH.OE FLASH_DIR_O...
Page 104 Traffic Controller Figure 14. Asynchronous 16-Bit Write Operation on a 16-Bit Width Device (WRWST=2, WELEN=4 FCLKDIV=00 and ADVHOLD=1) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:1) Valid address FLASH.D(15:0) Write data P cycles FLASH.WE FLASH_DIR_O FLASH.BE(1:0) FLASH.RDY The REF_CLK is divided from TC_CK by a programmable value contained in FCLKDIV bit field of the CS configuration register.
Page 105: Multiplexed Asynchronous Write Operation
Traffic Controller The CS address and data hold time setup from WE high is fixed to one REF_CLK (Q cycle in Figure 14). In asynchronous mode 0−1−2−3, REF_CLK is not provided outside the EMIFS and FLASH.CLK is kept low. In synchronous mode 4−5, REF_CLK is provided outside the EMIFS through the FLASH.CLK (see mode 4,5).
Page 106 Traffic Controller The CS and address setup time from WE low is controlled by programmable WRWST bit field of the CS configuration register (see Table 19). (WRWST + 1) REF_CLK (N cycles in Figure 15) WRWST minimum pulse width is 1 REF_CLK. The ADV pulse width depends on ADVHOLD bit field of the advanced CS configuration register (see Table 28).
Page 107 Traffic Controller Figure 16. Asynchronous 16-Bit Write Operation on a Multiplexed Address/16-Bit Data Bus (WRWST = 1, WELEN = 3, FCLKDIV = 00 and ADVHOLD = 0) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV 1 Flash clk FLASH.A/D(15:0) Write data FLASH.A(25:16) P cycles FLASH.WE FLASH_DIR_O FLASH.BE(1:0)
Page 108: Full-Handshaking And Ready Pin Usage In Asynchronous Write Mode
Traffic Controller Full-Handshaking and Ready Pin Usage in Asynchronous Write Mode In full-handshaking mode, FLASH.RDY is monitored by the EMIFS to control read access time. The access is completed when both internal wait state WELEN expires and FLASH.RDY (ball V2) is asserted by the external device.
Page 109: Write Access Size Adaptation And Cs Pulse Width High Control
Traffic Controller Figure 17. Asynchronous 16-Bit Write Operation on 16-Bit Multiplexed Address and Data Memory With Ready (WELEN = 2, WRWST = 0, FCLKDIV = 0) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A/D(15:0)/ Write data FLASH.A(25:16) FLASH.WE FLASH_DIR_O FLASH.BE(1:0) FLASH.RDY READY_SYNC2 Write Access Size Adaptation and CS Pulse Width High Control During write access, the EMIFS splits the Word32 access into two Word16 accesses in case of 16-bit device width.
Page 110: Mode 1−2−3− Asynchronous Page Mode Read Operation
Traffic Controller Figure 18. Asynchronous 32-Bit Write Operation on 16-Bit Multiplexed Address and Data Memory (WELEN = 2, WRWST =1, FCLKDIV =0, BTWST = 0, and BTMODE = 1) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:16) FLASH.A/D(15:0) P cycles P cycles FLASH.WE FLASH_DIR_O FLASH.BE(1:0)
Page 111 Traffic Controller page length and word size (device width), the EMIFS can control device page crossing during a burst request (4×word32) and inserts initial wait state delay on purpose. The delay between successive words in the page is controlled by the PGWST bit field in the CS configuration register (in page wait state).
Page 112 Traffic Controller Delay equals to (PGWST + 1) REF_CLK (P cycles in Figure 19). ADV (FLASH.ADV on ball L4) is kept low for the entire access. Address drive time follows CS activation (no setup time guaranty). Delay time (OESETUP) and advanced time (OEHOLD) are disabled (OESETUP and OEHOLD bit fields don’t care).
Page 113: Mode 4 And Mode 5 Synchronous Burst Read Operation Mode
Traffic Controller 3.2.11 Mode 4 and Mode 5 Synchronous Burst Read Operation Mode Synchronous Read in Non-Multiplexed Address and Data Memory The synchronous burst read mode 4 and 5 are selected by setting the RDMODE bit field in the corresponding EMIFS chip-select configuration register (see Table 19).
Page 114 Traffic Controller In case this one REF_CLK cycle advance is not enough to meet the setup time requirement, the ADV pulse width can be extended by ADVHOLD. The real access time start from CS & ADV & address setup time to device clock rising edge valid.
Page 115 Traffic Controller Figure 22. Mode 5 Synchronous Burst 8x16-Bit Read Operation on 16-Bit Width Device (RDWST=3, FCLKDIV =0, ADVHOLD=0, RDMODE=5). Data write-back on the bus after read completion. TC_CLK FLASH.CLK N cycles FLASH.CSx FLASH.ADV FLASH.A(25:1) Valid address Î Î Î FLASH.D(15:0) Î...
Page 116: Synchronous Read In Multiplexed Address And Data Memory
Traffic Controller Figure 23. Mode 5 Synchronous Burst 2x16-Bit Read Operation on 16-Bit Width Device (RDWST=3, FCLKDIV =0, ADVHOLD=0, RDMODE=5). Data write-back on the bus after read completion TC_CLK FLASH.CLK N cycles FLASH.CSx FLASH.ADV FLASH.A(25:1) Read address FLASH.D(15:0) Î Î Î Î Î FLASH.OE FLASH_DIR_O FLASH.BE(1:0)
Page 117 Traffic Controller Figure 24. Mode 5 Synchronous Burst 8x16-Bit Read Operation on Multiplexed Address/Data 16-Bit Width Device (RDWST=2, FCLKDIV =0, ADVHOLD=0, OESETUP = 3, RDMODE=5). Data write-back on the bus after read completion. TC_CLK FLASH.CLK N cycles FLASH.CSx M cycles FLASH.ADV FLASH.A(25:16) 1 fl cycle...
Page 118 Traffic Controller Modes 4−5 are by default in full-handshaking mode. FLASH.RDY is monitored by the EMIFS to control read access time. FLASH.RDY must be asserted synchronously to REF_CLK. The first access is completed when both internal RDWST wait state expired and when ready pin is asserted by the external device. The internal initial wait state depends on RDWST bit field of the CS configuration register.
Page 119: Write Access In Mode 4 And 5
Traffic Controller Figure 26. Mode 5 Synchronous Burst 8x16-Bit Read Operation on Multiplexed Address/Data 16-Bit Width Device (RDWST=3, FCLKDIV =0, ADVHOLD=0, OESETUP = 3, RDMODE=5). Data write-back on the bus after read completion. TC_CLK FLASH.CLK N cycles FLASH.CSx OESETUP FLASH.OE M cycles FLASH.ADV FLASH.A(25:16)
Page 120: Read Retimed Protocol
Traffic Controller Figure 27. Asynchronous 16-Bit Write Operation on a 16-Bit Width Device (RDMODE = 5, WRWST=2, WELEN=4 FCLKDIV=00 and ADVHOLD=1) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:1) Valid address FLASH.D(15:0) Write data P cycles FLASH.WE FLASH_DIR_O Î FLASH.BE(1:0) Î FLASH.RDY 3.2.12 Read Retimed Protocol Warning...
Page 121 Traffic Controller The retiming mode is enabled through the RT bit field in the CS configuration register. Retiming mode is only allowed in synchronous modes 4−5−7 and has no effect on write accesses. Figure 28. Mode 4 Synchronous Burst 4x16-Bit Read Operation on 16-Bit Width Device With Retiming on (RDWST=2, FCLKDIV =0, ADVHOLD=0, RDMODE=4).
Page 122 Traffic Controller Figure 29. Mode 4 Synchronous Burst 4x16-Bit Read Operation on 16-Bit Width Device With Retiming on (RDWST=1, FCLKDIV =1, ADVHOLD=0, RDMODE=4) TC_CLK REF_CLK RET REF_CLK N +1 cycles FLASH.CSx FLASH.ADV FLASH.A(25:1) Valid address FLASH.OE Î Î Î FLASH.D(15:0) Î...
Page 123: Mode 7-Synchronous Burst Read Operation Mode
Traffic Controller Figure 30. Mode 4 Synchronous Burst 4x16-Bit Read Operation on Multiplexed Address/Data 16-Bit Width Device With Retiming on (RDWST=3, FCLKDIV =0, ADVHOLD=0, OESETUP = 3, RMODE=4). Data write-back on the bus after read completion. TC_CLK REF_CLK RET REF_CLK N +1 cycles FLASH.CSx FLASH.ADV...
Page 124 Traffic Controller Figure 31. Mode 7 Synchronous Burst 4x16-Bit Read Operation on 16-Bit Width Device (RDMODE = 7, FCLKDIV =1). Data write-back on the bus after read completion. TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV Î Î Î Î Î Î Î Î Î Î Î FLASH.A(25:1) Î...
Page 125: Write Access In Mode 7
Traffic Controller during read access in mode 7. RDWST field is not active and FLASH.RDY is not monitored in this mode (non-full-handshaking mode only). CS, ADV, OE are driven low for the entire access. ADVHOLD, OESETUP, OEHOLD time control are disabled in this mode. Address and data multiplexed protocol is not supported in mode 7 (MAD bit field not considered).
Page 126 Traffic Controller Figure 33. Mode 7 Asynchronous 16-Bit Burst Write Operations on a 16-Bit Width Device (WRWST=0, WELEN=0 FCLKDIV=1 and ADVHOLD=0, BTMODE = 0) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:1) FLASH.D(15:0) FLASH.WE FLASH_DIR_O FLASH.BE(1:0) FLASH.RDY OMAP3.2 Subsystem SPRU749A...
Page 127 Traffic Controller Figure 34. Mode 7 Asynchronous 16-Bit Burst Write Operations on a 16-Bit Width Device (WRWST=0, WELEN=0 FCLKDIV=1 and ADVHOLD=0, BTMODE = 1 and BTWST = 0) TC_CLK REF_CLK FLASH.CLK FLASH.CSx FLASH.ADV FLASH.A(25:1) FLASH.D(15:0) FLASH.WE FLASH_DIR_O FLASH.BE(1:0) FLASH.RDY 3.2.14 Bus Turn-Around and CS Negation Time Control When slow devices are attached to the IC, it can be necessary to control the next data bus activation time after a read access to this slow device.
Page 128 Traffic Controller After a read completion, if no other access (RD, WR) is pending, the data bus is driven with the previous read value. The bus turn-around time (OE going high to direction going out) is a minimum of 1 TC_CK cycle and can be extended through BTWST.
Page 129 Traffic Controller Figure 35. Wait States During a Read to Read Operation (BTWST (CSX) = 2 and BTWST (CSY) = 1, BTMODE=0) TC_CLK FLASH_CLK_M (REF_CLK) BTWSTX+1 CSX read FLASH.CSX BTWSTV+1 CSY read1 CSY read2 FLASH.CSY FLASH.OE IDLE IDLE IDLE FL_DIR_O(DATAEN) READ0 READ1 READ2...
Page 130 Traffic Controller Figure 36. Wait States During a Read to Write Transition (BTWST(CSX)= 3 BTWST (CSY) = 2, BTMODE=0) TC_CLK FLASH_CLK_M (REF_CLK) BTWSTX+1 CSX read FLASH.CSX BTWSTV+1 CSY read1 CSY read2 FLASH.CSY FLASH.OE IDLE IDLE IDLE FL_DIR_O(DATAEN) READ0 READ1 READ2 Î...
Page 131 Traffic Controller Table 2. Idle Time Between Different Bus Access Transitions (BTMODE = 1) Access(n) Access(n+1) Chip-Select Idle Time Length(BTWST) RD(csx) RD(csx) Same Inserted RD(csx) WR(csx) Same Inserted WR(csx) RD(csx) Same Inserted WR(csx) WR(csx) Same Inserted RD(csx) RD(csy) x != y Different Inserted RD(csx)
Page 132 Traffic Controller The EXTPWR bit field in the ARM_EWUPCT register is used to specify the minimum time between FLASH.RP deasserted and TC going out of idle state (See section 4.3.4). 3.2.16 Dynamic Auto Idle and System Idle Synchronization EMIFS supports auto idle mode (clock gating) to dynamically reduce power consumption when no requests are pending and no accesses are on-going.
Page 133 Traffic Controller The abort flag bit is cleared when the abort type register is read. At reset, TIMEOUT_EN is set to 1 and time-out value is set to 255 REF_CLK cycles. 3.2.18 EMIFS Boot Mode There are a number of external mechanisms that affect the initial state of the EMIFS during reset.
Page 134 Traffic Controller Note that the internal boot ROM may change the values of the MAD bit depending on the execution path. When BW = 0, the following CS0 and CS3 configuration is selected. RDMODE=0 FCLKDIV=3 RDWST=15 WELEN =15 WRWST=15 RT=0 When BW = 1, the following CS0 and CS3 configuration is selected.
Page 135 Traffic Controller It can support one 16-bit device or two 8-bit devices. The external interface data bus width is always 16 bits. The following devices are supported: Standard single-data-rate SDRAM Low-power single-data-rate SDRAM Mobile double-data-rate SDRAM In terms of capacity and organization for the memory components that can be attached, the EMIFF can handle: 1G-bit, 512M-bit, 256M-bit, 128M-bit, 64M-bit, and 16M-bit devices 2-bank16M-bit devices, 2-bank or 4-bank 64M-bit devices, and 4-bank...
Page 136 Traffic Controller 3.3.2 Initialization Sequence Before it can be accessed for writing or reading after power on, or when exiting deep power-down mode, an SDRAM device must be initialized with various protocol parameters (burst size, CAS idle time, write burst, etc.). This is known in SDRAM literature as the initialization sequence.
Page 137 Traffic Controller This procedure is also suitable for the mobile DDR device, as this kind of device does not include delay-locked loop technology (DLL). 3.3.3 Memory Mode Registers The following restrictions apply to the MRS register programming: Burst length must be programmed to full page for SDR devices. For mobile DDR devices, burst length must be programmed to 8 and the CAS idle time must be set to 3.
Page 138 Traffic Controller Entering self-refresh (SLRF bit). The self-refresh mode is automatically exited when the EMIFF receives an access request from OMAP initiators. You can set the refresh counter value corresponding to system frequency. The following formula can be used for refresh counter value (the counter value is the number of TC_CK between refreshes).
Page 139 Traffic Controller 3.3.6 Command Table Table 4 lists the commands. Table 4. Command List Command ADDR Command inhibit (NOP) No operation (NOP) Active (select bank and Bank/Row row activate) Read (select bank and Bank/Col column and start read burst) Write (select bank and Bank/Col column and start write burst)
Page 140 Traffic Controller Table 4. Command List (Continued) Command ADDR L → H X Deep power down exit Deep power down The difference between power down and deep power down mode is that in case of power down mode whenever there is an access request to EMIFF, the memory is brought out of power down by pulling CKE high, but in case of deep power down mode even when there is an access request the memory is not brought out of deep power down mode (CKE is still low).
Page 141 2) T2: The EMIFF_DLL_WRD_CTRL .DLLP control bit selects whether the internal strobe is 72 or 90 degrees (20% or 25% delay) from the external strobe The write DLL controls one DCDL. This DCDL is used to shift the data lines from OMAP5912 to the DDR (see Figure 39). SPRU749A OMAP3.2 Subsystem...
Page 142 Traffic Controller Figure 39. EMIFF DDR Data Writes (with respect to DLL) Strobe (to memory) Data Notes: 1) T1: Fine tune delay control for shifting the data (a manual adjustment). 64 steps of adjustment with a step value of 26.3ps (6 bit signed value in EMIFF_DLL_WRD_CTRL.WO). Note that 26.3 ps is a value valid in a nominal pro- cess at room temp and is subject to variation across process and temperature.
Page 143 Traffic Controller Thus, there are four important register controls: ENADLL in the EMIFF_DLL_WRD_CTRL register (See Table 37) enables or disables DLL. DLLPHASE in the EMIFF_DLL_WRD_CTRL register (See Table 37) allows a fine tuning of the delayed transaction to either 72 or 90 degrees out of phase with the internal strobe.
Page 144 Traffic Controller When loading a value into the DLL, the DLL must be enabled (ENADLL set to 1) for the load to be effective, for at least two clock cycles.To setup the controlled delay block for unlock mode: Write into the DLL control register, with ENADLL set, LOADDLL set, delay field set to the expected value.
Page 145 Traffic Controller The DLL behavior can be monitored by the software using the EMIFF DLL status registers (URD status and WRD status registers). For each DLL, the current counter value is available (DLLCount field), as well as two status bits: overflow and underflow.
Page 146 Traffic Controller High-power/high-bandwidth mode (HPHB) In this mode of operation, the active page is always left open at the end of access. The EMIFF controller keeps track of the open pages. It then deter- mines if the current access is to an opened page (access proceeds without latency) or to a closed page (the currently active page within that internal bank is closed, the necessary page is activated, and the access proceeds after a necessary latency).
Page 147 Traffic Controller OCP-I Programming The OMAP 3.2 OCP external initiator port is an interface intended to connect an external master device to the OMAP 3.2 platform. The OMAP 3.2 core appears as a slave, and its entire memory map, including TIPB peripherals, is accessible.
Page 148 Traffic Controller Figure 41. OCP-I Block Diagram OCP master port MData Bus (To all Sub-targets) MData Bus (To all Sub-targets) front- MAddr-Address Bus (To all Sub-targets) SSideBand Target1 Lock Target1 SResp Address MSideBand decoding Select signals Target1 SData MAddr (32) checker Target1 Abort From...
Page 149 Traffic Controller If OS protection is needed, it is recommended that any device integrating the OMAP 3.2 core provide an MMU or a translation table controlled by the OMAP MPU. Then it is the responsibility of the system software to ensure that undefined or unauthorized locations are not accessed.
Page 150 Traffic Controller Table 7 lists the 32-bit OCP-T1 and OCP-T2 registers. Table 7 through Table 15 describe the register bits. Table 7. OCP-T1/OCP-T2 Registers Base Address = FFFE CC00 Name Description Offset OCPT1_PRIOR OCP-T1 LRU priority register 0x00 OCPT1_PTOR1 OCP-T1 dynamic priority time-out 1 0xA0 OCPT1_PTOR2 OCP-T1 dynamic priority time-out 2...
Page 151 Traffic Controller Table 8. OCP Priority Registers 1 and 2(OCPT1_PRIOR and OCPT2_PRIOR) (Continued) Base Address = 0xFFFE CC00, Offsets = 0x00 and 0xD0 Name Function Reset DSP_PRIORITY Number of consecutive accesses allowed for DSP Reserved ARM_PRIORITY Number of consecutive accesses allowed for MPU The OCP target priority registers (OCPTx_PRIOR) allow the target to give consecutive accesses to a host when the host is granted the OCP target.
Page 152 Traffic Controller Table 10. OCP-T1 and OCP-T2 Priority Time-Out Registers 2 (OCPT1_PTOR2 and OCPT2_PTOR2) (Continued) Bits Field Description Reset 15:8 RESERVED Reserved. To ensure software compatibility, reserved 0x00 bit should be written to 0 and read value should be considered undefined. Number of TC_CK cycles that LCD must wait in 0x00 low-priority queue before going to high-priority queue...
Page 153 Traffic Controller The abort time-out register (ATOR) is used to store the number of clock cycles the OCP target counts down before activating the abort signal because the peripheral did not return a SRESP signal. Table 13. OCP-T1 and OCP-T2 Abort Address Registers—Access Address (OCPT1_AADDR and OCPT2_AADDR) Base Address = 0xFFFE CC00, Offsets = 0xB0 and 0xE4 Bits...
Page 154 Traffic Controller Table 14. OCP-T1 and OCP-T2 Abort Type Registers—Access Address (OCPT1_ATYPER and OCPT2_ATYPER) (Continued) Base Address = 0xFFFE CC00, Offsets = 0xB4 and 0xE8 Bits Field Description Reset HOST_ID Host ID of request that caused memory fault 00: MPU 01: DSP 10: DMA 11: OCPI...
Page 155 Traffic Controller Table 16. EMIFS Registers (Continued) Base Address = FFFE CC00 Name Description Offset EMIFS_CCS0 EMIFS chip-select configuration CS0 0x10 EMIFS_CCS1 EMIFS chip-select configuration CS1 0x14 EMIFS_CCS2 EMIFS chip-select configuration CS2 0x18 EMIFS_CCS3 EMIFS chip-select configuration CS3 0x1C EMIFS_PTOR1 EMIFS dynamic priority time-out 1 0x28 EMIFS_PTOR2...
Page 156 Traffic Controller Table 17. EMIFS Priority Register (EMIFS_PRIOR) (Continued) Base Address = 0xFFFE CC00, Offset = 0x04 Bits Field Description Reset DSP consecutive access RESERVED Reserved MPU consecutive access The EMIFS priority register allows the EMIFS to give consecutive accesses to a master when EMIFS is configured for least recently used (LRU) priority arbitration.
Page 157 Traffic Controller Table 18. EMIFS Configuration Register (EMIFS_CONFIG) Base Address = 0xFFFE CC00, Offset = 0x0C Field Description Reset Boot mode. Enables CS0 and CS3 address decoding See note swapping (See section 3.2.18 for BM reset value.) 0: CS0 [0000:0000 − 03FF:FFFF] CS3 [0C00:0000 −...
Page 158 Traffic Controller Table 19. EMIFS Chip-Select Configuration Registers (EMIFS_CCS0, EMIFS_CCS1,...,EMIFS_CCS3) (Continued)(Continued) Base Address = 0xFFFE CC00, Offsets = 0x10, 0x14, 0x18, 0x1C Field Description Reset 18:16 RDMODE Read mode select (see table below and section 3.2.1). See See note section 3.2.18 for RDMODE reset value for CS0 and CS3. or 000 15:12 PGWST/WE...
Page 159 Traffic Controller Table 20. EMIFS Chip-Select Configuration Register RDMODE Field Definition RDMODE Memory Mode 0: Asynchronous read Mode 1: Page mode ROM read—4 words per page Mode 2: Page mode ROM read—8 words per page Mode 3: Page mode ROM read—16 words per page Mode 4: Synchronous burst read mode Mode 5: Synchronous burst read mode Reserved for future extension...
Page 160 Traffic Controller Table 24. EMIFS Dynamic Wait States Control Register (EMIFS_DWS) Base Address = 0xFFFE CC00, Offset = 0x40 Field Description Reset 31:8 Reserved Reserved 0x000000 Full handshake enable Enables Full-/non-full-handshaking mode for for CS3 0: Full-handshaking 1: Non-full-handshaking Full handshake enable Enables Full-/non-full-handshaking mode for for CS2 0: Full-handshaking...
Page 161 Traffic Controller Table 25. EMIFS Abort Address Register (EMIFS_AADDR) Base Address = 0xFFFE CC00, Offset = 0x44 Field Description Reset 31:0 Abort address 0x00000000 This register holds the address involved in the aborted transaction. Table 26. EMIFS Abort Type Register (EMIFS_ATYPER) Base Address = 0xFFFE CC00, Offset = 0x48 Field Description...
Page 162 Traffic Controller Table 27. EMIFS Abort Time-Out Register (EMIFS_ATOR) Base Address = 0xFFFE CC00, Offset = 0x4C Field Description Reset 31:9 Reserved Reserved. To ensure software compatibility, reserved 0x0000000 bit should be write to 0 and read value should be considered undefined.
Page 163 Traffic Controller Table 29. EMIFF Registers Base Address = 0xFFFE CC00 Name Description Offset EMIFF_PRIOR EMIFF priority register 0x08 EMIFF_CONFIG EMIFF configuration register 0x20 EMIFF_MRS * EMIFF SDRAM MRS register (legacy) 0x24 EMIFF_CONFIG2 EMIFF configuration register 2 0x3C EMIFF_DLL_WRD_CTRL DLL WRD control register (write byte) 0x64 EMIFF_DLL_WRD_STAT DLL WRD status register...
Page 164 Traffic Controller Table 29. EMIFF Registers (Continued) Base Address = 0xFFFE CC00 Name Description Offset EMIFF_EMRS2 EMIFF SDRAM EMRS2 register 0xC8 EMIFF_DLL_LRD_CTRL DLL LRD control register 0xCC Note: EMIFF_MRS is a legacy register. Old software can use this register at offset 0x24. However, new software should use the EMIFF_MRS_NEW register at 0x70.
Page 165 Traffic Controller Table 31. EMIFF SDRAM Configuration Register (EMIFF_CONFIG) Base Address = 0xFFFE CC00, Offset = 0x20 Field Description Reset Power down enable. Puts the SDRAM device into power down mode. The CKE signal to the device is held high only for an active transaction.
Page 166 Traffic Controller Table 32. EMIFF SDRAM Register Memory/Data Bus Size Number EMIFF config SDRAM Type Memory SDRAM address multiplexing with respect to system 32−bit address register Size/Org./Bank space size devices [29:28][7:4] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 16M x 8 x 2b 000000 4 Mbytes...
Page 167 Traffic Controller Table 33. Frequency Range (SDRAM) ac Parameters SDF0 SDF1 SDF2 SDF3 (Cycles) (Cycles) (Cycles) (Cycles) tRAS tRCD tRRD Table 34. Frequency Range (Mobile DDR) ac Parameters SDF0 SDF1 SDF2 SDF3 (Cycles) (Cycles) (Cycles) (Cycles) tRAS tRCD tRRD Depending on the value programmed into the SDRAM_TYPE field of the EMIFF SDRAM operation register, either the ac parameters for SDRAM or the ac parameters for mobile DDR are supported;...
Page 168 Traffic Controller Table 35. EMIFF SDRAM MRS Register (legacy for OMAP3.1) Base Address = 0xFFFE CC00, Offset = 0x24 Field Description Reset 31:10 Reserved Must be all 0 0x000000 WBST Write burst must be 0 (burst write same as burst read). Reserved Must be 00.
Page 169 Traffic Controller Table 37. DLL WRD Control Register (EMIFF_DLL_WRD_CTRL) Base Address = 0xFFFE CC00, Offset = 0x64 Field Description Reset 31:26 Reserved Must be all 0. 0x00 25:20 Write offset. 6-bit delay fine adjustment, signed, 0x00 range – 32…+31. One step represents a 26.3 ps ± 10.5 ps delay adjustment.
Page 170 Traffic Controller Table 38. DLL WRD Status Register (EMIFF_DLL_WRD_STAT) Base Address = 0xFFFE CC00, Offset = 0x68 Field Description Reset 31:16 Reserved Must be all 0. 0x0000 15:8 DLL Count. Current DLL counter value for 0x00 monitoring/debug (assumes control bit ENADLL is 1 in DLL Control register.
Page 171 Traffic Controller Note that there is only one physical MRS register. Using that address, no automatic initialization sequence is generated; only a LOAD MODE register command is issued. A CPU write to this register generates a LOAD MODE register command, with BA1,BA0 = 0,0.
Page 172 Traffic Controller Table 41. EMIFF Low Power SDRAM Register (EMIFF_EMRS1) (Continued) Base Address = 0xFFFE CC00, Offset = 0x78 Field Description Reset TCSR Temperature-compensated self-refresh 00: 70°C maximum temperature 01: 45°C maximum temperature 10: 15°C maximum temperature 11: 85°C maximum temperature PASR Partial-array self-refresh 000: All banks...
Page 173 Traffic Controller Table 42. EMIFF SDRAM Operation Register (EMIFF_OP) (Continued) Base Address = 0xFFFE CC00, Offset = 0x80 Field Description Reset Operation mode 00: Low-power/low-bandwidth mode (LPLB mode). 01: High-power/high-bandwidth mode (HPHB mode). 10: Programmable operating mode 0 (POM0 mode). 11: Reserved.
Page 174 Traffic Controller Table 45. EMIFF Dynamic Arbitration Priority Time-Out Register 2 (EMIFF_PTOR2) Base Address = 0xFFFE CC00, Offset = 0x90 Field Description Reset 31:7 Reserved Must be all 0. 0x000000 23:16 Number of clock cycles before DSP requests are made high priority 0x00 in the dynamic priority scheme for the EMIFF SDRAM interface.
Page 175 Traffic Controller Table 47. EMIFF Abort Address Register (EMIFF_AADDR) Base Address = 0xFFFE CC00, Offset = 0x98 Field Description Reset 31:0 Abort Address Address of the transaction aborted 0x00000000 Table 48. EMIFF Abort Type Register (EMIFF_ATYPER) Base Address = 0xFFFE CC00, Offset = 0x9C Field Description Reset...
Page 176 Traffic Controller Table 50. DLL URD Control Register (EMIFF_DLL_URD_CTRL)(Continued) Base Address = 0xFFFE CC00, Offset = 0xC0 Field Description Reset 15:8 Delay 8-bit delay to adjust the digitally controlled delay, to 0x00 be used when the DLL is disabled. Range 0…225 One step represents a 26.3 ps ±...
Page 177 Traffic Controller Table 51. DLL URD Status Register (EMIFF_DLL_URD_STAT) (Continued) Base Address = 0xFFFE CC00, Offset = 0xC4 Field Description Reset Underflow status 0: DLL is OK. 1: DLL counter underflow Overflow status 0: DLL is OK. 1: DLL counter overflow This register controls the DLL for the lower read byte.
Page 178 Traffic Controller Table 54. OCP Registers Base Address = 0xFFFE C320 Name Register Description Offset OCPI_AFR OCP address fault 0x00 OCPI_MCFR OCP master command fault 0x04 OCPI_ATYPER OCP type of abort 0x0C OCPI_PR OCP protection 0x14 OCPI_SMR OCP-I secure mode. See note. 0x18 The reset value of the OCP protection register is all ones, such that all buses are protected on reset.
Page 179 Traffic Controller controller and is replaced by a simple read with a lock signal to the subtargets. The READEX command must be followed by a write that matches the address of the READEX as specified in Sonic’s OCP specification. A READEX command followed by a read results in unpredictable behavior.
Page 180 Traffic Controller Table 60. Secure Mode Register (OCPI_SMR) Base Address = 0xFFFE C320, Offset = 0x18 Name Function Reset 31:7 Reserved Reserved. Must be 0. In secure mode 0: Access is allowed. 1: Access to API is prohibited from initiator. RHEA_PRIV In secure mode 0: Access is allowed.
Page 181 Traffic Controller Priority Algorithms The traffic controller provides a choice of two priority algorithms for simultaneous requests. Arbitration is performed in each TC target port (OCP-T1, OCP-T2, EMIFF, and EMIFS). Selection of the arbitration scheme is common to all TC ports. Depending on the OMAP device, it can be either hardwired to one of the two algorithms or programmable (outside of OMAP).
Page 182 Clock Generation and Reset Management Clock Generation and Reset Management Overview The clock generation and system reset module is part of the MPU subsystem in the OMAP 3.2 platform. This module manages the clock generation modes for the microprocessor unit (MPU), the digital signal processor (DSP), and various other subsystems (memory interface, system DMA controller, MPU port interface (MPUI), etc.).
Page 183 Clock Generation and Reset Management Power control for external device reset/power on (flash memory) Wake-up functions initiated by interrupts (MPU and DSP) and DMA requests (traffic controller and TIPB) in the idle mode Initiation of the wake-up sequence by external devices during the idle mode OMAP3.2 Clock Generation The clock domains in the OMAP 3.2 hardware engine platform are...
Page 184 Clock Generation and Reset Management Figure 42. Clock Generator Module CLKM1 CK_GEN1 To MPU clock CLKREF DPLL1 clock generator domain CLKM2 CK_GEN2 To DSP clock clock generator domain CLKM3 To traffic Traffic controller CK_GEN3 controller clock generator cock domain 4.2.1 Clock Generation Modes The clock generation and system reset module of the OMAP 3.2 hardware engine supports four kinds of clocking modes:...
Page 185 Clock Generation and Reset Management Table 61. OMAP 3.2 Hardware Engine Clocking Modes (Continued) Clock Clocking Operating Mode MPU Clock DSP Clock TC Clock Remarks Select Source Source Source Reserved Bypass mode CK_REF CK_REF CK_REF Input reference clock Mix mode #3: MPU DPLL1/N DPLL1/M DPLL1/N...
Page 186 Clock Generation and Reset Management The TC clock frequency must be the same speed or slower than the MPU, DSP, and the DSP MMU clocks. Mix Modes Clock generation supports two mix modes. Mix mode #3 The MPU and TC clock domains are synchronous (same clock frequen- cy), and the DSP is scaled synchronous (synchronous but with a frequen- cy that is a multiple of the MPU/TC clock frequency).
Page 187 Clock Generation and Reset Management DPLL Modes The DPLL can operate either in bypass mode or in lock mode. Bypass mode In bypass mode (PLL_ENABLE bit of the DPLL1_CTL_REG register set to 0), the DPLL output clock can be CK_REF (input reference clock), CK_REF/2, or CK_REF/4, depending on the BYPASS_DIV bit-field value of the DPLL1_CTL_REG register.
Page 188 Clock Generation and Reset Management in bypass mode and switches to locked clock in an other 32 maximum reference clock cycles. If the DPLL was synthesizing a frequency prior to the idle state, the DPLL switches from bypass mode to synthesizer frequency when the lock state is reacquired.
Page 189 Clock Generation and Reset Management Even when the MPU is not in idle mode, you have the option of individually disabling the clock to the MPU subdomains via the ARM_IDLECT2 register. This allows power saving when a module is not used. 4.2.4 DSP Clock Domain Depending on the OMAP clocking mode, the DPLL1 output frequency defines...
Page 190 Clock Generation and Reset Management timers. At reset, the clock issued from the DPLL is selected but the timer clocks are inactive. DSP Level 1 and 2.0 interrupt handlers (DSP_INTH_CK) DSP interrupt handlers are supplied with CK_GEN2 divided by 2. Even when the DSP is not in idle mode, you have the option of individually disabling these subdomains using the DSP_IDLECT2 register.
Page 191 Clock Generation and Reset Management generate proper interrupts. This free-running clock for external LCD controller can only be cut off when the external LCD controller is in idle state. Power-Saving Modes and Wake-Up Control This section describes the following power-saving features: MPU idle control DSP idle control Traffic controller idle control...
Page 192 Clock Generation and Reset Management The ARM_CK is stopped in a low static state after some synchronization cycles. If the IDLCLKOUT_ARM bit field of ARM_IDLECT1 is set to 1, then the DPLL output clock also goes to idle after some synchronization cycles.
Page 193 Clock Generation and Reset Management (DSP_IDLECT1 and DSP_IDLECT2), different parts of the DSP subsystem go to idle mode when the IDLE instruction is executed. The following procedure describes how the DSP enters idle mode: 1) Disable the watchdog timer. When the timer/watchdog timer is configured as a watchdog, its clock (CK_REF/14) is never shut down.
Page 194 Clock Generation and Reset Management A wake-up sequence is initiated in DSP domain only upon one of the following events: A system reset A DSP reset An unmasked DSP interrupt request. The interrupt request restarts the DSP clock if the WKUP_MODE bit of ARM_IDLECT1 is set to 1 or if the chip is not in idle.
Page 195 Clock Generation and Reset Management OCP-T1/T2 modules are in idle mode. This can be done by setting ARM_IDLECT3 (IDLTC1_CK) = 1 and ARM_IDLECT3 (IDLTC2_CK) = 1, which disables the TC1_CK and TC2_CK clocks when there is no activity and the idle request is acknowledged by the target. These modules can also be placed in idle mode by disabling TC1_CK and TC2_CK completely by setting EN_TC1_CK and EN_TC2_CK to 0.
Page 196 Clock Generation and Reset Management The TC_CK restarts upon: An MPU or DSP interrupt request A DMA request L3_OCPI_EN pin set to logic 1 (enables restarting of the clock to L3 OCP initiator bus) System DMA Idle Control The system DMA employs a built-in power-saving mechanism. The clock is only requested to the clock generator when DMA transfers are occurring.
Page 197 Clock Generation and Reset Management with a programmable counter that delays the restart of all clocks from FLASH.RP signal going high. The EXTPWR bit field of the ARM_EWUPCT register permits the delay to be defined as follows: ± 1) x CK_REF = (EXTPWR (wake-up time) (field value)
Page 198 Clock Generation and Reset Management (sending a command from the MPU to DSP via the mailbox is one way to start this sequence). If the DSP has not been enabled after reset, it is only necessary to clear the ARM_CKCTL(EN_DSPCK) register bit to 0 in order to reach the idle state for this domain.
Page 199 Clock Generation and Reset Management An interrupt request from MPU interrupt handler. The MPU interrupt handler sets the nIRQ_SET signal to logic low and initiates the restarting of the ARM_CK, ARM_INTH_CK, Rhea_CK, DMA_CK, and TC_CK clocks. Depending on the setting of the ARM_IDLECT1/2 registers, peripherals clocks can also restart.
Page 200 Clock Generation and Reset Management Table 62. MPU Registers Base Address = 0xFFFE CE00 Name Description Offset ARM_CKCTL MPU clock control prescaler selection 0x00 ARM_IDLECT1 MPU idle enable control 1 0x04 ARM_IDLECT2 MPU idle enable control 2 0x08 ARM_EWUPCT MPU restore power delay 0x0C ARM_RSTCT1 Master software reset...
Page 201 Clock Generation and Reset Management Table 63. MPU Clock Control Prescaler Selection Register (ARM_CKCTL) (Continued) Base Address = 0xFFFE CE00, Offset = 0x00 Name Function Reset 11:10 DSPMMUDIV Define prescaler value from the frequency of CK_GEN2 to DSPMMU clock domain. 00: CK_GEN2 01: CK_GEN2/2 10: CK_GEN2/4...
Page 202 Clock Generation and Reset Management Table 63. MPU Clock Control Prescaler Selection Register (ARM_CKCTL) (Continued) Base Address = 0xFFFE CE00, Offset = 0x00 Name Function Reset LCDDIV Define prescaler value from the frequency of CK_GEN3 to LCD controller clock signal 00: CK_GEN3 01: CK_GEN3/2 10: CK_GEN3/4...
Page 203 Clock Generation and Reset Management Table 64. MPU Idle Enable Control Register 1 (ARM_IDLECT1) (Continued) Base Address = 0xFFFE CE00, Offset = 0x04 Name Function Reset WKUP_MODE Controls how the MPU can exit the CHIP_IDLE state 0: After the interrupt has been asserted, the MPU idle mode is exited upon a low level at the external CHIP_nWKUP pin.
Page 204 Clock Generation and Reset Management Table 64. MPU Idle Enable Control Register 1 (ARM_IDLECT1) (Continued) Base Address = 0xFFFE CE00, Offset = 0x04 Name Function Reset IDLIF_ARM Enables the TIPB bridge, the system DMA controller, and the TC to enter idle mode when the MPU processor executes the wait-for-interrupt instruction.
Page 205 Clock Generation and Reset Management Table 65. MPU Idle Enable Control Register 2 (ARM_IDLECT2) Base Address = 0xFFFE CE00, Offset = 0x08 Name Function Reset 31:12 RESERVED See note. 0000 EN_CKOUT_ARM This read-write bit enables the free running clock from DPLL1 output 0: The clock generated from DPLL1 output is stopped.
Page 206 Clock Generation and Reset Management Table 65. MPU Idle Enable Control Register 2 (ARM_IDLECT2) (Continued) Base Address = 0xFFFE CE00, Offset = 0x08 Name Function Reset EN_PERCK Enables the external peripheral clock. 0: The external peripheral clock ARMPER_CK is stopped. 1: The external peripheral clock ARMPER_CK is active and can be stopped depending on the IDLLPER_ARM bit.
Page 207 Clock Generation and Reset Management Table 66. MPU Restore Power Delay Register (ARM_EWUPCT) Base Address = 0xFFFE CE00, Offset = 0x0C Name Function Reset 31:6 RESERVED Reading these bits gives undefined values. Writing to 0x000 them has no effect. REPWR_EN Enables the external power control feature.
Page 208 Clock Generation and Reset Management Table 67. Master Software Reset Register (ARM_RSTCT1) (Continued) Base Address = 0xFFFE CE00, Offset = 0x10 Name Function Reset DSP_EN Resets the DSP. 0: Resets the DSP, excluding the configuration setting. The reset state is maintained as long as this bit is asserted low.
Page 209 Clock Generation and Reset Management Table 69. MPU Clock Reset Status Register (ARM_SYSST) Base Address = 0xFFFE CE00, Offset = 0x18 Name Function Reset 31:14 RESERVED Reading these bits gives undefined values. Writing to them has no effect. 13:11 CLOCK_SELECT Reading these bits indicates the clock_select pins and indicates the current clocking mode selection.
Page 210 Clock Generation and Reset Management Table 69. MPU Clock Reset Status Register (ARM_SYSST) (Continued) Base Address = 0xFFFE CE00, Offset = 0x18 Name Function Reset ARM_MCRST Indicates whether or not an MPU reset has occurred. This bit is cleared to 0 upon an external reset pulse asserting at the CHIP_nRESET pin, or by writing to it a logic 0.
Page 211 Clock Generation and Reset Management Table 70. MPU Clock Out Definition Register (ARM_CKOUT1) Base Address = 0xFFFE CE00, Offset = 0x1C Name Function Reset 31:6 RESERVED Reading these bits gives undefined values. Writing to 0x0000 them has no effect. TCLKOUT The POCLKOUT3 pin functions are: 00: Reserved 01: POCLKOUT3 pin is an output and reflects...
Page 212 Clock Generation and Reset Management Table 71. MPU Reserved Register (ARM_CKOUT2) Base Address = 0xFFFE CE00, Offset = 0x20 Name Function Reset 31:0 RESERVED Reading these bits gives undefined values. Writing 0x0000 to them has no effect. Table 72. MPU Idle Enable Control Register 3 (ARM_IDLECT3) Base Address = 0xFFFE CE00, Offset = 0x24 Name Function...
Page 213 Clock Generation and Reset Management Table 72. MPU Idle Enable Control Register 3 (ARM_IDLECT3) (Continued) Base Address = 0xFFFE CE00, Offset = 0x24 Name Function Reset EN_TC1_CK Enables the TC1 clock. This is a generic clock supplied to peripherals outside OMAP boundary and is at the same frequency as the TC clock.
Page 214 Clock Generation and Reset Management Table 73. DSP Registers (Continued) Base Address = 0xE100 8000 or 0x008000 Name Description Offset DSP_CKOUT1 DSP reserved register 3 0x1C DSP_CKOUT2 DSP reserved register 4 0x20 Table 74. DSP Clock Control Prescaler Selection Register (DSP_CKCTL) Base Address = 0xE100 8000 or 0x00 8000, Offset = 0x00 Name Function...
Page 215 Clock Generation and Reset Management Table 75. DSP Idle Enable Control Register 1 (DSP_IDLECT1) Base Address = 0xE100 8000 or 0x008000, Offset = 0x04 Name Function Reset 15:9 RESERVED Reading these bits gives undefined values. Writing to 0x00 them has no effect. IDLTIM_DSP Selects the idle entry mode for the internal DSP timer clock.
Page 216 Clock Generation and Reset Management Table 75. DSP Idle Enable Control Register 1 (DSP_IDLECT1) (Continued) Base Address = 0xE100 8000 or 0x008000, Offset = 0x04 Name Function Reset IDLXORP_DSP Selects idle entry mode for external reference peripheral clock. 0: The DSPXOR_CK clock remains active when DSP enter the idle mode.
Page 217 Clock Generation and Reset Management Table 76. DSP Idle Enable Control Register 2 (DSP_IDLECT2) (Continued) Base Address = 0xE100 8000 or 0x008000, Offset = 0x08 Name Function Reset EN_XORPCK Enables the external reference clock (DSPXOR_CK). 0: DSPXOR_CK clock is stopped. 1: DSPXOR_CK clock is active and can be stopped depending on the IDLXORP_DSP bit of DSP_IDLECT1.
Page 218 Clock Generation and Reset Management Table 79. DSP Peripherals Reset Register (DSP_RSTCT2) Base Address = 0xE100 8000 or 0x008000, Offset = 0x14 Name Function Reset 15:2 RESERVED Reading these bits gives undefined values. Writing to 0x0000 them has no effect. WD_PER_EN Controls the WD_DSPPER_nRST output, which can be used to reset the external peripherals connected...
Page 219 Clock Generation and Reset Management Table 80. DSP Clock Reset Status Register (DSP_SYSST) Base Address = 0xE100 8000 or 0x008000, Offset = 0x18 Name Function Reset 15:14 RESERVED Reading these bits gives undefined values. Writing to them has no effect. 13:11 CLOCK_SELECT These read-only bits reflect the CLOCK_SELECT...
Page 220 Clock Generation and Reset Management Table 80. DSP Clock Reset Status Register (DSP_SYSST) (Continued) Base Address = 0xE100 8000 or 0x008000, Offset = 0x18 Name Function Reset DSP_ARM_RST Used by the DSP to hold the MPU in reset. This is for test and debug purposes only.
Page 221 Clock Generation and Reset Management Table 81. DSP Reserved Register 3 (DSP_CKOUT1) Base Address = 0xE100 8000 or 0x008000, Offset = 0x1C Name Function Reset 15:0 RESERVED Reading these bits gives undefined values. Writing to 0x0000 them has no effect. Table 82.
Page 222 Clock Generation and Reset Management Table 83. DPLL Registers Base Address = 0xFFFE CF00 Name Description Offset DPLL1_CTL_REG DPLL1 control 0x00 DPLL2_CTL_REG DPLL2 control (all reserved) 0x100 Table 84. DPLL1 Control Register (DPLL1_CTL_REG) Base Address = 0xFFFE CF00, Offset = 0x00 Name Function Reset...
Page 223 Clock Generation and Reset Management Table 84. DPLL1 Control Register (DPLL1_CTL_REG) (Continued) Base Address = 0xFFFE CF00, Offset = 0x00 Name Function Reset 11:7 PLL_MULT DPLL multiply value. 00000 The maximum clock out frequency is 31 * CK_REF. PLL_DIV DPLL divide value. The minimum DPLL1 clock out frequency is CK_REF/4.
Page 224 MPU and MPUI Port Table 85. DPLL2 Control Register (DPLL2_CTL_REG) Base Address = 0xFFFE D000, Offset = 0x00 Reset Value Name Function 15:0 RESERVED Reserved. Do not write to these bits. 0x00002000 MPU and MPUI Port The MPU, system DMA, and OCP initiator (OCP-I) can access the DSP memories and peripherals via two interfaces: the MPUI and the MPUI port.
Page 225 MPU and MPUI Port Figure 43. OMAP 3.2 MPUI and MPUI Port Environment DSP subsystem OMAP Public core MPUI port RAM peripherals DSP MMU DARAM TIPB Flash TIPB bridge SARAM 16,32 Shared DSP DMA MPUI port peripherals T1/T2 Memory interface MPUI Endianism SDRAM...
Page 226 MPU and MPUI Port to which the MPUI has exclusive access. The DSP is denied access to the host-only RAM portion; however, both the MPUI and the DSP can access the other part of the SARAM (shared-access RAM). All access available to the MPUI in HOM remains available even if the DSP is in idle mode.
Page 227 MPU and MPUI Port big endian formats. The swapping logic is controlled by software to have maximum flexibility to handle different types of data, based on the BYTE_SWAP_CTL and WORD_SWAP_CTL bits of (MPUI_CONTROL) from the MPUI. The ability to turn the endianism on or off makes it more convenient for peripheral (control) register read/writes.
Page 228 SARAM memory space and SARAM start addresses, see the memory map in chapter 10. For detail on the translation of DSP internal (logical) addresses into OMAP (physical) addresses, see OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (literature number SPRU750).
Page 229 MPU and MPUI Port In HOM, the SARAM memory requests are completely asynchronous relative to the DSP clock. Therefore, memory accesses can be performed without resynchronization, allowing faster communication between MPU/system DMA/OCP-I and SARAM. Any access to DARAM or EMIF causes a bus error. In SAM, both DSP and MPU/system DMA/OCP-I can access the entire SARAM, DARAM, and EMIF (if API_SIZE in DSP_MPUI_CONFIG register equals 0xFFFF, the DSP can not access the SARAM).
Page 230 MPU and MPUI Port TIPB, the time-out counter is loaded with the value programmed in the TIMEOUT bits of (MPUI_CONTROL). If the current cycle is not finished when the counter reaches 0, the MPUI terminates the access and an abort exception is generated to the MPU/system DMA/OCP-I.
Page 231 MPU and MPUI Port HOM_M (host only for SARAM access) HOM_R (host only for DSP TIPB access) SAM_M (shared access for SARAM, DARAM, EMIF access) SAM_R (shared access for DSP TIPB access) Only the DSP can select HOM or SAM. This is controlled by the SMOD bits of (APIRS).
Page 232 MPU and MPUI Port 5.2.3 Memory Accesses in SAM When the MPUI port is in SAM_M mode, both the DSP and the MPU/system DMA/OCP-I can access the SARAM, DARAM, and EMIF. In this mode, the asynchronous host accesses from the MPU/system DMA/OCP-I are resynchronized on the DSP clock internally in the MPUI port logic.
Page 233 MPU and MPUI Port DMA/OCP-I write accesses are released before the write completion on the peripheral side. The MPU/system DMA/OCP-I is then free to carry on with the next access and the posted writes run as slots become available. This functionality can be turned off to aid in debugging, because when write posting is enabled it becomes difficult to attribute a bus error to a particular access.
Page 234 MPU and MPUI Port MPUI Port and MPUI Registers This section provides information about the MPUI port and MPUI registers. Table 88 lists the 16-bit MPUI port registers. Table 89 and Table 90 describe the register bits. Table 88. MPUI Port Registers Base Address = 0xE102 0000 Name Description...
Page 235 MPU and MPUI Port Table 90. MPUI Port Control/Status Register (APIRS) (Continued) Base Address = 0xE102 0000, Offset = 0x02 Name Function Reset SMOD [1:0] HOM or SAM setting for MPUI port RAM and DSP R by TIPB peripherals. MPU/system DMA/OCP-I 00: SAM for MPUI port RAM and DSP TIPB.
Page 236 MPU and MPUI Port Table 91. MPUI Registers (Continued) Base Address = 0xFFFE C900 Name Description Offset MPUI_STATUS MPUI status register 0x10 DSP_STATUS DSP status register 0x14 DSP_BOOT_CONFIG DSP boot configuration register 0x18 DSP_MPUI_CONFIG MPUI port RAM configuration register 0x1C DSP_MISC DSP miscellaneous 0x20...
Page 237 MPU and MPUI Port Table 92. MPUI Control Register (MPUI_CONTROL) (Continued) Base Address = 0xFFFE C900, Offset = 0x00 Name Function Reset 17:16 BYTE_SWAP_CTL Bits to control byte swap between MPUI and MPUI port (see note below): 00: Turn off byte swap for all accesses 01: Byte swap only for DSP TIPB peripheral and MPUI port control/ status register accesses 10: Byte swap for all accesses...
Page 238 MPU and MPUI Port Table 92. MPUI Control Register (MPUI_CONTROL) (Continued) Base Address = 0xFFFE C900, Offset = 0x00 Name Function Reset API_ERR_EN Send MPUI port abort. 0: Mask the abort 1: An abort signal is forwarded by MPUI to the MPU for an aborted MPUI port transaction.
Page 239 MPU and MPUI Port Table 94. Debug Data Register (DEBUG_DATA) Base Address = 0xFFFE C900, Offset = 0x08 Name Function Reset 31:0 DATA_SAV The value of MPU/OCP-I/system DMA data input 0xFFFFFFFF bus is saved when a read access has a size mismatch, and the MPU data output bus is saved when a write access is aborted or has a size mismatch.
Page 240 MPU and MPUI Port Table 95. Debug Flag Register (DEBUG_FLAG) (Continued) Base Address = 0xFFFE C900, Offset = 0x0C Name Function Reset BURST_SIZE_SAV System bus data burst size indicated from MPU core on abort. Can be used in conjunction with BURST_SIZE_ERR flag bit.
Page 241 MPU and MPUI Port Table 96. MPUI Status Register (MPUI_STATUS) Base Address = 0xFFFE C900, Offset = 0x10 Name Function Reset 31:13 Reserved 0x0000 12:11 ACCESS_STATUS Current access in progress is: 00: MPU access 01: System DMA access 10: OCP-I access 11: No access 10:3 TIMEOUT_VAL...
Page 242 MPU and MPUI Port Table 97. DSP Status Register (DSP_STATUS) (Continued) Base Address = 0xFFFE C900, Offset = 0x14 Name Function Reset PENRESETDPLL Reflects level of asynchronous reset in the DSP (controlled by emulation) PEIDLE7 Idle peripherals flag. Reflects bit 7 of (ISTR) from the DSP.
Page 243 MPU and MPUI Port Table 98. DSP Boot Configuration Register (DSP_BOOT_CONFIG) (Continued) Base Address = 0xFFFE C900, Offset = 0x18 Name Function Reset BOOT_RHEA_PTR1 User-defined pointer that can be used for 000000 application-specific boot code location DSP_BOOT_MODE DSP boot mode inputs. 0000 Table 99.
Page 244 MPU and MPUI Port Table 102. DSP SARAM Configuration Map API SIZE SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM 0x0000−0x0001 0000 0000 0000 0000 0000 0000 0000 0000 0x0002−0x0003 0000 0000 0000 0000 0000 0000 0000 0001 0x0004−0x0005 0000 0000 0000 0000...
Page 245 Mailboxes Table 102. DSP SARAM Configuration Map (Continued) API SIZE SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM 0x0034−0x0035 0000 0011 1111 1111 1111 1111 1111 1111 0x0036−0x0037 0000 0111 1111 1111 1111 1111 1111 1111 0x0038−0x0039 0000 1111 1111 1111 1111 1111...
Page 246 Mailboxes MPU2DSP1A and MPU2DSP1B for mailbox1 MPU2DSP2A and MPU2DSP2B for mailbox2 The sequence is as follows: An interrupt for the DSP is generated when the MPU/DMA/OCP-I writes to the second register; that is, MPU2DSP1B or MPU2DSP2B. Writing to the first registers MPU2DSP1A or MPU2DSP2A does not generate an interrupt.
Page 247 Mailboxes For example, if the MPU sets MPU2DSP1_FLAG by writing to MPU2DSP1B, the MPU has no write access to MPU2DSP1A or MPU2DSP1B until the DSP clears the interrupt flag by reading the MPU2DSP1B. Because a processor cannot write to registers associated with an interrupt after the interrupt flag has been set up, both processors must write the data or command that needs to be communicated before setting the interrupt flag register.
Page 248 Mailboxes Registers All these registers are 16-bit aligned on a 32-bit address boundary. The DSP-to-MPU mailbox registers are written by the DSP and read by the MPU/DMA/OCP-I, while the MPU-to-DSP mailbox registers are written by the MPU/DMA/OCP-I and read by the DSP. Table 104 lists the mailbox registers. Table 105 through Table 116 provide register bit descriptions.
Page 249 Mailboxes Table 106. MPU to DSP Mailbox 1B Register (MPU2DSP1B) Base Address = 0xFFFC F000, Offset = 0x04 Name Function Reset 15:0 MPU2DSP1B This register stores the data to be shared R/W by MPU/DMA/OCP-I 0x0000 for the MPU-to-DSP interrupt in mailbox 1. R by DSP The MPU2DSP1 interrupt is generated to DSP when this register is written.
Page 250 Mailboxes Table 110. DSP to MPU Mailbox 2B Register (DSP2MPU2B) Base Address = 0xFFFC F000, Offset = 0x14 Name Function Reset 15:0 DSP2MPU2B This register stores the data to be shared for R/W by DSP 0x0000 the DSP-to-MPU interrupt in mailbox 2. The R by MPU/DMA/OCP-I DSP2MPU2 interrupt is generated to MPU/DMA/OCP-I when this register is...
Page 251 TIPB Bridge Table 114. MPU to DSP Mailbox 2A Register (MPU2DSP2A) Base Address = 0xFFFC F000, Offset = 0x24 Name Function Reset 15:0 MPU2DSP2A This register stores the data to be shared R/W by MPU/DMA/OCP-I 0x0000 for the MPU-to-DSP interrupt in mailbox 2. R by DSP Table 115.
Page 252 TIPB Bridge Figure 44. OMAP 3.2 Platform TI Peripheral Bridge TIPB peripherals TIPB bridge Private TIPB (private) MPU− DMA/OCP-I System arbiter Public TIPB TIPB controller DMA/OCP-I bridge arbiter (public) L3 OCP-I TIPB peripherals port TIPB bridge configuration registers Functionality This section describes the functionality of the TI peripheral bus bridge. 7.1.1 Bus Allocation The TIPB is shared between the MPU memory interface, the OCP initiator...
Page 253 TIPB Bridge 7.1.2 Access Permissions Access permissions to the MPU public and private TIPBs vary with initiator and target. The MPU has unconditional access permissions to the MPU public and private TIPBs. The system DMA has unconditional access permission to the MPU public TIPB and conditional, software-controlled access permission to the MPU private TIPB.
Page 254 TIPB Bridge handles the access to the TIPB peripheral so that the MPU is not stalled during the access. If the MPU/system DMA/OCP-I performs another TIPB operation when there is a posted write, this operation must wait until the posted write is complete. If the system DMA or OCP-I performs a read operation to the same address as the posted write, the posted write data is not forwarded to the DMA or OCP-I.
Page 255 TIPB Bridge Table 117 provides a list of the TIPB registers. Table 118 through Table 126 provide register bit descriptions. Table 117. TIPB Registers Base Address = 0xFFFE D300 (public), 0xFFFE CA00 (private) Name Description Offset RHEA_CNTL TIPB control 0x00 RHEA_BUS_ALLOC TIPB allocation control 0x04...
Page 256 TIPB Bridge Table 118. TIPB Control Register (RHEA_CNTL) (Continued) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x00 Name Function Reset ACCESS_FACTOR1 Clock period multiplication factor for TIPB strobe 1. Allows access to slow peripherals by lengthening TIPB strobe 1 period by a multiple of the internal TIPB bridge clock period.
Page 257 TIPB Bridge Table 118. TIPB Control Register (RHEA_CNTL) (Continued) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x00 Name Function Reset ACCESS_FACTOR0 Clock period multiplication factor for TIPB strobe 0. Allows access to slow peripherals by lengthening TIPB strobe 0 period by a multiple of the internal TIPB bridge clock period.
Page 258 TIPB Bridge Table 119. TIPB Allocation Control Register (RHEA_BUS_ALLOC) (Continued) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x04 Name Function Reset FIXNROUND_PRIORITY Type of priority scheme used in DMA and OCP-I arbitration: 0: Round-robin scheme used 1: Fixed priority scheme used PRIORITY_ENABLE 0: TIPB bus allocation is done using the...
Page 259 TIPB Bridge Table 121. Enhanced TIPB Control Register (ENH_RHEA_CNTL) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x0C Name Function Reset 15:4 Reserved 0x000 MASK_ABORT 0: An abort signal is sent to the MPU whenever an MPU to TIPB access is aborted.
Page 260 TIPB Bridge Table 124. Debug Data MSB Register (DEBUG_DATA_MSB) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x18 Name Function Reset 15:0 DATA_DBG_HIGH Bits 31 to 16 of data bus from MPU. The value of the 0xFFFF MPU data input bus is saved when a read access has a size mismatch, and the MPU data output bus is saved when a write access is aborted or has a size mismatch.
Page 261 TIPB Bridge Table 125. Debug Control Signals Register (DEBUG_CTRL_SIGNALS) (Continued) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x1C Name Function Reset DBG_NSUPV Indicates supervisor mode status of MPU; saved when abort or access size mismatch occurs. 0: Processor in supervisor mode 1: Processor not in supervisor mode DBG_RNW...
Page 262 TIPB Bridge Table 126. Access Control Register (ACCESS_CNTL) (Continued) Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x20 Name Function Reset MASK_DMA 1: The abort for DMA access is masked before NABORT sending back to the DMA. 0: The abort for DMA access is sent back to the DMA.
Page 263 MPU level 1 interrupt handler 21 MPU peripherals 22 system DMA 23 MPU level 1 interrupt handler OMAP3.2 Mailboxes 22 OMAP3.2 memory traffic controller 22 OMAP3.2 MPU peripherals 22 OMAP3.2 buses 25 OMAP3.2 subsystem, introduction 19 OMAP3.2 DPLLs 25 OMAP3.2 system DMA 23 SPRU749A OMAP5912...
Page 264 OMAP5912 Multimedia Processor DSP Subsystem Reference Guide Literature Number: SPRU750A March 2004...
Page 265 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 266 OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
Page 267 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 268 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU750A...
Page 269 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 270 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 271 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 272 ............SPRU750A OMAP5912...
Page 273 ..........OMAP5912...
Page 274 ......... . SPRU750A OMAP5912...
Page 275 ........OMAP5912...
Page 276 ......External Memory Boot Table for 32-Bit Boot Download ......SPRU750A OMAP5912...
Page 277 OMAP5912 SPRU750A...
Page 278: Architecture Overview
DSP Subsystem This chapter describes the OMAP5912 multimedia processor DSP subsystem. Architecture Overview The digital signal processor (DSP) subsystem is built around a core processor and peripherals that interface with: The ARM926EJS via the microprocessor unit interface (MPUI) Various standard memories via the external memory interface (EMIF) Various system peripherals via the TI peripheral bus (TIPB) bridge Figure 1 shows the DSP subsystem and the modules with which it interfaces.
Page 279 Architecture Overview Figure 1. DSP Subsystem and Modules DSP private MPU/DSP shared peripherals DSP subsystem and interfaces peripherals Timer Mailbox DSPTM_CK (1 INT) MPU/DSP static Endianism Internal shared conversion EMIF memory 8 x GPTIMERS WD timer buses TMS320C55x DSPWD_CK UART1,2,3 DSP core (1 INT) I 2 C...
Page 280: Dsp Core
Architecture Overview The DSP subsystem has the following components: DSP module: TMS320C55x (C55x) DSP CPU core revision 2.11 Tightly coupled hardware accelerator: discrete cosine transform/ inverse discrete cosine transform (DCT/IDCT), motion estimation, and half-pixel interpolation Tightly coupled memories and their interfaces: dual-access RAM (DARAM), single-access RAM (SARAM), programmable dynamic ROM (PDROM), and instruction cache (I-cache) External memory interface (EMIF) that connects the CPU to external...
Page 281: Tms320C55X Dsp Cpu Overview
TMS320C55x DSP CPU Overview Figure 2. DSP Core and Internal Bus Designations Private Trace FIFO TIPB bridge C,D,E,F DSP CPU core Shared plus hardware accelerator (DCT/IDCT motion estimation half-pixel interpolation EMIF I-Cache bridge DMA controller 6 channels, 5 ports P,B,C,D,E,F SARAM 96K bytes P,B,C,D,E,F...
Page 282: On-Chip Memory
TMS320C55x DSP CPU Overview Unified program/data memory architecture Dual 17-bit x17-bit multipliers coupled to 40-bit dedicated adders for non-pipelined single-cycle multiply accumulate (MAC) operations Add/compare/select (CSSU) unit for the add/compare section of the Viterbi operator Exponent encoder to compute an exponent value of a 40-bit accumulator value in a single cycle Two address generators with eight auxiliary registers and two auxiliary register arithmetic units...
Page 283: Hardware Acceleration Modules
Automatic power management Advanced low-power complimentary metal-oxide semiconductor (CMOS) process Hardware Acceleration Modules The OMAP5912 device contains several hardware acceleration modules to improve performance and reduce power consumption for certain computations relating to image and video processing. These coprocessors include:...
Page 284 TMS320C55x DSP CPU Overview Figure 3 shows the C55x DSP architecture. Figure 3. C55x DSP Architecture Data read address buses bb, cb, db (3 x 16) Data read address buses BAB, CAB, DAB (3 x 24) Program address bus PAB (24) TMS320C55x DSP Auxiliary Instruction buffer...
Page 285: Dsp Memory
DSP Memory TMS320C5510 DSP Functional Overview (SPRU312) (only CPU sections apply to the OMAP5912 device) DSP Memory The DSP subsystem contains four types of tightly coupled memory to provide maximum efficiency of the DSP CPU. Dual-access RAM (DARAM) Single-access RAM (SARAM)
Page 286: Internal Memory
DSP Memory Figure 4. DSP Memory Connections 12 blocks of 8K bytes 8 blocks of 8K bytes 1 block of 32K bytes DARAM SARAM PDROM P bus B bus C bus external memory D bus E bus F bus Internal Memory The DARAM (64K bytes) can support up to two memory accesses in one CPU clock cycle into each RAM block.
Page 287: Cache Memory Organization
DSP Memory significantly improve the CPU performance by buffering the instructions most recently fetched from external memory. The entire external program memory space is cacheable. The I-cache total size is 24K bytes divided into three memory banks. Two 8K-byte banks are traditional cache modules. The third module is a special type of cache called ramset, which is divided into two 4K-byte blocks.
Page 288: Ramset Memory Organization
DSP Memory block consists of 512 cache lines containing 16 bytes (4 words) of instructions from consecutive addresses. Control and status bits are associated with each cache line to support virtual to physical mapping and cache control/operation. A 24-bit program virtual address is parsed into word, line index, and TAG sections, as shown in Figure 5.
Page 289 DSP Memory The two-way set associative cache has an extra status bit for each cache line index. The least recently used (LRU) bits are associated with the pair of cache lines assigned to the same line index. The LRU bit indicates which of the two cache lines did not have the last cache hit.
Page 290: Ramset Structure
DSP Memory 3.2.4 Ramset Structure Ramset memory uses the live valid bit (LVB) to indicate whether or not an individual line in the memory block is valid like regular cache memory. In addition, there is a TAG valid bit (TVB) associated with each ½ ramset memory block that indicates whether the TAG entry is valid.
Page 291: Instruction Cache Configuration
DSP Memory cache hit, the word number is used to select which word from the cache line is returned to the DSP to complete the fetch request. When ½ ramset memory is enabled, the presence check is performed on both the cache and ramset blocks simultaneously.
Page 292: I/O Mapped Cache Control Registers
DSP Memory Table 2. ST3 CPU Register (ST3) Name Description CAFRZ Instruction cache freeze CAFRZ = 1: The cache contents are locked. In this mode, the cache contents are not updated on a cache miss, but its contents still are available for cache hits.
Page 293 DSP Memory Table 3. Global Control Register (GCR) (Continued) Name Description Access Global Flush Global flush configuration: 0: The flush configuration must take into account the specific flush bits (n-way and ½ ramset). 1: All the I-cache is flushed when CACLR = 1. (Line valid bits are invalidated and ramset tag valid bit is invalidated.) ½...
Page 294 DSP Memory Table 4. Flush Line Register 0 (FLR0) Name Description Access 15:0 Line address Low 16 bits of line address: byte address This address is used to select the line when a flush line occurs. Table 5. Flush Line Register 1 (FLR1) Name Description Access...
Page 295: Lvb And Lru Status Registers
DSP Memory When either the ½ ramset1..2 or TAG registers are written through Debug mode the TIPB bus in debug mode, this bit is set. This bit is reset to 0 if this register is read in normal operation; it is not reset to 0 if this register is read during emulation.
Page 296: I-Cache Operations
DSP Memory 0x1620 0x163F 512 LVBs of bank1 = 32 words 0x1640 0x165F 512 LVBs of bank2 = 32 words 0x1660 0x167F 512 LRUs = 32 words I-Cache Operations 3.4.1 Enable and Disable I-Cache The cache and ramset modules can be enabled together by setting the global enable bit in GCR, in conjunction with the way/ramset presence bits.
Page 297: Freeze Mode
DSP Memory I-cache is enabled. The CAEN = 1 request to enable the I-cache is not instantaneous, and latency can occur before the I-cache is truly enabled. RTR1/2 can be changed to map ramsets to different locations anytime when the I-cache is enabled. Again, note that the ramset must be used in conjunction with the cache memory (two-way or direct).
Page 298: Flush I-Cache
DSP Memory 1) Set the GCR to have the following settings: a) Global enable = 1 b) Way presence = 1 c) Way number = 00 d) ½ ramset presence = 1 e) ½ ramset number = 0000 Streaming = 1 g) Line_Fill_Mode = 1 2) Set the NWCR to have the following settings: a) Way size = 011...
Page 299: Flush Cache Line
DSP Memory 2) Write CACLR = 1 in DSP CPU ST3 register. Once the I-cache has been flushed, the CACLR bit is automatically reset to 0. 3.5.4 Flush Cache Line This operation flushes a single line in the cache (for example, when an instruction is directly modified in the external memory by the software): 1) Write the address, which identifies the flush line (see the flush line address register: FLAR).
Page 300: I-Cache Performance
DSP Memory All the line valid bits of the ½ ramset are then invalidated, as well as the TAG_ VALID bit. I-Cache Performance The I-cache performances can be characterized by: Average memory-access time = (Hit rate* Hit time) + (Miss rate * Miss penalty.) Hit time is described in Section 3.6.1 and miss penalty is described in Section 3.6.2.
Page 301: Emulation Mode
DSP Memory X+7 cycles: I-cache returns data. All in all, X + 7 cycles are required for the first access. If a second request is issued that is also a miss but lies in the present occurring line fill, those requests either fill with streaming as the data is returned by the EMIF or wait for the present line fill to complete before returning the data.
Page 302: Memory Map
DSP Memory three system memory interfaces: internal memory (IMIF), slow external memory (EMIFS), or fast external memory (EMIFF). If the MMU is not enabled, then the access request is passed directly to the system traffic controller. In this case, the DSP virtual addresses are mapped to the first 16M bytes of CS0 of the system memory.
Page 303 * The DMA controller references byte addresses. SARAM To access control and data registers associated with various OMAP5912 peripherals, the DSP uses 16-bit I/O space. This space is referenced 96K bytes by using appropriate I/O access qualifiers with load or store instructions.
Page 304 DSP Memory Table 11. I/O Spaces Byte Name Word 00000 TIPB bridge 00000 00800 EMULATOR/TEST 00400 01000 STIO(EMIF) 00800 01800 00C00 02000 01000 02800 ICACHE 01400 03000 01800 03800 01C00 04000 TRACE 02000 04800 Configurable (private/shared) 02400 05000 TIMER 1 02800 05800 TIMER 2...
Page 305 DSP Memory Table 11. I/O Spaces (Continued) Byte Name Word 10C00 08600 11000 McBSP2 08800 11400 GPTIMER1 08A00 11800 McBSP1 08C00 11C00 GPTIMER2 08E00 12000 MCSI2 09000 12400 GPTIMER3 09200 12800 MCSI1 09400 12C00 GPTIMER4 09600 13000 09800 13400 GPTIMER5 09A00 13800 C multimaster...
Page 306: Peripheral Register Addresses
0CE00 1A000 0D000 1A400 (reserved) 0D200 1A800 0D400 1B000 0D800 1B800 0DC00 1C000 0E000 1C400 32-kHz synchronization timer 0E200 1C800 OMAP5912 TIPB switch 0E400 1CC00 0E600 1D000 0E800 1D400 GPTIMER8 0EA00 1D800 0EC00 1E400 GPIO1 0F200 1EC00 GPIO2 0F600 1F000...
Page 307 DSP Memory An interrupt handler MPU/DSP shared peripherals MMCSDIO2 GPIO (x4) DSP public peripherals Two multichannel buffered serial ports (McBSPs) for synchronous serial communications Two multichannel serial interfaces (MCSIs) Configuration and data registers for all peripherals reside in the DSP subsystem I/O space, which consists of 64K-word addresses, with each peripheral mapping into a 1K-word section of I/O memory.
Page 308 DSP Memory Table 12. DSP Peripheral Mapping (Continued) Start Byte Address (hex) Name Strobe x 004800 Configurable (private/shared) Strobe0/n x 005000 TIMER 1 Stroben x 005800 TIMER 2 Stroben x 006000 TIMER 3 Stroben x 006800 WD_TIMER Stroben x 007000 DSPINT IF Stroben x 007800...
Page 309 DSP Memory Table 12. DSP Peripheral Mapping (Continued) Start Byte Address (hex) Name Strobe X01 2800 MCSI1 Strobe1 X01 2C00 GPTIMER4 Strobe1 X01 3000 Reserved Strobe1 X01 3400 GPTIMER5 Strobe1 X01 3800 C multimaster Strobe1 X01 3C00 GPTIMER6 Strobe1 X01 4000 Reserved Strobe1 X01 4800...
Page 310: Tipb Bridge
X01 B000 Reserved Strobe1 X01 B800 Reserved Strobe1 X01 C000 Reserved Strobe1 X01 C400 32-kHz synchronization timer Strobe1 X01 C800 OMAP5912 TIPB switch Strobe1 X01 CC00 Reserved Strobe1 X01 D000 Reserved Strobe1 X01 D400 GPTIMER8 Strobe1 X01 D800 Reserved Strobe1...
Page 311 TIPB Bridge The private TIPB bridge provides a preconfigured bus interface to peripherals residing on the the DSP private TIPB. The public TIPB bridge provides a user-configurable interface to peripherals on the DSP public TIPB. It includes functions to tailor the interface timing to the complement of peripherals operating at a given time.
Page 312 TIPB Bridge Figure 10. DSP Subsystem Modules DSP private MPU/DSP shared peripherals DSP subsystem and interfaces peripherals Timer Mailbox DSPTM_CK (1 INT) Endianism MPU/DSP static conversion shared EMIF Internal 8 x GPTIMERS memory WD timer TMS320C55x buses DSPWD_CK DSP core UART1,2,3 (1 INT) I 2 C...
Page 313: Control Mode Register
TIPB Bridge Control Mode Register The control mode register (CMR) indicates the shared-access mode/host-only mode (SAM/HOM) status of the MPUI and bus error condition status for accesses to the TIPB bridge. It also controls CPU priority versus the MPUI and DMA for accesses to peripherals on the TIPB bridge.
Page 314 McBSP3 (optical) MCSI-1 MCSI-2 GPIO Mailbox DSP MPUI register OMAP5912 TIPB switch GP timer (x8) 32-kHz synchronization timer MMCSDIO2 GPIO (x4) The control mode register bits [5−3] and [8−6] contain the number of wait states required to generate the appropriate strobe frequency (see Table 14).
Page 315 TIPB Bridge Table 14. Wait States Number of Wait States Strobe Period DSP clk/2 DSP clk/3 DSP clk/4 DSP clk/5 DSP clk/6 DSP clk/7 DSP clk/8 DSP clk/9 Time-out[6:0] This field specifies the number of cycles that can elapse before the TIPB returns a bus error condition.
Page 316 TIPB Bridge EMIF The DSP DPLL is controlled by the MPU subsystem. When entering low-power mode requiring DSP DPLL off, the DSP sets DPLL idle domain on, followed by the MPU idling the DPLL source by writing the appropriate control registers (see Chapters 4 and 5).
Page 317: Mpu Interface
DMA controller to communicate with the DSP and its peripherals, facilitating software downloads and data transfers. For additional information, please see OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (literature number SPRU749). The MPUI provides the MPU with access to the full memory space of the DSP (16M bytes).
Page 318 MPU Interface The MPU domain (including ARM926EJS and system DMA) always masters the transfer operation. It initiates the read or write of DSP memory or peripherals. The MPU also controls the parameters of the MPUI by configuring the MPUI_CTRL_REG and the MPUI_DSP_MPUI_CONFIG register. There are five additional registers the MPU can read to observe the state of the MPUI: MPUI_DEBUG_ADDR MPUI_DEBUG_DATA...
Page 319: Hom/Sam Change Outside Of Reset
MPU Interface HOM/SAM Change Outside of Reset Only the DSP can invoke a HOM/SAM change outside of reset. The mode change is initiated by a DSP write to HOM_P bit (bit 8) and HOM_R bit (bit 9) of the ST3 register. The appropriate bit is written to request the SAM_M/HOM_M or SAM_P/HOM_P change.
Page 320: External Memory Interface
External Memory Interface 1: On The MPUI RAM is owned only by the host processor. If you set the HOM_R bit, a request for host-only mode is sent to the MPUI. If the MPUI sets the HOM_R bit, the setting indicates that the host processor has exclusive ownership of the MPU RAM.
Page 321: Emif Global Reset Register
The DSP MMU maps the 16M bytes of the DSP virtual external addresses to anyplace in the 4G-byte address space of the OMAP5912 device. At reset the MMU is disabled and the DSP external memory space is mapped to the first 16M bytes of CS0 system memory.
Page 322 DSP Memory Management Unit The DSP MMU contains a 32-entry translation lookaside buffer (TLB) that holds translations and permissions for current pages. This TLB is often managed statically by the MPU OS; but the MMU also includes hardware table walking logic, as in the MPU, to autonomously traverse the page table on a TLB miss.
Page 323: Address Translation
DSP Memory Management Unit Figure 11. DSP MMU Architecture 0 0 Not valid 0 0 Section (1MB) AP (Access Permission) 0 1 Large page (64KB) 1 0 Small page (4KB) 1 1 Tiny page (1KB) Page descriptor from: Physical address TI Peripheral (PA) TIPB...
Page 324: Translation Process
DSP Memory Management Unit The MPU software typically loads the TLB entries of the MMU before enabling the MMU (Mmu_en bit in CNTL_REG). When the MMU is disabled, no translation is done, the host addresses pass through untranslated, and no permission checks or table walking are performed.
Page 325 DSP Memory Management Unit Figure 12 shows an example of how the physical address is built with the logical address. Figure 12. Address Translation Process for a Section Logical address 20 19 Table index Section index Search in CAM entries CAM - table index Indexed in MMU RAM 20 19...
Page 326 DSP Memory Management Unit Figure 13 shows the translation table hierarchy. The physical address is built with the logical address. As with the MPU, the page table may be hierarchical, as shown in Figure 13. Figure 13. Translation Table Hierarchy Translation table Section MS_ADD(19:0)
Page 327: Page Table Format
DSP Memory Management Unit 7.2.2 Page Table Format Figure 14. Level One Descriptor 31:20 19:12 11:10 0 Fault Coarse page table base address 1 Coarse page Section base address 0 Section Fine page table base address 1 Fine page Note: AP = Protection bits for the page.
Page 328 DSP Memory Management Unit Figure 16 shows the translation for a section. Figure 16. Translation for a Section DSP virtual address 2019 P/D: 0 Program address Table index Section index 1 Data address Translation table base Translation base Translation base Table index First level descriptor 2019...
Page 329 DSP Memory Management Unit Figure 17 and Figure 18 show how the physical address is built as a function of the page sizes and hierarchy. Figure 17. Translation for a Large Page Included in a Coarse Page DSP virtual address 20 19 AP: Protection of the Table index...
Page 330 DSP Memory Management Unit Figure 18. Translation for a Small Page Included in a Coarse Page DSP virtual address 20 19 12 11 Table index L2 table index Page index Translation table base Translation base Translation base Table index First level descriptor Page table base address L2 table index Page table base address...
Page 331 DSP Memory Management Unit 7.2.4 Fine Page Tables Fine page tables have 1024 entries, and each entry describes 1K byte. These entries provide a base address for tiny, small, or large pages. Small page descriptors must be repeated in four consecutive entries. Large page descriptors must be repeated in 64 consecutive entries.
Page 332 DSP Memory Management Unit Figure 19. Translation for a Large Page Included in a Fine Page DSP virtual address 20 19 Page index Table index L2 Table index Translation table base Translation base Translation base Table index First level descriptor Page table base address L2 Table index Page table base address...
Page 333 DSP Memory Management Unit Figure 20. Translation for a Small Page Included in a Fine Page Logic address 20 19 11 10 Table index L2 table index Page index Translation table base Translation base Table index Translation base First level descriptor Page table base address L2 table index Page table base address...
Page 334 DSP Memory Management Unit Figure 21. Translation for a Tiny Page Included in a Fine Page DSP virtual address 20 19 Page index L2 table index Table index Translation table base Translation base Translation base Table index First level descriptor Page table base address L2 table index Page table base address...
Page 335 DSP Memory Management Unit Figure 22. DSP Memory Request Results Example DSP External access (or 1 access of a burst) TLB miss TLB hit Check permission Page Fault Invalid Valid Table walker Table walker Memory access Permission fault enabled disabled DSP continue execution Stall DSP, generate MPU interrupt...
Page 336 DSP Memory Management Unit 7.3.3 Fault Handling The following types of faults may occur: TLB miss with table walker disabled TLB entries can be locked from [Base_value−1] down to 0. No translation is found for the logical address required. If the hardware table walker is disabled, a fault is generated.
Page 337 DSP Memory Management Unit 7.3.5 Table Walking Logic The entire TLB can be flushed at once by setting the global_flush bit in the GFLUSH_REG register. TLB entries with a preserved bit set to 1 (bit P of the CAM_L_REG register) are not flushed. Regardless of the preserved bit setting, a specific TLB entry can be flushed by setting the flush_entry bit in the FLUSH_ENTRY_REG register.
Page 338 DSP Memory Management Unit 7.3.6 Boot After reset, the TLB is empty, the MMU is disabled, and the DSP is held in reset. The fields of LOCK_REG must be initialized from the MPU before enabling the MMU. TLB entries can then be initialized as needed, starting from entry zero and incrementing current_victim in LOCK_REG as each entry is written.
Page 339 DSP Memory Management Unit Table 19. DSP MMU Registers Base Address = FFFE D200 Name Description Offset PREFETCH_REG Prefetch register 0x00 WALKING_ST_REG Status CNTL_REG Control FAULT_AD_H_REG MSB fault address FAULT_AD_L_REG LSB fault address FAULT_ST_REG Fault status IT_ACK_REG It acknowledge TTB_H_REG MSB TTB TTB_L_REG LSB TTB...
Page 340 DSP Memory Management Unit Table 20. Prefetch Register (PREFETCH_REG) Base Address = FFFE D200, Offset = 000 Name Function Reset 31:14 Unused 0x00000 13:0 PrefAddr MSB of virtual address of the TLB entry to be prefetched. Table 21. Status Register (WALKING_ST_REG) Base Address = FFFE D200, Offset = 004 Name Function...
Page 341 DSP Memory Management Unit Table 23. MSB Fault Address Register (FAULT_AD_H_REG) Base Address = FFFE D200, Offset = 00C Name Function Reset 31:8 Unused Fault_address_msb MSB of logical address of the access that generated a permission fault Table 24. LSB Fault Address Register (FAULT_AD_L_REG) Base Address = FFFE D200, Offset = 010 Name Function...
Page 342 DSP Memory Management Unit Table 27. MSB TTB Register (TTB_H_REG) Base Address = FFFE D200, Offset = 01C Name Function Reset 31: 16 Unused 15:0 TTB_H_REG MSB of TTB Table 28. LSB TTB Register (TTB_L_REG) Base Address = FFFE D200, Offset = 020 Name Function Reset...
Page 343 DSP Memory Management Unit Table 31. MSB of CAM Entry Register (CAM_H_REG) Base Address = FFFE D200, Offset = 02C Name Function Reset 31:16 Unused 15:0 VA_tag_l1_H Table index level 1 MSB Should be used only when WTL_EN is disabled Table 32.
Page 344 DSP Memory Management Unit Table 34. LSB of RAM Entry Register (RAM_L_REG) Base Address = FFFE D200, Offset = 038 Name Function Reset 15:10 Ram_lsb LSB physical address Access permission bits Unused Table 35. Global Flush Register (GFLUSH_REG) Base Address = FFFE D200, Offset = 03C Name Function Reset...
Page 345 DSP Memory Management Unit Table 38. LSB Read CAM Register (READ_CAM_L_REG) Base Address = FFFE D200, Offset = 048 Name Function Reset 31:16 Unused 15:14 VA_tag_l1_L Table index level 1 LSB which means bits (21:20) of logical address 13:4 VA_tag_l2 Table index level 2: Tiny page: bits 13:4 Small page: bits 13:6, rest of bits discarded...
Page 346 OMAP5912. The clock domains in the OMAP5912 platform are synthesized by the DPLL1. The DPLL input clock source is externally supplied from the CLKIN pin.
Page 347 TIPB CMR register. See Section 4.1, Control Mode Register. Boot Mode for DSP Subsystem The OMAP5912 device contains a bootloader that is a ROM-based utility residing in the DSP subsystem ROM. It consists of a program (code) that...
Page 348 System Operating Details facilitates downloading (bootloading) of DSP code into the DSP subsystem internal memory from either the DSP EMIF interface to the traffic controller or the MPUI interface when it is held in reset by the MPU. The boot mode used by the DSP subsystem bootloader is specified by the MPU using the DSP_BOOT_CONFIG register when it is released from reset by the MPU.
Page 349 System Operating Details Table 43. Boot Modes BOOT_MOD[3−0] Boot Process Starting Address of DSP MPU 0000 No boot download 0xFFFF00 (direct boot from a 32-bit asynchronous interface) 0001 No boot download Pseudodirect boot from a 32-bit asynchronous interface (bootloader configures the EMIF, and then branches to address 0x080000) 0010 Put DSP into IDLE state...
Page 350 System Operating Details Table 44. External Memory Boot Table for 16-Bit Boot Download (Continued) Word Address (16-Bit Word) Contents Number of elements of the 2nd section to transfer = N2 Most significant word of destination address for the 2nd section. Can be 0, 1, or 2. Least significant word of destination address for the 2nd section.
Page 351 System Operating Details Table 45. External Memory Boot Table for 32-Bit Boot Download (Continued) Word Address (16-bit word) Contents Emifaddr+ 2h Least significant word of destination address for the 1st section. Can be from 0000h to FFFFh. Emifaddr+3h Most significant word of destination address for the 1st section. Can be 0, 1, or 2. Emifaddr+4h 1st word of 1st section to transfer Emifaddr+5h...
Page 352 System Operating Details 9.4.3 Bootloader Description When the MPU releases the DSP subsystem from reset, if pins BOOT_MOD[3:0] = 0000, then the address 0xFFFF00 is mapped into external memory space. If pins BOOT_MOD[3:0] ≠ 0000, then the address 0xFFFF00 maps to internal ROM that has vector to the bootloader at 0xFF800. At this point, the bootloader starts to execute.
Page 353 DSP Subsystem SPRU750A...
Page 354 DSP ramset structure 27 ramset structure 27 cache operation 27 structure 25 DSP subsystem DSP instruction cache configuration 28 architecture overview 15 DSP instruction cache configuration examples 34 clocking and reset 83 DSP instruction cache emulation mode 38 components 17 SPRU750A OMAP5912...
Page 355 50 performance 22 idle registers 52 DSP TIPB control mode register 50 DSP TIPB idle registers 52 DSP/MPU shared peripherals 84 Ramset functional configuration 33 ST3−HOM_P 56 Enable and disable instruction cache 33 ST3−HOM_R 56 OMAP5912 SPRU750A...
Page 356 OMAP5912 Multimedia Processor Clocks Reference Guide Literature Number: SPRU751A March 2004...
Page 357 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 358 OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
Page 359 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 360 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU751A...
Page 361 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 362 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 363 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 364 ....5.10 Clock Distribution in OMAP5912 ..........
Page 365 Contents 5.14 OMAP5912 Output Clocks ........... .
Page 366 Figures OMAP5912 Clocks .............
Page 367 ............. . OMAP5912...
Page 368: Overview
This document describes the clocking mechanisms of the OMAP5912 multimedia processor. Overview In OMAP5912, various clocks are created from special components such as the digital phase locked loop (DPLL) and the analog phase-locked loop (APLL). The DPLL converts the input clock (12 MHz–20 MHz) to a high-frequency clock (200 MHz), which is then distributed within OMAP 3.2 gigacell and...
Page 369: Omap5912 Integration
Overview Figure 1. OMAP5912 Clocks External 32 kHz EXT_CLK External system clock 32-kHz Osc 12-MHz Osc RESPWRON Resets, clocks, clk_32-kHz ON_OFF clock requests RESPWRON_CORE Power split ULPD MPURESET Clocks ULPD_PLL_CLKIN Peripheral ULPD_PLL_CLK Resets configuration APLL Resets, clocks, wakeup interrupt OMAP3.2 gigacell...
Page 370: 96-Mhz Apll
Overview Table 1. LDO Control and Observability LDO Mode Signal Register Bit Description Notes LDO in power-down PWRDWN CONF_LDO_PWRDN_CNTRL_R OMAP5912 configuration mode LDO in sleep mode SLEEP SOFT_LDO_SLEEP ULPD register file LDO stable STEADY LDO_STEADY ULPD register file 1.1.2 96-MHz APLL The APLL is enabled whenever a clock request for a 48-MHz clock is active.
Page 371: Omap3.2 Dpll
APLL has locked. The internally generated 48-MHz clock or an external 48-MHz clock are selected via the TEST_DBG_CTRL_0 bit in the OMAP5912 configuration. If the TEST_DBG_CTRL_0 bit is set to 1, GPIO_14 becomes the source of the 48 MHz for the device.
Page 372 V is lower than 200 mV. Note: OMAP5912 supports only the above application modes. Although other ap- plication modes are possible because of the generic nature of APLL, they are not included in the ULPD architecture.
Page 373 Analog Phase-Locked Loop Figure 2. APLL Block Diagram SEL2 PWRDN VCTL CLKIN Loop Charge filter pump Lock detection LOCK Prescaler ratio: 5, 6, 7 or 8 CLKOUT SEL[0:1] Fractional accumulatior SYNC MISR TEST LS: Level shifter LSn: Natural level shifter or two successive buffers tied to different supply domains.
Page 374: Application Guidelines
Analog Phase-Locked Loop Application Guidelines Adhere to the following guidelines to get the best performance from the cell. Fast Lockup A fast lockup follows this control sequence (see Figure 3): 1) PWRDN must be set to 0 any time the APLL must be used. 2) PWRDN must stay at low for a minimum time.
Page 375: Bmode Switching
OMAP3.2 DPLL BMode Switching The fast lockup scheme changes the APLL operation mode. The selection bits must not be changed during normal operation. If the above condition is not met, be aware that: Digital state machines have been designed in such a way to avoid any deadlock condition, but any switching different from the above can lead to unpredictable long transients that differ considerably from case to case.
Page 376: Features
OMAP3.2 DPLL match the on-chip clock to a system clock so that the integrity of the data transfer from one clock to the other is maintained irrespective of the clock skew and timing variations over different process, voltage, and temperature conditions.
Page 377 OMAP3.2 DPLL Table 5. Control Register Base Address = 0xFFFE CF00, Offset = 0x00 Name Function Reset LS_DISABLE Level shifter disable: 0: Level shifter in transparent mode; all signals between wrapper and DPLL core connected. 1: Level shifter in isolated mode; wrapper and DPLL core disconnected.
Page 378 OMAP3.2 DPLL Table 5. Control Register (Continued) Base Address = 0xFFFE CF00, Offset = 0x00 Name Function Reset 11:7 PLL_MULT (4:0) DPLL multiple value: 00000: CLKOUT = CLKREF * 1 00001: CLKOUT = CLKREF * 1 00010: CLKOUT = CLKREF * 2 00011: CLKOUT = CLKREF * 3 11111: CLKOUT = CLKREF * 31 PLL_DEV (1:0)
Page 379 OMAP3.2 DPLL Table 5. Control Register (Continued) Base Address = 0xFFFE CF00, Offset = 0x00 Name Function Reset BREAKLN Indicates break: 0: DPLL has broken lock for some reason. 1: Lock condition has been restored or write to control register has occurred. LOCK Indicates lock status: 0: DPLL in bypass mode and CLKOUT contains...
Page 380 OMAP3.2 DPLL Figure 4. DPLL Î Î Î Î Î Î CLKREF Î Î Î DPLL core (subchip) Î Î Î Î Î Î Î Î Î Subchip control Î Î Î Î Î Î Level shifter area Î Î Î Î...
Page 381 OMAP3.2 DPLL For PLL_MULT = 0 or 1, the clkout is not synthesized. Hence, the output -clock duty cycle (clkout) is directly dependent on the input-clock duty cycle (clkref). The lock times depend on the values of PLL_MULT and PLL_DIV and the clkout frequency as given below : Lock time in number of clkref cycles: # clkref clocks=4N(11D+28)
Page 382 OMAP3.2 DPLL Figure 5. Operational Flow Reset PLL Not enabled Load new control register value mode = BYPASS Control PLL enabled register write Control register write Locking Mode = BYPASS mode = BYPASS IDLE PLL locked enabled IDLE Lost Control disabled register LOCK...
Page 383: Low-Dropout Voltage Regulator
Low-Dropout Voltage Regulator Table 6. Clock Timings Description Value Unit CLKREF duty cycle From 40 to 60 Min CLKREF frequency Max CLKREF frequency Max CLKOUT frequency Low-Dropout Voltage Regulator LDO005 is a linear voltage regulator that supplies the OMAP3.2 DPLL macro. This LDO uses peripheral supply input voltage to make the DPLL a quiet power supply.
Page 384 Low-Dropout Voltage Regulator Figure 6. LDO005 VDDS PWRDN VOUT LDO005 STEADY SLEEP VSSS VSSS Table 7. LDO005 Pins Name Type Description Power signal ring Positive core power supply VDDS Power signal ring Positive periphery power supply input voltage VOUT Power signal/pad side Core Positive output voltage connected to DPLL power supply and bond pad...
Page 385 Low-Dropout Voltage Regulator Figure 7. LDO005 Block VDD domain Steady COMP VDDS SETZ 1.7-3.6 V Peripheral PWRDN Sleep PWRDN2 VOUT to DPLLs and VDDS domain bond pad (1.2V − 1.6V) The reference is a circuit that delivers voltage and current to the regulator and steady comparator.
Page 386: Timing Diagrams
Low-Dropout Voltage Regulator Table 8. Mode Selection PWRDN SLEEP Mode Application, active Don’t care Powerdown Sleep Timing Diagrams Figure 8. VDD_CORE Ramps First VDD_IO VDD_CORE PWRDN SLEEP RESPWRON STEADY LDO is ON LDO is OFF SPRU751A Clocks...
Page 387: Omap5912 Clock Architecture
(ULPD), which is responsible for power-mode transitions and clock management. System clock frequencies are 12, 13, or 19.2 MHz. OMAP5912 is also clocked by a 32-kHz clock used by the ULPD finite state machine (FSM) and for specific clocking needs such as the real−time counter (RTC) or the general-purpose timers.
Page 388: Reset Modes And Clocking Options
SYS_CLK_IN support w/external clock source? External System Clock with Reset Mode 0 The OMAP5912 system clock can be driven at 12MHz, 13MHz, or 19.2MHz. For an external system clock, the following hardware connections are used (see Figure 10). Figure 10 applies to reset mode 0 only.
Page 389: External 32-Khz Clock With Reset Mode 0
External 32-kHz Clock with Reset Mode 0 The OMAP5912 32-kHz clock can be driven by an external squarewave clock. See Figure 10 for the hardware connections of the external 32-kHz clock. This figure applies to reset mode 0 only.
Page 390: Using The Internal Oscillator For The System Clock With Reset Mode 0
1 will also disable the oscillator circuit). Using the Internal Oscillator for a 32-kHz Clock with Reset Mode 0 The OMAP5912 32-kHz clock can be driven by an internal oscillator and crystal. See Figure 11 for the hardware connections of the external 32-kHz clock.
Page 391: External System Clock With Reset Mode 1
32-kHz oscillator circuit. External System Clock with Reset Mode 1 The OMAP5912 system clock is driven at 19.2 MHz only in reset mode 1. For an external system clock, the following hardware connections are used (see Figure 12).
Page 392: External 32-Khz Clock With Reset Mode 1
External 32-kHz Clock with Reset Mode 1 The OMAP5912 32-kHz clock can be driven by an external clock. See Figure 12 for the hardware connections of the external 32-kHz clock. This figure applies to reset mode 1 only.
Page 393: Using The Internal Oscillator For The System Clock With Reset Mode 1
Notes: 1) Ball Y13 MUST NOT be connected to board ground (VSS). Please see the OMAP5912 Data Manual (SWPS012) for more details on clock connections. See Figure 14 for a summary of the 32-kHz and system clock internal connections.
Page 394: Clock Distribution In Omap5912
Communication is ensured through LOW_POWER outputs from OMAP5912. Figure 15 provides an overview of ULPD clocking. See OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) for further details on the ULPD.
Page 395 OMAP5912 Clock Architecture Table 10. ULPD Input Clocks Input Name Description Origin ARMXOR_CK MPU peripheral clock OMAP3.2 EXT_48M External 48-MHz clock GPIO_14 ULPD_PLL_CLK Clock from 96-MHz PLL APLL 32-kHz Clock 32-kHz clock (either from 32-kHz oscillator or from external 32-kHz clock input) System Clock 12- to19.2-MHz system clock (12−19.2-MHz oscillator or from...
Page 396 OMAP5912 Clock Architecture Figure 15. ULPD Clocking Overview ULPD CAM.CLKOUT System clock 48 MHz (UART1) 48 MHz (UART2) 48 MHz (UART3) 48 MHz (USB OTG) 12/13-19.2 MHz ARMXOR_CK (to APLL) Clock (Camera I/F) EXT_48M MCLK ULPD_PLL_CLK BCLK 32-kHz clock SYS_CLK_OUT...
Page 397: Omap 3.2 Clocks
OMAP5912 Clock Architecture 5.11 OMAP 3.2 Clocks Table 11 describes the OMAP3.2 gigacell clocking distributed to external peripherals. Table 11. OMAP 3.2 Clocks Clock Name Description CK_REF System clock, input to DPPL1 CK_DPLL1OUT Clock from DPPL1, same as MPU clock...
Page 398 OMAP5912 Clock Architecture Figure 16. OMAP 3.2 Clock Generation CK_GEN1 CK_DPLL1OUT IDLE condition + SW Clock Enable: ARM_IDLECT2[EN_CKOUT_ARM(11)] ARM_CK Frequency divider ARM_CK IDLE condition ARM_CKCTL[ARMDIV(5:4)] ARMCPU_CK ARMPER_CK Frequency divider IDLE condition + SW Clock Enable: ARM_CKCTL[PERDIV(1:0)] ARM_IDLECT2[EN_PERCK(2)] external CK_REF peripherals...
Page 399: Clock Distribution To Peripherals
OMAP5912 Clock Architecture 5.12 Clock Distribution to Peripherals Figure 17 shows OMAP5912 peripherals (outside of the MPU subsystem) and associated clock distribution. Clocks SPRU751A...
Page 400 OMAP5912 Clock Architecture Figure 17. Peripheral Clock Distribution 48 MHz USB OTG* (from ULPD) MOD_CONF_CTRL_0[30] System clock (from ULPD) 48 MHz (from ULPD) MMC−SDIO(1)* 48 MHz UART2* 32 kHz (from ULPD) static loop (from ULPD) System clock (from ULPD) MCSI1.CLK...
Page 401: Peripheral Module Clocking
OMAP5912 Clock Architecture 5.13 Peripheral Module Clocking Figure 18 shows the peripheral clocking. Figure 18. Peripheral Clocking Internal Peripheral system External External Internal interface interface clock clock (bus transactions) (receive/transmit) Receive/transmit Bus interface transactions Internal External interface interface domain Functional domain...
Page 402 OMAP5912 Clock Architecture Table 12. Peripheral Clocks and Associated Controls (Continued) Peripheral Name Functional Clock Interface Clock MOD_CONF_ MOD_CONF_ Domain CTRL_0 CTRL_1 (OMAP5912 Con- (OMAP5912 figuration) Configuration) Boot ROM TC_CK Not applicable Secure RAM TC_CK Not applicable TC1_CK ARMPER_CK Secure watchdog...
Page 403 OMAP5912 Clock Architecture Table 12. Peripheral Clocks and Associated Controls (Continued) Peripheral Name Functional Clock Interface Clock MOD_CONF_ MOD_CONF_ Domain CTRL_0 CTRL_1 (OMAP5912 Con- (OMAP5912 figuration) Configuration) General-purpose 32 kHz from ULPD ARMPER_CK CONF_MODE_ timer 5 EXTCLK CLK_SEL[9:8] ARMXOR_CLK General-purpose...
Page 404 OMAP5912 Clock Architecture Table 12. Peripheral Clocks and Associated Controls (Continued) Peripheral Name Functional Clock Interface Clock MOD_CONF_ MOD_CONF_ Domain CTRL_0 CTRL_1 (OMAP5912 Con- (OMAP5912 figuration) Configuration) General-purpose 32 kHz from ULPD CONF_MODE_ timer 8 EXTCLK CLK_SEL[15:14] ARMXOR_CLK 32 kHz from ULPD...
Page 405 OMAP5912 Clock Architecture Table 12. Peripheral Clocks and Associated Controls (Continued) Peripheral Name Functional Clock Interface Clock MOD_CONF_ MOD_CONF_ Domain CTRL_0 CTRL_1 (OMAP5912 Con- (OMAP5912 figuration) Configuration) MMC/SDIO1 48 MHz from ULPD ARMPER_CK ARMXOR_CK (gated Not applicable in ULPD) MPUIO...
Page 406: Clock Gating In Ulpd
Wake-up requests can be hardware or software and can be disabled by software. For software requests, disables, and associated clocks, see Table 13. In addition, some software requests can be set up in the OMAP5912 configuration module. Table 13. Hardware Requests Hardware Request...
Page 407 USB device is not used, is unconnected, or is put in suspend). Table 14 summarizes software clock requests that are mapped in the OMAP5912 configuration module and in the ULPD module and that differ from the generic ULPD software requests in SOFT_REQ_REG. Table 14. Software Requests...
Page 408 OMAP5912 Clock Architecture Table 15. Active Clocks in Big Sleep Mode Module/ Clock Description Active Request Notes OMAP5912 I/O Destination BCLK System clock or BCLKREQ (see note 5) When 48MHz clock is selected 48-MHz clock from SDW_CLK_DIV_CTRL_ APLL SEL[7:2] further divides BCLK.
Page 409 OMAP5912 Clock Architecture Table 15. Active Clocks in Big Sleep Mode (Continued) Module/ Clock Description Active Request Notes OMAP5912 I/O Destination USB OTG EXT_48M USB_DPLL_MCLK_REQ 48 MHz from ULPD CONF_MOD_USB_HOST_ HHC_UHOST_EN_R SOFT_REQ_REG[8] MMC/SDIO1 EXT_48M MOD_CONF_CTRL_0[23] SOFT_REQ_REG[12] 48 MHz from ULPD...
Page 410 5.14 OMAP5912 Output Clocks There are four OMAP5912 output clocks that can be used to clock external ICs. All of these output clocks are on pins that are multiplexed with other functions. Therefore, the appropriate pin multiplexing must be programmed by software (e.g.
Page 411 OMAP5912 Clock Architecture MCLK, software also ULPD CLOCK_CTRL_REG.COM_MCLK_INV to select the inactive level of MCLK. A software request for MCLK is also available. Depending on the software request used, MCLK can be: 48MHz coming from the ULPD APLL (legacy support)
Page 412 OMAP5912 Clock Architecture Set ULPD COM_CLK_CTRL_DIV_SEL.COM_RATIO_SEL to the desired ratio. Set the COM_SYSCLK_PLLCLK_SEL bit to 0 in the ULPD COM_CLK_CTRL_DIV_SEL register. COM_ULPD_PLL_CLK_REQ ULPD COM_CLK_CTRL_DIV_SEL register. Consequently, the 48MHz clock divided by the programmed ratio will be available on MCLK. Use COM_ULPD_PLL_CLK_REQ to disable or re-enable MCLK clock.
Page 413 OMAP5912 Clock Architecture Set the SOFT_SDW_REQ bit to 1 in the ULPD SOFT_REQ_REG register. Consequently, the system clock is available on BCLK. Use SOFT_SDW_REQ to disable or reenable BCLK (regardless of the BCLKREQ pin). When the system clock is output on BCLK, the software can also use the ULPD CLOCK_CTRL_REG.SDW_MCLK_INV to select the inactive level of BCLK.
Page 414 OMAP5912 Clock Architecture B15 acts as SYS_CLK_OUT. The procedure to enable SYS_CLK_OUT using a hardware request is: Set the TI_RESERVED_EN bit to 1 in the ULPD CLOCK_CTRL_REG register. DIS_COM_MCLK_REQ ULPD SOFT_DISABLE_REQ_REG register. Consequently, the system clock is available on ball B15. Modifying the SOFT_DIS_COM_MCLK_REQ or TI_RESERVED_EN bits masks out MCLKREQ and deactivates MCLK clock.
Page 415 Converts 12-MHz to 19.2-MHz clock to 48-MHz clock APLL active whenever a request for 48-MHz clock is set to 1. Table 17 details the OMAP5912 sleep modes as they relate to power dissipation and clocks. Table 17. Mode Description Modes...
Page 416 OMAP5912 clock overview 13 clock distribution to peripherals 44 OMAP5912 clocks low−power modes 59 APLL 16 Clock distribution in OMAP5912, clock and reset OMAP3.2 DPLL 20 architecture 39 OMAP3.2 low dropout voltage regulator 28 Clock distribution to peripherals, clock and reset...
Page 417 OMAP5912 SPRU751A...
Page 418 OMAP5912 Multimedia Processor Initialization Reference Guide Literature Number: SPRU752B October 2004...
Page 419 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 420 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments Documentation that describes the OMAP5912 device, related peripherals, and other technical collateral, is available in the OMAP5912 Product Folder on TI’s website: www.ti.com/omap5912. Trademarks OMAP and the OMAP symbol are trademarks of Texas Instruments.
Page 421 ........OMAP5912/5910 Software and Hardware Compatibility .
Page 422 ......Test Debug Control 0 Register (TEST_DBG_CTRL_0) ......SPRU752B OMAP5912...
Page 423 ........OMAP5912 Configuration Control Register (CONF_5912_CTRL) .
Page 424: Reset Architecture
Initialization This document describes the reset architecture, the configuration, and the initialization of the OMAP5912 multimedia processor. All references to device package ball number in this document refer to the ZZG package. Please see the data manual (SPRS231) for complete pinout information for both the ZZG and ZDY packages.
Page 425: Resets
Reset Architecture Resets This processor has up to three external reset pins depending on the reset mode. PWRON_RESET is the cold reset for the entire chip. is the MPU_RST MPU subsystem reset (this pin has special setup requirements in reset mode 1).
Page 426: Rtc Split Power
Reset Architecture 1.2.1 RTC Split Power RTC split power is available with reset mode 0 only. The RTC power domain is split from the core power domain so that the real-time clock and its associated oscillator can continue to run off of the battery while the MPU subsystem is completely powered off.
Page 427 MPU TIPB bridge and peripherals Shared peripherals In RESET_MODE 1 sole reset source GLOB_SWRST (bit1) for Class1 modules: boot ROM, ULPD, MPU clock reset status OMAP5912 conf, sync counter. Sole register (ARM_SYSST) reset source for RTC. External Low on Reset LCD controller...
Page 428 Reset Architecture Table 3. Global Resets (Continued) Reset Source Event Reset Description Status Bit Production eFuse Warm reset permanently asserted by EXT_RST (bit 4) MPU eFuse programmed ULPD clock reset status value to BAD register (ARM_SYSST) GLOB_SWRST (bit 1) MPU clock reset status register (ARM_SYSST) Warm 32-kHz WD...
Page 429 Reset Architecture Table 3. Global Resets (Continued) Reset Source Event Reset Description Status Bit Warm Global SW_RST Reset LCD controller GLOB_SWRST (bit 1) reset system reset (bit 3) in System DMA MPU clock reset status (software) ARM_ MPU port interface register (ARM_SYSST) (continued) RSTCT1 is...
Page 430: Omap 3.2 Resets
Reset Architecture Table 3. Global Resets (Continued) Reset Source Event Reset Description Status Bit DSP core Software DSP_EN Reset the DSP, excluding the software (bit 1) in configuration settings (config registers reset ARM_RSTC1 of EMIF internal to DSP and the MPUI is cleared to control logic internal to DSP).
Page 431 Reset Architecture Table 4. OMAP 3.2 Resets (Continued) Components Type Cold Warm DSP WD DSP Core DSP Software Resets Resets Reset Software Software Reset Reset Reset MPU timer 1 MPU timer 2 MPU timer 3 MPU WD timer MPU INTH LCD controller DSP core Only EMIF con-...
Page 432: Peripheral Resets
Reset Architecture Table 4. OMAP 3.2 Resets (Continued) Components Type Cold Warm DSP WD DSP Core DSP Software Resets Resets Reset Software Software Reset Reset Reset TIPB bridge EMIFF Self-Ref ‡ EMIFS L3/OCP/T1 (target) L3/OCP/T2 (target) L3/OCP(initiator) † DSP-MMU SW reset bit in CNTL_REG of DSP-MMU module must also be set correctly for DSP-MMU to be reset. ‡...
Page 433 Reset Architecture Figure 1. Reset Distribution to Peripherals Class 3 Modules DSP L2 INTH Boot ROM MCSI2 Sync counter MCSI1 McBSP3 OMAP5912 Class 1 Modules conf McBSP1 OMAP3.2 CHIP_RESET_IN DSPPER_RST Warm Resets Warm Reset ULPD_RESET Cold Reset ARMPER_RST 32K WD...
Page 434: Peripheral Reset Table
Reset Architecture 1.2.5 Peripheral Reset Table Table 5 shows the various reset sources for each peripheral. Many of the OMAP peripherals (external to the MPU subsystem) have module wrappers or switches that facilitate conversion between different bus protocols (wrapper) or control DSP and MPU access to that peripheral (switch). For example, the UART1 peripheral is on the TIPB, but the internal bus protocol for UART1 is OCP.
Page 435 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 2 Modules µWire Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 HDQ/1-Wire Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Camera I/F Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm...
Page 436 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 2 Modules (Continued) CompactFlash controller Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm OCP SWRST OCP wrapper Cold reset/Warm reset/ARM_WD/SWRS reset/ARM_WD/SWRS T2/SWRST1 T2/SWRST1 GPIO1 Cold reset/Warm...
Page 437 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 2 Modules (Continued) UART2 Cold reset/Warm OCP SWRST Static switch Cold reset/Warm reset/ARM_WD/SWRS reset/ARM_WD/DSP_ T2/SWRST1 WD/SWRST3/SWRST 2/SWRST1 UART3 Cold reset/Warm OCP SWRST Static switch Cold reset/Warm...
Page 438 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 2 Modules (Continued) General-purpose timer 3 Cold reset/Warm OCP SWRST Static switch Cold reset/Warm reset/ARM_WD/SWRS reset/ARM_WD/DSP_ T2/SWRST1 WD/SWRST3/SWRST 2/SWRST1 General-purpose timer 4 Cold reset/Warm OCP SWRST Static switch...
Page 439 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 2 Modules (Continued) MPU level 2 interrupt Cold reset/Warm OCP SWRST OCP wrapper Cold reset/Warm handler reset/ARM_WD/SWRS reset/ARM_WD/SWRS T2/SWRST1 T2/SWRST1 MMC/SDIO1 Cold reset/Warm OCP SWRST...
Page 440 Reset Architecture Table 5. Reset Sources for Peripherals (Continued) Peripheral Name HW Reset SW Reset Wrapper/ Wrapper/Switch Reset Switch Class 3 Modules DSP Interrupt handler 2.1 Cold reset/Warm OCP SWRST OCP wrapper Cold reset/Warm reset/ARM_WD/SWRS reset/ARM_WD/ T3/SWRST2 DSP_WD/SWRST3/S WRST2 McBSP1 Cold reset/Warm Partial OCP wrapper...
Page 441: Input/Output
Reset Architecture Input/Output Table 6 lists all I/Os that are related to the clock and reset module. Table 6. Input/Output for Clock and Reset Pin Name Dir. Ball Descrip- Default Mode in Default Mode in Notes tion RESET_MODE 0 RESET_MODE 1 RESET_ Reset_ Sampled at...
Page 442 Reset Architecture Table 6. Input/Output for Clock and Reset (Continued) Pin Name Dir. Ball Descrip- Default Mode in Default Mode in Notes tion RESET_MODE 0 RESET_MODE 1 SYS_CLK_IN 12-MHz to Must be tied low if 19.2-MHz on-chip oscillator is clock in used.
Page 443: Configuration
Configuration Reset Architecture / Configuration Table 6. Input/Output for Clock and Reset (Continued) Pin Name Dir. Ball Descrip- Default Mode in Default Mode in Notes tion RESET_MODE 0 RESET_MODE 1 USB.CLK0 Derived 96-MHz APLL from APLL clock divided by 16 clock SYS_CLK_ System...
Page 444: Configuration Register Capabilities
DSP DMA request multiplex registers FUNC_MUX_DSP_DMA(A-D) Table 7. Configuration Registers (Continued) MPU DMA request multiplex registers FUNC_MUX_ARM_DMA(A-G) Status register CONF_STATUS LDO bypassing control register LDO_PWRDN_CTRL USB Transceivers control register USB_TRANSCEIVER_CTRL Reset control register RESET_CONTROL OMAP5912 control register CONF_5912_CTRL SPRU752B Initialization...
Page 445: Pin Multiplexing And Pullups/Pulldowns
Configuration Pin Multiplexing and Pullups/Pulldowns Each pin that has a multiplexing function is assigned a 3-bit field in the register set FUNC_MUX_CTRL(3-12), thus creating up to eight possible multiplexing options per pin. At reset (PWRON_RESET is low), the multiplexing of each pin is asynchronously forced by the RESET_MODE pin, regardless of the value written to the FUNC_MUX_CTRL(3-12) registers.
Page 446: Multiplexing Exceptions With Usb Host Client
Configuration Even though all FUNC_MUX_CTRL registers reset to 0x0000, reset mode 1 causes some pins to default to a pin mux mode other than 000. To maintain the same mux mode on such pins, the appropriate FUNC_MUX_CTRL register must be programmed prior to writing 0x0000EAEF to COMP_MODE_CTRL_0.
Page 447: Procedure For Setting The Pin Multiplexing
Configuration 2.2.4 Procedure for Setting the Pin Multiplexing value RESET_MODE read CONF_RESET_MODE_STAT_R bit field of the CONF_STATUS register: All mux mode registers (FUNC_MUX_CTRL(3-12)) reset to 000, regardless of RESET_MODE input pin status. All pullup/pulldown enable registers (PULL_DWN_CTRL(0-4)) reset to 0, regardless of the RESET_MODE input pin status. However, the actual states of the pulldowns does not depend on the values in the PULL_DWN_CTRL(0−4) registers until programming 0x0000EAEF in the COMP_MODE_CTRL_0 register.
Page 448: Parallel Observability During Functional Mode
Configuration Table 8. Functional Multiplexing Modes FUNC_MUX_CTRL Corresponding Multiplexing Mode for 3-Bit Value Pin Configuration Default configuration/functional multiplexing 0 Functional pin multiplexing mode 1 Functional pin multiplexing mode 2 Functional pin multiplexing mode 3 Functional pin multiplexing mode 4 Functional pin multiplexing mode 5 Functional pin multiplexing mode 6 Functional pin multiplexing mode 7 For a given interface, the values of the FUNC_MUX_CTRL bits may vary from...
Page 449 Configuration Table 9. Parallel Observability Multiplexing Signals CONF_OBS_MUX_SEL_R Value Ball Reserved ARMXOR_CK LDO_SLEEP ULPD_DPLL48M Reserved DSPXOR_CK LDO_STEADY ULPD_ USBW2FCCLK12M Ball USB RXD ARMPER_CK LDO_PWRDN OMAP3.2 functional clock USB RXDP DSPPER_CK UART3 functional Reserved clock USB RXDM Reserved UART2 functional Reserved clock Reserved Reserved...
Page 450: Omap5912/5910 Software And Hardware Compatibility
12-MHz oscillator Reserved PWRDN OMAP5912/5910 Software and Hardware Compatibility The device resets based on the RESET_MODE pin are forced either to the functional multiplexing mode 000, with the appropriate pullups or pulldowns configured and enabled to preserve the OMAP5910 pinout reset condition, or to the new reset mode 1.
Page 451 VOLTAGE_CTRL_0 TEST_DBG_CTRL_0 MOD_CONF_CTRL_0 For OMAP5912, all I/O power supplies have a low- and a high-voltage mode VS. In OMAP5910, only the EMIFS, EMIFF, and communication processor interface have dual voltage interfaces. For OMAP5912 at reset, the voltage mode has changed to default to low-voltage mode, whereas in OMAP5910 it is high-voltage mode.
Page 452: Configuration Registers
Configuration Table 10 lists the configuration registers. Table 11 through Table 52 describe the register bits. Configuration Registers Table 10. Configuration Registers Base Address = 0xFFFE 1000 Name Description Offset FUNC_MUX_CTRL_0 Functional multiplexing control 0 0x00 FUNC_MUX_CTRL_1 Functional multiplexing control 1 0x04 FUNC_MUX_CTRL_2 Functional multiplexing control 2...
Page 453 Configuration Table 10. Configuration Registers (Continued) Base Address = 0xFFFE 1000 Name Description Offset USB_TRANSCEIVER_CTRL USB transceiver control 0x64 LDO_PWRDN_CBTRK LDO powerdown control 0x68 TEST_DBG_CTRL_0 Test debug control 0 0x70 MOD_CONF_CTRL_0 Module configuration control 0 0x80 FUNC_MUX_CTRL_E Functional multiplexing control 0x90 FUNC_MUX_CTRL_F Functional multiplexing control...
Page 454 Configuration status 0x130 RESET_CONTROL Reset control register 0x140 CONF_5912_CTRL OMAP5912 configuration control 0x150 Register descriptions for DMA functional mux registers are in the Multimedia Processor Direct Memory Access (DMA) Note: Support Reference Guide (SPRU755). Table 11. Functional Multiplexing Control O Register (FUNC_MUX_CTRL_0)
Page 455 Configuration Table 11. Functional Multiplexing Control O Register (FUNC_MUX_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x00 Name Function Reset OBS_288_1 Configures observation mode multiplexing on the camera interface (See Section 2.3). 0: Observation mode is disabled and camera interface is in functional mode.
Page 456 Configuration Table 11. Functional Multiplexing Control O Register (FUNC_MUX_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x00 Name Function Reset NRESET_ENABLE Allows AND gating of outputs with the OMAP CHIP_NRESET_OUT 0: Disabled 1: Enabled PWR_MASK_IN This register enables the Inhibit2 function. Depending on the status of GPIO(9) and ARMIO(3), subject inputs are gated to low internally when this function is enabled.
Page 457 Configuration Table 11. Functional Multiplexing Control O Register (FUNC_MUX_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x00 Name Function Reset BVLZ_MASK_IN This register enables the Inhibit1 function. Depending on the status of BVLZ input pin, subject inputs are gated to low internally when this function is enabled.
Page 458 Configuration This register primarily controls legacy functional multiplexing. Many mux modes have been removed and made more generic. When a function has been removed, it is noted in the register description. Table 12. Functional Multiplexing Control 1 Register (FUNC_MUX_CTRL_1) Base Address = 0xFFFE 1000, Offset Address = 0x04 Name Function Reset...
Page 459 Configuration Table 13. Functional Multiplexing Control 2 Register (FUNC_MUX_CTRL_2) Base Address = 0xFFFE 1000, Offset Address = 0x08 Name Function Reset 12:7 CONF_DSP_INT_SEL_R Select the DSP level 2 interrupts to be 0x00 observed. The pin configuration for each observation mode is specified (See Section 2.3). Observing interrupts is done after multiplexers that select between level and edge activity.
Page 460 Configuration Table 15. Functional Multiplexing Control 3 Register (FUNC_MUX_CTRL_3) Base Address = 0xFFFE 1000, Offset Address = 0x10 Name Function Reset 31:30 RESERVED Reserved for future expansion. 29:27 CONF_F19 Controls the multiplexing on F19. Formerly, CONF_KBR_1_R. 26:24 CONF_H14 Controls the multiplexing on H14. Formerly, CONF_KBR_2_R. 23:21 CONF_E20 Controls the multiplexing on E20.
Page 461 Configuration Table 16. Functional Multiplexing Control 4 Register (FUNC_MUX_CTRL_4) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x14 Name Function Reset 14:12 CONF_H15 Controls multiplexing on H15. Formerly CONF_MCBSP1_SYNC_R. 11:9 CONF_G21 Controls multiplexing on G21. Formerly CONF_MCBSP1_BCLK_R. CONF_G20 Controls multiplexing on G20. Formerly CONF_MCBSP1_CLKS_R.
Page 462 Configuration This register controls functional multiplexing. COMP_MODE_CTRL_0 must be programmed to 0xEAEFh for this register to control functional multiplexing. See Table 8 for bit field values. Table 18. Functional Multiplexing Control 6 Register (FUNC_MUX_CTRL_6) Base Address = 0xFFFE 1000, Offset Address = 0x1C Name Function Reset...
Page 463 Configuration Table 19. Functional Multiplexing Control 7 Register (FUNC_MUX_CTRL_7) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x20 Name Function Reset 17:15 CONF_T19 Controls multiplexing on T19. Formerly, CONF_ARMIO_4_R. 14:12 CONF_T20 Controls multiplexing on T20. Formerly, CONF_ARMIO_5_R. 11:9 CONF_R18 Controls multiplexing on R18.
Page 464 Configuration This register controls functional multiplexing. COMP_MODE_CTRL_0 must be programmed to 0xEAEFh for this register to control functional multiplexing. See Table 8 for bit field values. Table 21. Functional Multiplexing Control 9 Register (FUNC_MUX_CTRL_9) Base Address = 0xFFFE 1000, Offset Address = 0x28 Name Function Reset...
Page 465 Configuration Table 22. Functional Multiplexing Control A Register (FUNC_MUX_CTRL_A) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x2C Name Function Reset 26:24 CONF_V10 Controls multiplexing on V10. Formerly CONF_MMC_DAT1_R. 23:21 CONF_V11 Controls multiplexing on V11. Formerly CONF_MMC_CLK_R. 20:18 CONF_W10 Controls multiplexing on W10.
Page 466 Configuration Table 23. Functional Multiplexing Control B Register (FUNC_MUX_CTRL_B) Base Address = 0xFFFE 1000, Offset Address = 0x30 Name Function Reset CONF_Y10 Controls multiplexing on Y10. Formerly CONF_MCSI2_CLK_R. CONF_R11 Controls multiplexing on R11. Formerly CONF_MMC_DAT0_R. This register controls functional multiplexing. COMP_MODE_CTRL_0 must be programmed to 0xEAEFh for this register to control functional multiplexing.
Page 467 Configuration Table 25. Functional Multiplexing Control D Register (FUNC_MUX_CTRL_D) Base Address = 0xFFFE 1000, Offset Address = 0x38 Name Function Reset 31:30 RESERVED Reserved for future expansion. 29:27 CONF_G13 Controls multiplexing on G13. Formerly CONF_LCD_PIXEL_12_R. 26:24 CONF_A17 Controls multiplexing on A17. Formerly CONF_LCD_PIXEL_13_R. 23:21 CONF_C16 Controls multiplexing on C16.
Page 468 Configuration Table 26. Pulldown Control 0 Register (PULL_DWN_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x40 Name Function Reset CONF_PDEN_K18 Enables (0) pullup or pulldown on K18. CONF_PDEN_J14 Enables (0) pullup or pulldown on J14. CONF_PDEN_J19 Enables (0) pullup or pulldown on J19. CONF_PDEN_J18 Enables (0) pullup or pulldown on J18.
Page 469 Configuration pinout documentation in SPRS231 must be consulted to determine whether a pullup or pulldown exists on the specified I/O. COMP_MODE_CTRL_0 must be programmed to 0xEAEF, so that the programming is taken into account in the corresponding tactical cell. Table 27. Pulldown Control 1 Register (PULL_DWN_CTRL_1) Base Address = 0xFFFE 1000, Offset Address = 0x44 Name Function...
Page 470 Configuration Table 27. Pulldown Control 1 Register (PULL_DWN_CTRL_1) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x44 Name Function Reset CONF_PDEN_M14 Enables (0) pullup or pulldown on M14. CONF_PDEN_P18 Enables (0) pullup or pulldown on P18. CONF_PDEN_P20 Enables (0) pullup or pulldown on P20. CONF_PDEN_P19 Enables (0) pullup or pulldown on P19.
Page 471 Configuration This register controls the enable or disable of the combined pullup/pulldown cell (0 = enabled, 1 = disabled). When enabling the cell, the user must set the corresponding bit in PU_PD_SEL_1 to select either a pullup or a pulldown. The pinout documentation in SPRS231 must be consulted to determine whether a pullup or pulldown exists on the specified I/O.
Page 472 Configuration Table 28. Pulldown Control 2 Register (PULL_DWN_CTRL_2) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x48 Name Function Reset CONF_PDEN_P13 Enables (0) pullup or pulldown on P13. CONF_PDEN_R13 Enables (0) pullup or pulldown on R13. CONF_PDEN_V15 Enables (0) pullup or pulldown on V15. CONF_PDEN_P14 Enables (0) pullup or pulldown on P14.
Page 473 Configuration Table 29. Pulldown Control 3 Register (PULL_DWN_CTRL_3) Base Address = 0xFFFE 1000, Offset Address = 0x4C Name Function Reset CONF_PDEN_W2 Enables (0) pullup or pulldown on W2. CONF_PDEN_V4 Enables (0) pullup or pulldown on V4. CONF_PDEN_Y1 Enables (0) pullup or pulldown on Y1. CONF_PDEN_Y17 Enables (0) pullup or pulldown on Y17.
Page 474 Configuration Table 29. Pulldown Control 3 Register (PULL_DWN_CTRL_3) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x4C Name Function Reset CONF_PDEN_M4 Enables (0) pullup or pulldown on M4. CONF_PDEN_W4 Enables (0) pullup or pulldown on W4. CONF_PDEN_Y4 Enables (0) pullup or pulldown on Y4. CONF_PDEN_V6 Enables (0) pullup or pulldown on V6.
Page 475 Configuration Table 30. Gate and Inhibit Control Register (GATE_INH_CTRL_0) Base Address = 0xFFFE 1000, Offset Address = 0x50 Name Function Reset 31:6 CONF_GATE_INH_ Reserved for future expansion. 0x0000000 RESERVED RESERVED1 Reserved for future expansion. RESERVED Reserved for future expansion. CONF_HIGH_IMP3 Controls high impedance on MCSI1.DOUT.
Page 476 Configuration Table 31. Configuration Revision Register (CONF_REV) Base Address = 0xFFFE 1000, Offset Address = 0x58 Name Function Reset 31:8 CONF_REV_RESERVED Reserved for future expansion. 0x000000 CONF_REV_R This 8-bit field indicates the revision number of 0x10 the current module. This value is fixed by hardware.
Page 477 Configuration Table 32. Voltage Control 0 Register (VOLTAGE_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x60 Name Function Reset CONF_VOLTAGE_ This bit controls the drive strength of the VDDSHV9_R DVDD9 voltage domain. The bit controls the low/high voltage mode. The voltage range supported is defined in the SPRS231 document.
Page 478 Configuration Table 32. Voltage Control 0 Register (VOLTAGE_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x60 Name Function Reset CONF_VOLTAGE_ This bit controls the drive strength of the VDDSHV2_R DVDD2 voltage domain. The bit controls the low/high voltage mode. The voltage range supported is defined in the SPRS231 document.
Page 479 Configuration Table 32. Voltage Control 0 Register (VOLTAGE_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x60 Name Function Reset CONF_VOLTAGE_ This bit controls the drive strength of the COMIF_R DVDD3 communication processor interface voltage domain. The bit controls the low/high voltage mode.
Page 480 Configuration Table 33. USB Transceiver Control Register (USB_TRANSCEIVER_CTRL) Base Address = 0xFFFE 1000, Offset Address = 0x64 Name Function Reset 31:9 UNUSED These bits are not implemented. 0x000000 CONF_USB2_UNI_R This bit configures the way USB port 2 interfaces with external USB transceiver. 0: Bidirectional mode USB2.SE0 is a bidirectional I/O, rather than an output only.
Page 481 Configuration Table 33. USB Transceiver Control Register (USB_TRANSCEIVER_CTRL) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x64 Name Function Reset CONF_USB_PORT0_R These bits control the multiplexing on the I/O, which defaults to USB.DP and USB.DM at reset. These 3 bits configure USB port 0 for alternate operation.
Page 482 Configuration This 1-bit register bypasses the LDO. Table 35. Test Debug Control 0 Register (TEST_DBG_CTRL_0) Base Address = 0xFFFE 1000, Offset Address = 0x70 Name Function Reset 31:22 CONF_TEST_DBG_ Reserved for future expansion. 0x0000 RESERVED CONF_RNG_TEST_OSC Ring oscillator divider enable. CONF_RNG_SELECT_ Ring oscillator selection for characterization Active high.
Page 483 Configuration Table 36. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) Base Address = 0xFFFE 1000, Offset Address = 0x80 Name Function Reset CONF_MOD_UART3_CLK This bit determines the 48-MHz clock request _MODE_R for UART3. 0: 48-MHz clock request is inactive. 1: 48-MHz clock request is active. CONF_MOD_UART2_CLK This bit determines the clock source of UART2.
Page 484 Configuration Table 36. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x80 Name Function Reset CONF_MOD_MCBSP3_ This bit determines the method of frame sync CLK_SEL_R wrap-around used on MCBSP3. 0: Wrap-around done in hardware external to the McBSP (3 pins mode).
Page 485 Configuration Table 36. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x80 Name Function Reset CONF_MOD_MMC2_CLK_ This register selects the clock used for the SEL_R MMC/SD2 module: 0: 48-MHz MMC2_DPLL_CLK from the ULPD. 1: ARM_XOR_CLK from OMAP clock module CONF_MOD_COM_MCLK This bit determines whether MCLK of the...
Page 486 Configuration Table 36. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x80 Name Function Reset CONF_MOD_USB_HOST_ Transceiverless link logic (TLL) USB speed HMC_TLL_SPEED_R control. For HMC modes (as defined by HMC_MODE_I and HMC_JTAG_EN_I) where the TLL is used, this bit determines whether the modeling of the device pullup resistor is on the internal D+ or the internal D−...
Page 487 Configuration Table 36. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x80 Name Function Reset CONF_MOD_USB_HOST_ Transceiverless link logic (TLL) USB attach HMC_TLL_ATTACH_R control. For HMC modes (as defined by HMC_MODE_I and HMC_JTAG_EN_I) where the TLL is used, this bit determines whether or not the TLL models its internal representation of USB differential data signals with or without a...
Page 488 Configuration Table 37. Functional Multiplexing Control E Register (FUNC_MUX_CTRL_E) Base Address = 0xFFFE 1000, Offset Address = 0x90 Name Function Reset 31:30 RESERVED Reserved for future expansion. 29:27 CONF_G14 Controls multiplexing on G14. Formerly CONF_LCD_PIXEL_3_R. 26:24 CONF_H13 Controls multiplexing on H13. Formerly CONF_LCD_PIXEL_4_R.
Page 489 Configuration Table 38. Functional Multiplexing Control F Register (FUNC_MUX_CTRL_F) Base Address = 0xFFFE 1000, Offset Address = 0x94 Name Function Reset 31:30 RESERVED Reserved for future expansion. 29:27 CONF_V2 Controls multiplexing on V2. Formerly CONF_FRDY_R. 26:24 CONF_U4 Controls multiplexing on U4. Formerly CONF_NFOE_R. 23:21 CONF_W1 Controls multiplexing on W1.
Page 490 Configuration Table 39. Functional Multiplexing Control 10 Register (FUNC_MUX_CTRL_10) Base Address = 0xFFFE 1000, Offset Address = 0x98 Name Function Reset 11:9 CONF_L4 Controls multiplexing on L4. Formerly CONF_NFADV_R. CONF_L3 Controls multiplexing on L3. Formerly CONF_NFBE_0_R. CONF_M8 Controls multiplexing on M8. Formerly CONF_NFBE_1_R. CONF_M7 Controls multiplexing on M7.
Page 491 Configuration Table 41. Functional Multiplexing Control 12 Register (FUNC_MUX_CTRL_12) Base Address = 0xFFFE 1000, Offset Address = 0xA0 Name Function Reset 31:30 RESERVED Reserved for future expansion. 29:27 RESERVED Reserved for future expansion. 26:24 CONF_J8 Controls multiplexing on J8. Formerly CONF_FADD_1_R. 23:21 CONF_D3 Controls multiplexing on D3.
Page 492 Configuration Table 42. Pulldown Control 4 Register (PULL_DWN_CTRL_4) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xAC Name Function Reset CONF_PDEN_M3 Enables (0) pullup or pulldown on M3. CONF_PDEN_N8 Enables (0) pullup or pulldown on N8. CONF_PDEN_N3 Enables (0) pullup or pulldown on N3. CONF_PDEN_J8 Enables (0) pullup or pulldown on J8.
Page 493 Configuration This register controls the enable or disable of the combined pullup/pulldown cell (0 = enabled, 1 = disabled). When enabling the cell, the user must set the corresponding bit in PU_PD_SEL_4 to select either a pullup or a pulldown. The pinout documentation (Application Processor Data Manual (SPRS231)) must be consulted to determine whether a pullup or pulldown exists on the specified I/O.
Page 494 Configuration Table 43. Pullup/Pulldown Selection 0 Register (PU_PD_SEL_0) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xB4 Name Function Reset RESERVED Reserved for future expansion. CONF_PU_PD_G18 Configure pullup (=1) or pulldown (=0) on G18. CONF_PU_PD_F19 Configure pullup (=1) or pulldown (=0) on F19. CONF_PU_PD_H14 Configure pullup (=1) or pulldown (=0) on H14.
Page 495 Configuration Table 44. Pullup/Pulldown Selection 1 Register (PU_PD_SEL_1) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xB8 Name Function Reset CONF_PU_PD_Y12 Configure pullup (=1) or pulldown (=0) on Y12. CONF_PU_PD_W19 Configure pullup (=1) or pulldown (=0) on W19. CONF_PU_PD_P15 Configure pullup (=1) or pulldown (=0) on P15.
Page 496 Configuration This register controls the selection of the pullup or pulldown (0 = pulldown, 1 = pullup). The pinout documentation must be consulted to determine whether a pullup or pulldown exists on the specified I/O. COMP_MODE_CTRL_0 must be programmed to 0xEAEF for this register to control the selection. Table 45.
Page 497 Configuration Table 45. Pullup/Pulldown Selection 2 Register (PU_PD_SEL_2) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xBC Name Function Reset CONF_PU_PD_V15 Configure pullup (=1) or pulldown (=0) on V15. CONF_PU_PD_P14 Configure pullup (=1) or pulldown (=0) on P14. CONF_PU_PD_AA17 Configure pullup (=1) or pulldown (=0) on AA17.
Page 498 Configuration Table 46. Pullup/Pulldown Selection 3 Register (PU_PD_SEL_3) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xC0 Name Function Reset CONF_PU_PD_A20 Configure pullup (=1) or pulldown (=0) on A20. CONF_PU_PD_B19 Configure pullup (=1) or pulldown (=0) on B19. CONF_PU_PD_C18 Configure pullup (=1) or pulldown (=0) on C18.
Page 499 Configuration This register controls the selection of the pullup or pulldown (0 = pulldown, 1 = pullup). The pinout documentation in SPRS231 should be consulted to determine whether a pullup or pulldown exists on the specified I/O. COMP_MODE_CTRL_0 must be programmed to 0xEAEF for this register to control the selection.
Page 500 Configuration Table 47. Pullup/Pulldown Selection 4 Register (PU_PD_SEL_4) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0xC4 Name Function Reset CONF_PU_PD_G2 Configure pullup (=1) or pulldown (=0) on G2. CONF_PU_PD_K8 Configure pullup (=1) or pulldown (=0) on K8. CONF_PU_PD_H4 Configure pullup (=1) or pulldown (=0) on H4.
Page 501 Configuration Table 48. Module Configuration Control 1 Register (MOD_CONF_CTRL_1) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x110 Name Function Reset CONF_OSC1_GZ_R Disables oscillator. See Table 49. 0: 12-MHz oscillator GZ pin is not activated. 1: 12-MHz oscillator GZ pin is activated (oscillator is disabled).
Page 502 Configuration Table 48. Module Configuration Control 1 Register (MOD_CONF_CTRL_1) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x110 Name Function Reset 15:14 CONF_MOD_GPTIMER8_ This register selects the clock source for CLK_SEL_R general-purpose timer 8. 00 = ARMXOR_CLK 01 = 32-kHz clock 10 = EXT_CLK of the device external timer clock 11 = Reserved;...
Page 503 Configuration Table 48. Module Configuration Control 1 Register (MOD_CONF_CTRL_1) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x110 Name Function Reset CONF_MOD_GPTIMER3_ This register selects the clock source for CLK_SEL_R general-purpose timer 3. 00 = ARMXOR_CLK 01 = 32-kHz clock 10 = EXT_CLK of the device external timer clock 11 = Reserved;...
Page 504 Configuration Table 50. Configuration Status Register (CONF_STATUS) Base Address = 0xFFFE 1000, Offset Address = 0x130 Name Function Reset 31:6 UNUSED These bits are not implemented. CONF_DEVICE_TYPE_R Contains the status of the eFuses that determine the type of device. 00: Production (normal) device 01: Bad device 10: Emulator device 11: Test device...
Page 505 Configuration Table 50. Configuration Status Register (CONF_STATUS) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x130 Name Function Reset CONF_ARM_BOOT_STAT This register contains boot mode active chip-select (CONF_ARM BOOT MODE), latched at the rising edge of PWRON_RESET. Emulator type devices only, 0: MPU boots from internal ROM 1: MPU boots from external memory Reset value for this signal depends on...
Page 506 Configuration Table 51. Reset Control Register (RESET_CONTROL) (Continued) Base Address = 0xFFFE 1000, Offset Address = 0x140 Name Function Reset CONF_OSTIMER_ This register controls reset of the OS timer. RESET_R 0: OS timer is in reset. 1: OS timer is in functional mode. CONF_ARMIO_RESET_R This register controls reset of the MPUIO.
Page 507 Configuration Table 52. OMAP5912 Configuration Control Register (CONF_5912_CTRL) Base Address = 0xFFFE 1000, Offset Address = 0x150 Name Function Reset 31:16 RESERVED Reserved. 0x0000 15:4 RESERVED Reserved. 0x000 RESERVED Reserved. RESERVED This bit should be set to 0. RESERVED Reserved.
Page 508: External Interfaces
External Interfaces External Interfaces This section describes the various external interfaces supported by this device. It also gives an overview of duplicated interfaces. External Interface Descriptions This device supports different classes of interfaces: Reset, clocks, and power management General-purpose input/output Keyboard interface General-purpose counter Memory interfaces...
Page 509: Duplicated Interfaces
External Interfaces Display interface LCD interface Emulation JTAG Trace interface The user selects the appropriate interfaces for an application during the boot sequence. In effect, only a subset of all possible interfaces is available at power-on reset. For flexibility, some interfaces are duplicated. See the pinout section of the Application Processor Data Manual (SPRS231) to select the desired configuration.
Page 510 External Interfaces Table 54 indicates the interfaces after programming the configuration registers. Table 54. Configuration After Programming Ball I/O Description Mode MMC2.CLK MMC2.CMD/SPI.DO MMC2.CMDDIR MMC2.DAT0/SPI.DI MMC2.DAT1 MMC2.DAT3 MMC2.DATDIR0 MMC2.DATDIR1 ETM_PSTAT[1] ETM_PSTAT[2] ETM_PSTAT[0] ETM_D[6] ETM_D[7] ETM_D[0] SPRU752B Initialization...
Page 511: Reset/Boot Overview
Reset/Boot Overview Reset/Boot Overview The memory interfaces and clock sources are controlled and configured during power-on reset by external pins and on-chip electronic fuses (eFuses). Boot Mode Control and EMIFS Multiplexing Control Generation The device type changes depending on the programming at the probe of the eFuse bits.
Page 512: Configuration Of Interfaces In Internal Boot Rom
Reset/Boot Overview Table 55. EMIFS Multiplexing Control and MPU_BOOT Mode Signal Generation for Reset Mode 0 (Continued) DEVICE_TYPE MPU_BOOT GPIO1 Boot Default EMIFS EMIFS Protocol Protocol (after boot) Production (sampled at (sampled (at Boot) Emulation reset) at reset) Emulation Internal on Nonaddress/data Nonaddress/data multiplexed...
Page 513 Reset/Boot Overview Configuration needed for NAND EMIFS (enable GPIO_10). FUNC_MUX_CTRL_F: 0x0800 0000 Configuration needed for USB Client Initialization FUNC_MUX_CTRL_D: 0x0000 0018 Configuration needed for USB port1 detection FUNC_MUX_CTRL_8: 0x1000 0000 FUNC_MUX_CTRL_9: 0x0100 0014 FUNC_MUX_CTRL_A: 0x0000 0290 Configuration needed to enable UART pins FUNC_MUX_CTRL_6: 0x0000 0001 FUNC_MUX_CTRL_9: 0x0020 1000 FUNC_MUX_CTRL_10: 0x0000 0001...
Page 514: Omap Device Identification Registers
Reset/Boot Overview OMAP Device Identification Registers The following registers are chip revision registers for the device. Reset values depend on the device are are listed in the tables as unknown. Table 56. OMAP Die ID Register (OMAP_DIE_ID_0) Address = 0xFFFE 1800 Name Function Reset...
Page 515 Reset/Boot Overview Table 58. OMAP Die ID Register (OMAP_PRODUCTION_ID_0) Address = 0xFFFE 2000 Name Function Reset 31:30 SECURITY Security device type. 00: General-purpose device type (GP) 29:25 RESERVED Reserved. 24:9 ID_KEY Reserved for special identification. 0x5555 Secure protect. DFT write MPU. MPU DFT write value. DFT read MPU.
Page 516 Reset/Boot Overview Some of the bit fields described above will change depending on the chip revision. Table 61 lists device revisions. Note that new revisions may exist. Please contact your TI representative for more information. Table 61. Revision Table Revision Part # PROD_ID DEV_REV...
Page 517 This page is intentionally left blank. Initialization SPRU752B...
Page 518 OMAP5912 peripherals resets, clock and reset architecture 15 OMAP5912 reset/boot overview 94 interfaces configuration in internal boot ROM 95 OMAP5912 resets, clock and reset architecture 8 Duplicated interfaces, OMAP5912 initialization 92 OMAP5912/5910 SW/HW compatibility, OMAP5912 configuration 33 EMIFS multiplexing control generation, OMAP5912...
Page 519 OMAP5912 Multimedia Processor Power Management Reference Guide Literature Number: SPRU753A March 2004...
Page 520 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 521 OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
Page 522 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 523 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU753A...
Page 524 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 525 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 526 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 527 Contents Contents Ultralow-Power Device ............ULPD Features .
Page 528 ......... . . OMAP5912 Power Management Software User Guide .
Page 529 ........Control of OMAP5912 Low-Power Output by ULPD POWER_CTRL_REG .
Page 530 Tables Tables Sleep Modes versus Active Mode (Summary) ........Initiators to Deep Sleep −>...
Page 531 ......OMAP5912 Peripherals With Clock Autogating Enable Feature .....
Page 532 OMPA5912 SPRU753A...
Page 533: Ultralow-Power Device
Power Management This document describes power management in the OMAP5912 multimedia processor. Ultralow-Power Device The ultralow-power device (ULPD) generates and manages clocks and reset signals to OMAP3.2 and to some peripherals. It controls chip-level power-down modes and handles chip-level wake-up events. In deep sleep mode, this module is still active to monitor wake-up events.
Page 534: Overview
Ultralow-Power Device Overview The ULPD is a power management module running at 32 kHz (CLK32K). The ULPD employs three global-system power modes: awake mode, big sleep mode, and deep sleep mode. See Section 1.5, Power Modes, for a description of these modes and the transitions between them. The ULPD controls the various module clocks with several input clock sources provided by the oscillator and by the OMAP3.2 DPLL and the 96-MHz analog phase-locked loop (APLL).
Page 535 Ultralow-Power Device Figure 1. ULPD and Clock Domains in OMAP5912 OMAP5912 Processor clock MMU clock Clock control Timers clock Watchdog clock module2 Interrupts clock External Pheriperals clock clocks DSP clocks domain Processor clock MMU clock Clock control Timers clock Watchdog clock...
Page 536: Ulpd Input Clock Sources
(for example, oscillator and regulator). The ULPD FSM1 is instantiated in OMAP5912 with two setup counters, each associated with an analog cell. Setup counters are cascaded and must be programmed with the stabilization time of the associated analog cell.
Page 537: Power Modes
OSC12M_STOP output of ULPD is active high every time the state machine is in a deep-sleep state. EXT_CLK_REQ is the same signal but with inverted polarity. OMAP5912 cannot go into deep−sleep while an emulator (JTAG) is connected 1.5.2 Big Sleep Mode In big sleep mode, the OMAP input clock is inactive, the 32-kHz clock is active, and the system input clock is active in both oscillator and external modes.
Page 538: Awake Mode
Ultralow-Power Device This mode has a shorter wake-up latency. It also provides clocks (system frequency clocks and/or ULPD_PLL clock) to peripherals whenever requested and while the OMAP3.2 input clock is stopped. 1.5.3 Awake Mode In awake mode, the OMAP input clock and any requested peripheral clocks are active.
Page 539: Behavior Of Low_Pwr
Ultralow-Power Device Figure 3. Release of LOW_PWR CLK32K_IN CK_REF ULPD_STATE Deep sleep Awake sequence Awake state LOW_PWR System clock request Must be OMAP wake up or a peripheral request 1.6.2 Behavior of LOW_PWR The LOW_PWR signal is used in oscillator clock mode to control an external power management device.
Page 540: Low-Voltage Operation At Reduced Clock Frequency
Ultralow-Power Device At reset, the low-power feature is disabled (POWER_CTRL_REG[0] is set to 0). The LOW_PWR signal is inactive low, which indicates a nominal voltage requirement. Figure 4. Behavior of LOW_PWR in RESET_MODE 0 ULPD state Awake... Deep sleep Setup Big sleep...
Page 541: Transitions Between Power Modes
POWER_CTRL_REG[11]=0. This feature allows dynamic control of the operating voltage of OMAP5912. It provides two operating points (voltage, frequency) to adapt the operating voltage to the performance requirement. The OMAP3.2 DPLL frequency must be set accordingly before initiating the procedure.
Page 542 Ultralow-Power Device Figure 6. Simplified State Diagram of the ULPD FSM1 Wake-up request from OMAP or UART2 request for system clock BIG SLEEP AWAKE Idle request from OMAP and external clock request or not Wake-up request from POWER_CTRL_REG No external clock request. OMAP or UART2 request [DEEP_SLEEP_ No wake-up request from OMAP...
Page 543: Power-On Transition To Deep Sleep Mode
Ultralow-Power Device 1.10 Power-on Transition to Deep Sleep Mode At power-up, namely when the power-up input signal PWRON_RESET is asserted low, the ULPD FSM1 enters deep sleep mode. In this case, the LOW_PWR signal is reset to inactive state 1. When PWRON_RESET is released, the FSM automatically switches from deep sleep to awake.
Page 544 CONF_MOD_MMC_SD2_CLK_REQ_R (register) MMC/SDIO2 Clock request by USB USB OTG. See Note 4. MCLKREQ OMAP5912 input pin BCLKREQ OMAP5912 I/O input pin SOFT_REQ_REG (active) Software requests. See Note 5. Other DEEP_TRANSITION_ENABLE ULPD Notes: 1) Software requests prevent the transition to deep sleep when leaving awake state but are not initiators of deep sleep to big sleep transition.
Page 545: Transition From Deep Sleep To Awake Mode
Ultralow-Power Device b) Oscillator mode: this case, setup counter, SETUP_ANALOG_CELL2, is loaded with the related setup value from the ULPD register that corresponds to the maximum time between ramp-up time of the external voltage supply and LDO stabilization time. When the counter underflow is generated, it enables the oscillator. Then the setup counter, SETUP_ANALOG_CELL3, is loaded with the related setup value from the ULPD register that corresponds to the stabilization delay of the oscillator.
Page 546 Ultralow-Power Device Table 3. Initiators of Deep Sleep −> Awake Transition Transition from Deep Sleep to Awake Wake-up Event PWRON_RESET Power-on reset pin RTC_ON_NOFF Power-on reset pin MPU_RST System reset pin 32-kHz watchdog reset 32-kHz watchdog time-out Wake-up request Peripheral unmasked interrupts PERIPH_REQ PERIPH_REQ System clock request from UART2...
Page 547 Ultralow-Power Device b) Oscillator mode: this case, setup counter, SETUP_ANALOG_CELL2, is loaded with the related setup value from the ULPD register that corresponds to the maximum time between ramp-up time of the external voltage supply and LDO stabilization time. When the counter underflow is generated, it enables the oscillator. Then the setup counter, SETUP_ANALOG_CELL3, is loaded with the related setup value from the ULPD register that corresponds to the stabilization delay of the oscillator.
Page 548 Ultralow-Power Device Figure 7. OMAP3.2-Initiated Wake-up Sequence CLK32K_IN CK_REF (Internal system clock) 4 CK_REF ULPD_STATE Deep sleep Awake sequence Awake state CHIP_IDLE (internal signal) CHIP_WAKEUP (internal signal) LOW_PWR OMAP3.2 wake−up request (internal) The wake-up sequence requires five CLK32K clock cycles from assertion of OMAP3.2 wake-up request to release of CK_REF.
Page 549: Transitions From Big Sleep Mode
Ultralow-Power Device Figure 8. Wake-up Sequence in Case of Warm Reset CLK32K_IN CK_REF (Internal system clock) Awake sequence ULPD_STATE Deep sleep or big sleep Awake state CHIP_IDLE (internal signal) CHIP_WAKEUP (internal signal) MPU_RST 30 CK_REF periods OMAP3.2 RESET (internal signal) 1.12 Transitions From Big Sleep Mode 1.12.1...
Page 550: Transition From Big Sleep Mode To Awake Mode
Ultralow-Power Device 1.12.2 Transition From Big Sleep Mode to Awake Mode The transition to awake mode occurs when OMAP3.2 requests wake-up or UART2 requests system clock. An OMAP3.2 wake-up request is initiated by the unmasked interrupts of the peripherals. The transition follows this sequence: 1) Wake-up event occurs (OMAP3.2 wake-up request or UART2 requests system clock) 2) FSM1 enters the awake mode.
Page 551: Transition From Awake Mode To Big Sleep Mode
Ultralow-Power Device Figure 9. Sleep Sequence CLK32K_IN CK_REF (system clock) CHIP_IDLE (internal signal) CHIP_WAKEUP (internal signal) LOW_PWR Sleep sequence ULPD_STATE Awake state Deep sleep or big sleep The sleep sequence requires three cycles of the CLK32K clock from assertion of the CHIP_IDLE signal to assertion of the LOW_PWR signal. Note: The name of the signal CHIP_WAKEUP may confuse users.
Page 552: Ulpd Output Clocks
The ULPD controls the system clock (12 MHz or 19.2 MHz) and the various 48-MHz clocks used by OMAP5912 peripherals. These clocks supply the OMAP3.2 subsystem and some of the OMAP5912 peripherals. Figure 10 shows a simplified diagram of the ULPD clock generation scheme.
Page 553 Ultralow-Power Device Figure 10. Basic Diagram of the ULPD Output and Input Clocks ULPD CAM.EXCLK System clock 48 MHz (UART1) 48 MHz (UART2) 48 MHz (UART3) 48 MHz (USB OTG) 12/13-19.2 Mhz MPU peripheral clock (to APLL) EXT_48M Clock (Camera I/F) MCLK ULPD_PLL_CLK BCLK...
Page 554 Ultralow-Power Device Table 4. ULPD Output Clocks Description OMAP5912 I/O Clock Source Wake-up Soft Request Destination Selection Request Disable Clock Selected BCLK Derived from APLL SDW_SYSCLK_ BCLKREQ SOFT_DISABLE_ CLK/2 PLLCLK_SEL REQ_REG[1] CLOCK_CTRL_ REG[2] SDW_CLK_DIV_ CTRL_SEL[7:2] (see Note 1) MCLK Derived from APLL...
Page 555 Ultralow-Power Device Table 4. ULPD Output Clocks Description (Continued) OMAP5912 I/O Clock Source Wake-up Soft Request Destination Selection Request Disable Clock Selected CAM.D[7] EXT.48M CONF_DPLL_EXT_ SOFT_REQ_ (See Note 4.) REG[0] APLL CLK/2 Clock request to APLL UART1 EXT.48M CONF_DPLL_EXT_ MOD_CONF_...
Page 556 Ultralow-Power Device Table 4. ULPD Output Clocks Description (Continued) OMAP5912 I/O Clock Source Wake-up Soft Request Destination Selection Request Disable Clock Selected USB OTG EXT.48M CONF_DPLL_ USB request for SOFT_REQ_ EXT_SEL 48 MHz REG[4] APLL CLK/2 (see Note 5) SOFT_DISABLE_...
Page 557 5) The USB will request 48 MHz clock in case of the following event: − The USB has detected that either an external host or an external device is attached to one of the configured OMAP5912 USB ports, or − The USB exits the suspend mode and enters the resume mode.
Page 558 Ultralow-Power Device Table 5. Clock Request to Clock Available Latencies Latency Name Description 4 x 32-kHz clock cycles + setup analog cell 3 x 32-kHz clock cycles 2 x 32-kHz clock cycles + setup analog cell 1 x 32-kHz clock cycles 1 x 32-kHz clock cycles + APLL lock time 2 x 32-kHz cycles + setup analog cell + APLL lock time 2 x 32-kHz clock cycles...
Page 559 Ultralow-Power Device Table 6. Latencies for Each Peripheral (Continued)Clock (Continued) Name Wake-Up Request Time to Get the Clock Active Depending on Initial FSM State Deep Awake Sleep Sleep • PWRON_RESET Functional Clock UART2 • MPU_RST • RTC_ON_NOFF • 32-kHz watchdog time-out •...
Page 560: Power-Up And Reset Management
Ultralow-Power Device Table 6. Latencies for Each Peripheral (Continued)Clock (Continued) Name Wake-Up Request Time to Get the Clock Active Depending on Initial FSM State Deep Awake Sleep Sleep • CONF_MOD_MMC_SD_CLK_REQ_R 48 MHz for MMCSDIO1 • SOFT_REQ_REG[12] • CONF_MOD_MMC_SD2_CLK_REQ_R 48 MHz for MMCSDIO2 •...
Page 561: Generic Power-Up Sequence In Oscillator Mode
Ultralow-Power Device The ULPD controls the oscillator and inserts proper setup times at power-up to ensure that a stable clock is released to the system. In this mode, PWRON_RESET must be released only when the 32-kHz clock and the supply voltage are stable. If RESET_MODE is at 1, the ULPD starts in external clock mode.
Page 562: Power-Up Sequence In External Clock Mode
Ultralow-Power Device Figure 12. Power-up Sequence in Oscillator Mode CLK32K_IN PWRON_RESET RESET_MODE0 Dxdk32k ANALOG_CELL_2_EN Glitch less latency mechanism ANALOG_CELL_3_EN CK_REF LOW_PWR 1.15.3 Power-up Sequence in External Clock Mode In external mode, all the analog cell setup counters are bypassed at power-up reset.
Page 563: Ulpd Reset Inputs
Ultralow-Power Device Figure 13. Power-up Sequence in External Clock Mode CLK32K_IN PWRON_RESET RESET_MODE1 Glitch less latency mechanism CK_REF At this step the system clock must be stable. SYS_CLK_IN LOW_PWR 1.16 ULPD Reset Inputs The ULPD has five distinct reset inputs that act differently on the ULPD generated output reset.
Page 564: Omap3.2 Embedded Ldo For Dpll[3] Control
Ultralow-Power Device Figure 14. OMAP3.2 Input Reset Generation VDD / DVDDx CLK32K_IN PWRON_RESET Optional warm reset MPU_RST CK_REF Internal cold reset 30 x system clock Cold reset sequence for OMAP Internal warm reset 2 x sleep 20 x system Optional warm reset Variable 30 x clock...
Page 565: Analog Phase-Locked Loop Control
Ultralow-Power Device If needed, the e-LDO can be tuned by adjusting SETUP_ANALOG_CELL2 in oscillator mode or SETUP_ANALOG_CELL3 in external mode. 1.19 Analog Phase-Locked Loop Control To provide a 48-MHz clock to peripherals that request it, the ULPD controls the activation and deactivation of an on-chip analog phase-locked loop (APLL). This APLL delivers a 96-MHz clock that is further divided inside the ULPD.
Page 566 Ultralow-Power Device Figure 16. RST_HOST_OUT Activation on PWRON_RESET PWRON_RESET RST_HOST_OUT 2 x 32 kHz clock cycle Upon a low level on BFAIL/EXTFIQ input, which signals a battery fail event, the ULPD starts a programmable counter. When the counter underflows, ULPD asserts low RST_HOST_OUT and places OMAP3.2 in power-down mode.
Page 567: 32-Khz Oscillator Calibration
Ultralow-Power Device 1.21 32-kHz Oscillator Calibration Figure 18. Functional Block Diagram of Gauging GAUGING_EN TIPB register Clear TIPB Counter high frequency EXT_HICLK_SEL OVERFLOW_HI_FREQ 46-MHz clock EXT_HITCH_GAUGING System clock Clear SELECT_HI_FREQ Counter low frequency TIPB register OVERFLOW_LO_FREQ 32-kHz clock Because the exact 32-kHz clock frequency is unknown, it is necessary to gauge it by comparing the 32-kHz clock with a higher frequency clock (system clock, APLL clock out, or EXT_HICLK_GAUGING) during any active period.
Page 568: Ulpd Interrupt Generation
Ultralow-Power Device 1.23 ULPD Interrupt Generation The ULPD generates an interrupt when one of the following events has been detected: An overflow occurred on the 32-kHz counter during gauging. This event is the same as the one that triggers the IT_STATUS_REG [2] bit. An overflow occurred on the HI_FREQ counter during gauging versus high frequency.
Page 569 Ultralow-Power Device Table 7. ULPD Registers (Continued) Base Address = 0xFFFE 0800 Name Description Offset SETUP_ANALOG_CELL2_ULPD1_REG Setup analog cell2 ULPD1 0x28 SETUP_ANALOG_CELL1_ULPD1_REG Setup analog cell1 ULPD1 0x2C CLOCK_CTRL_REG Clock control 0x30 SOFT_REQ_REG Software request 0x34 COUNTER_32_FIQ_REG Counter 32 FIQ 0x38 RESERVED Reserved 0x3C...
Page 570 Ultralow-Power Device Table 8. Counter 32 LSB Register (COUNTER_32_LSB_REG) Base Address = FFFE 0800, Offset = 0x00 Name Function Reset 15:0 COUNTER_SLEEP_ Lower value of the number of sleep clock cycles CLK_LSB during gauging time Note: The CPU must check that the IT_STATUS_REG[0] bit has been asserted high before reading this register. Table 9.
Page 571 Ultralow-Power Device Table 12. Gauging Control Register (GAUGING_CTRL_REG) Base Address = 0xFFFE 0800, Offset = 0x10 Name Function Reset 15:2 UNUSED Unused SELECT_HI_FREQ_CLOCK 1: High-frequency clock = auxiliary gauging clock 0: High-frequency clock = 12-Mhz clock GAUGING_EN 1: Gauging is running. 0: Gauging is stopped.
Page 572 Ultralow-Power Device Table 15. Reserved Register (RESERVED) Base Address = 0xFFFE 0800, ?Offset = 0x1C Name Function Reset 15:0 RESERVED Reserved 0x3FF Table 16. Setup Analog Cell3 ULPD1 Register (SETUP_ANALOG_CELL3_REG) Base Address = 0xFFFE 0800, Offset = 0x24 Name Function Reset 15:0 SETUP_ANALOG_CELL3...
Page 573 Ultralow-Power Device Table 19. Clock Control Register (CLOCK_CTRL_REG) (Continued) Base Address = 0xFFFE 0800, Offset = 0x30 Name Function Reset TI_RESERVED_EN 0: Disable clock on SYS_CLK_OUT output. 1: Enable. SDW_MCLK_INV 0: BLUETOOTH_CLK is low when inactive. 1: CLK is high when inactive COM_MCLK_INV 0: Modem clock is low when inactive.
Page 574 Ultralow-Power Device Table 20. Software Request Register (SOFT_REQ_REG) (Continued) Base Address = 0xFFFE 0800, Offset = 0x34 Name Function Reset SOFT_USB_OTG_DPLL_REQ Software request for USB OTG for ULPD_PLL clock. 1: Request active 0: Request inactive SOFT_CAM_DPLL_MCKO_REQ Software camera ULPD_PLL request. 1: Request active 0: Request inactive SOFT_COM_MCKO_REQ...
Page 575 Ultralow-Power Device Table 22. Reserved Register (RESERVED) Base Address = 0xFFFE 0800, Offset = 0x3C Name Function Reset 15:0 RESERVED Reserved Table 23. Status Request Register (STATUS_REQ_REG) Base Address = 0xFFFE 0800, Offset = 0x40 Name Function Reset CLOCK3_DPLL_REQ ULPD_PLL clock request from request Unknown RESERVED3 1: Active...
Page 576 Ultralow-Power Device Table 23. Status Request Register (STATUS_REQ_REG) (Continued) Base Address = 0xFFFE 0800, Offset = 0x40 Name Function Reset USB_DPLL_MCLK_REQ ULPD_PLL clock request from USB client Unknown 1: Request active 0: Request inactive USB_MCLK_REQ Hardware system clock request by USB Unknown client 1: Request active...
Page 577 Ultralow-Power Device Table 25. Reserved Register (RESERVED_48) Base Address = 0xFFFE 0800, Offset = 0x48 Name Function Reset 15:0 RESERVED Kept for software compatibility reason. Has no effect on 0x960 ULPD behavior. Table 26. ULPD PLL Control Status Register (ULPD_PLL_CTRL_STATUS) Base Address = 0xFFFE 0800, Offset = 0x4C Name Function...
Page 578 Ultralow-Power Device Table 27. Power Control Register (POWER_CTRL_REG) (Continued) Base Address = 0xFFFE 0800, Offset = 0x50 Name Function Reset SOFT_LDO_SLEEP Control the sleep of the e-LDO that supplies the DPLL 1=> LDO sleep is forced to active state. 0=> LDO not in sleep (except in deep sleep mode if LDO_CTRL_EN=1) LDO_CTRL_EN...
Page 579 Ultralow-Power Device Table 28. Status Request Register 2 (STATUS_REQ_REG2) Base Address =0xFFFE 0800, Offset = 0x54 Name Function Reset 15:1 UNUSED Unused MMC2_DPLL_REQ Status of the MMC2_PLL_REQ Unknown 0: Inactive 1: Active Note: Bit 0 in this register reflects the state of the clock request regardless of whether it is masked or not (by the corresponding SOFT_DISABLE_REQ_REG bit).
Page 580 Ultralow-Power Device Table 32. Setup Analog Cell6 ULPD1 Register (SETUP_ANALOG_CELL6_REG) Base Address = 0xFFFE 0800, Offset = 0x64 Name Function Reset 15:0 SETUP_ANALOG_CELL6 Setup time of analog cell6 in number of sleep clock cycles Note: This setup stage is for the FSM1 of the ULPD. Table 33.
Page 581 Ultralow-Power Device Table 33. Software Disable Request Register (SOFT_DISABLE_REQ_REG) (Continued) Base Address =0xFFFE 0800, Offset = 0x68 Name Function Reset DIS_UART1_DPLL_REQ Disable UART1 PLL hardware request 0: Not disabled 1: Disabled DIS_USB_HOST_DPLL_REQ Disable the USB host system clock hardware 0: Not disabled 1: Disabled DIS_CAM_DPLL_MCLK_REQ Disable hardware CAM_PLL_MCLK_REQ.
Page 582 Ultralow-Power Device Table 34. Reset Status Register (RESET_STATUS) (Continued) Base Address = 0xFFFE 0800, Offset = 0x6C Name Function Reset Security Violation Whenever a security violation event occurs, this bit is asserted.The user clears this bit by writing a 0. TIPB reset has no effect on this bit.
Page 583 Ultralow-Power Device Table 36. SDW Clock Divider Control Select Register (SDW_CLK_DIV_CTRL_SEL) Base Address = 0xFFFE 0800, Offset = 0x74 Name Function Reset 15:8 UNUSED Unused SDW_RATIO_SEL Select the divider ratio to apply to the APLL output clock to generate BCLK. 000000=>1;...
Page 584 Ultralow-Power Device Table 37. COM Clock Divider Control Select Register (COM_CLK_DIV_CTRL_SEL) (Continued) Base Address = 0xFFFE 0800, Offset = 0x78 Name Function Reset COM_ULPD_PLL_CLK_REQ MCLK clock software request 0: Request inactive 1: Request active COM_SYSCLK_PLLCLK_SEL 0: Select the divided version of APLL output clock for MCLK 1: Select SYSTEM_CLOCK for MCLK or 48 Table 38.
Page 585: Power System Overview
The OMAP5912 architecture implements hardware features so that various power management strategies can be enacted. Power Domains Table 40 lists all OMAP5912 power supplies with their respective nominal value and power domains. Figure 19 shows how those power domains are connected or can be isolated from one another.
Page 586 When using 3.3V power, CONF_VOLTAGE_SDRAM_R bit should be set to 1 (2.75V) for better performance. Notes: 3) Refer to the OMAP5912 Data Manual (SPRS231) for more information on nominal voltage min/max ranges. OMAP 5912 can be split into power planes and power domains: A power plane is composed of components that are supplied by a dedicated power rail.
Page 587 Isolation layer Power supply control signals domain OMAP5912 The different OMAP5912 power domains (RTC, MPU, and DSP) can be powered as shown in Table 41. Table 41. Powering OMAP5912 Domains † State 1 State 2 State 3 † V = 1.5 V or 1.1 V.
Page 588: Clock Domain
Clock Domain OMAP5912 can be split into clock domains and subdomains. As shown in Figure 20, OMAP5912 is divided into four clock domains. The RTC clock domain is totally independent and can be isolated by hardware from other clock domains.
Page 589 Power System Overview Figure 20. OMAP5912 Clock Domains OMAP5912 Processor clock MMU clock Clock control Timers clock Watchdog clock module2 Interrupts clock External Pheriperals clock clocks DSP clocks domain Processor clock MMU clock Timers clock Clock control Watchdog clock module1...
Page 590: Power Management User Services
Power Management User Services Power Services Power services include software and hardware mechanisms that allow the user to reduce OMAP5912 chip power-consumption during all system phases. Static Clock Management During major system phases, the clocks of each domain can be immediately validated or reconfigured by software register modification.
Page 591 Power Management User Services Table 42 describes all OMAP3.2 subsystem clocks, and Figure 21 provides an overview of their generation. Table 42. OMAP3.2 Subsystem Clocks Clock Name Description CK_DPLL1OUT Clock from DPPL1, same as MPU clock ARMCPU_CK Clock with same frequency as MPU clock, same as ARM_CK ARMXOR_CK MPU peripheral clock, fixed, generated from CK_GEN1, can be gated ARMPER_CK...
Page 592 Power Management User Services Figure 21. OMAP3.2 Clock Generation CK_GEN1 CK_DPLL1OUT IDLE condition + SW Clock Enable: ARM_IDLECT2[EN_CKOUT_ARM(11)] ARM_CK Frequency divider ARM_CK IDLE condition ARM_CKCTL[ARMDIV(5:4)] ARMCPU_CK ARMPER_CK Frequency divider IDLE condition + SW Clock Enable: ARM_CKCTL[PERDIV(1:0)] ARM_IDLECT2[EN_PERCK(2)] external CK_REF peripherals ARMXOR_CK IDLE condition + SW Clock Enable: ARM_IDLECT2[EN_XORPCK(1)]...
Page 593: Dsp (Mgs3) Clocks Management
Power Management User Services Clock subdomain control is done by software write to the CLKRST registers: ARM_CKCTL ARM_IDLECT1 ARM_IDLECT2 ARM_SYSST DSP_CKCTL DSP_IDLECT1 DSP_IDLECT2 DSP_SYSST As shown in Figure 21, the clock reference to build all other clocks is provided and controlled by the ULPD (ultralow-power device) module. The ULPD module performs several functions, which can be divided into three groups: Power-mode control...
Page 594 Power Management User Services Table 43. Idle Configuration Register (ICR) (Continued) MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x01 (word) Name Function R/W * Reset Reserved idle domain. EMIF EMIF idle domain. DPLL DPLL idle domain.
Page 595: Local Power Management
Power Management User Services Table 44. Idle Status Register (ISTR) (Continued) MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x02 (word) Name Function Reset RHEA_IDLECACHE_TR CACHE idle status. RHEA_IDLEDMA_TR DMA idle status. RHEA_IDLECPU_TR CPU idle status.
Page 596 Power Management User Services Table 45. EMIF Global Control Register (GCR) MPU Base Address (byte) = 0xE100 0800, DSP Base Address (word) = 0x00 0800, Offset = 0x00 (word) Name Function Reset 15:11 RESERVED Reserved 10:9 MEMFREQ MEMory clock FREQuency MEMFREQ = 00: SBSRAM and/or the SDRAM interface is configured for 1x mode and the CLKMEM clock frequency is equal to the DSP clock frequency...
Page 597 Power Management User Services Table 46. TIPB Control Mode Register (CMR) MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x00 (word) Name Description Reset CPU Access MPU Access [15−9] Timeout(6:0) Strobe cycles 0x7F Read/Write Read...
Page 598: Rng Clocks
Power Management User Services 3.2.4 RNG CLOCKS The RNG module is divided into four principal blocks: RING oscillators RNG generator State machine Output and input registers The random numbers are accessible to the application in a 32-bit read-only register (RNG_OUT). Once the register is read, the RNG module immediately generates a new value.
Page 599: Partial Rng Shutdown: Input Clock Cut Off
Power Management User Services Figure 22. Total Automatic RNG Shutdown Input system clock Clock and (OCP) reset module cutted (5) OCP clock RINGS Clock oscillators reference generator cutted (4) External clocks disable (2) ULPD RNG idle signal No read (1) indication (3) Output State...
Page 600: Total Rng Shutdown: Reset Rng Module
Power Management User Services Figure 23. Partial RNG Shut Down Input system clock Clock and (OCP) reset module cutted (2) OCP clock RINGS oscillators generator External OCP Clock disable (1) clocks ULPD Output State registers machine Input registers ARM926EJS RNG module OMAP 5912 Total RNG Shutdown: Reset RNG Module If an application no longer needs the RNG functions and needs to go into deep...
Page 601: Externals Clocks
EMIFS CONFIG_REG Bit 2, PWD_EN EMIFF SDRAM_CONFIG_2 Bit 2, SD_AUTO_CLK OMAP5912 Peripherals Autogating Table 49 lists the OMAP5912 peripherals that provide the autogating clock feature along with the relevant bit register to enable or disable the feature. SPRU753A Power Management...
Page 602: Mgs3/Dsp Autogating
Power Management User Services Table 49. OMAP5912 Peripherals With Clock Autogating Enable Feature Module Register Name Autogating Enable Bit (Register Field) 32-kHz watchdog WD_SYSCONFIG Bit 0, AutoIdle Secure watchdog WD_SYSCONFIG Bit 0, AutoIdle RNG_MASK Bit 0, AutoIdle DES3DES DES_MASK Bit 0, AutoIdle...
Page 603: Ulpd Power Modes Management
The ULPD provides system reference used by all clock domains. The ULPD internal state machine provides three system power modes: awake, big sleep, and deep sleep. These three modes determine global clock activity and overall consumption in OMAP5912. Idle states are defined for each clock domain or subdomain. SPRU753A...
Page 604: Ulpd Mode Descriptions
Standby wait for interruption signal received from the ARM926EJS processor.This signal is generated from specific MPU instruction decoding (software running). Idle request signals sent to all OMAP5912 clock domains Idle acknowledge signals from all OMAP5912 clock domains Wake-up signal (from external or internal requests) The different clock requests to the ULPD are described in Table 4.
Page 605 Power Management User Services Figure 24. OMAP5912 Shutdown Request Management Standby wait for interruption signal (1) ARM926EJS MPU (CP15) instruction Wake up interrupt signal Standby decoded Chip idle Control request (2) External idle x request registers clocks, cut (6) OMAP5912...
Page 606: Control Of External Clock And Voltage Supplies
Power Management User Services Figure 25. OMAP5912 Wake-Up Management Standby wait for interruption signal deassertion (4) ARM926EJS MPU (CP15) Instruction Wake up interrupt signal (3) Standby decoded Chip idle Control request (2) External idle x request registers clocks, on (2)
Page 607: Transitions Between Ulpd Modes
Transitions Between ULPD Modes Figure 27 describes the transition flow between the ULPD modes. Figure 27. Transition Flow BIG SLEEP AWAKE DEEP SLEEP OMAP5912 T0: Power up T1: Wake-up request from OMAP3.2 or from peripherals or after power up context SPRU753A Power Management...
Page 608: Power Domain Management
The RTC power domain supplies only real-time clock functions and associated reset controls. The user must control the ON_OFF signal during MPU and DSP domain switch-off and switch-on. Figure 28 describes the OFF state of OMAP5912, and Figure 29 describes the ON state. Power Management SPRU753A...
Page 609 Power Management User Services Figure 28. OMAP 5912 State OFF Very low consumption embedded real time clock running. External 32-kHz clock CVDDRTC domain supplied On/Off signal low domain No consumption domain OMAP5912 off No consumption SPRU753A Power Management...
Page 610: Dsp Domain Management
The assumption for OMAP5912 is that the power domains are connected exclusively to external power supplies (not necessarily dedicated). No e-LDO and no power switch are implemented in OMAP5912 to supply the MPU and DSP domains. When the DSP is in isolation mode, it is possible to cut its dedicated power supplies.
Page 611: Dynamic Voltage Scaling
Reset of this bit is done upon power up reset only (PWRON_RESET). Dynamic Voltage Scaling To minimize the leakage current when OMAP5912 is in deep sleep mode, decrease the external supply voltages once the deep sleep state is validated. The dynamic voltage scaling (DVS) feature enables the operation at reduced clock frequency when the external supply voltages are low.
Page 612: External Clock Mode
Dynamic Voltage Scaling Figure 30. Behavior of LOW_PWR Signal ULPD state Awake... Deep sleep Setup Big sleep... big sleep timer awake LOW_POWER 1.5 V 1.1 V ULPD setup timer delays deep sleep to big sleep/awake transition while the regulator ramps from 1.1 V to 1.5 V. 4.1.2 External Clock Mode The LOW_PWR signal is used in external clock mode.
Page 613: Low Voltage With Chip Running At Reduced Clock Frequencies
The power state transition of the MPU domain is controlled by software and hardware. The hardware part is composed mainly of the ULPD module FSM, which performs automatic transition between some of the MPU domain states. Table 52 lists the eight possible system power modes for OMAP5912. SPRU753A Power Management...
Page 614 On or Off OFF MODE Sleep state Sleep state On or Off The possible MPU system (ARM926EJS, TC, DMA, and memory interfaces—all OMAP5912 peripherals) states are described in Table 53. Table 53. MPU Domain States CLOCKS OMAP3.2 MPU and Peri- Power OMAP3.2...
Page 615: Omap5912 Power Mode Transitions
State retention is ensured when the DSP subsystem is in active, inactive, and pending states. In sleep state, there is no state retention. OMAP5912 Power Mode Transitions Figure 33 describes the OMAP5912 power mode transitions. Note that the initial state is state 0 (the only shaded state). SPRU753A Power Management...
Page 616 OMAP5912 Power Modes Figure 33. Power Mode Transitions MPU and MPU and active pending MPU active inactive MPU active Power up DSP sleep reset or wake-up inactive event DSP sleep MPU and MPU and inactive DSP sleep pending DSP sleep 1) DSP wake-up from inactive state Wake-up is automatically handled by the OMAP3.2 CLKRST module upon...
Page 617 OMAP5912 Power Modes DSP clock subdomains (CLKM2) (these belong to the MPU power domain and must be requested by the MPU). e) The DSP masks/unmasks interrupts in the DSP interrupt handler to ensure a wake-up path. The DSP executes the IDLE instruction.
Page 618 OMAP5912 Power Modes 4) DSP wake-up from sleep state In this case, the wake-up is handled entirely by the MPU software. There is no wake-up path through DSP interruptions. a) The MPU sets the GPIOs that control the external analog switch to power on the DSP domain.
Page 619 OMAP5912 Power Modes c) The MPU programs the IDLDPLL_ARM and IDLIF _ARM bits of ARM_IDLECT1 to allow TC and DPLL to go into idle mode. d) The MPU programs the MPU interrupt handlers to mask/unmask interrupts and ensure the wake-up path.
Page 620 OMAP5912 Power Modes The MPU programs the ULPD registers SETUP_ANALOG_CELL2 and SETUP_ANALOG_CELL3 with appropriate stabilization time for the external regulator and the oscillator. The MPU executes the STANDBYWFI instruction. k) All OMAP MPU and TC clock domains are automatically shutdown by the CLKRST module.
Page 621: Omap5912 Power Management Software User Guide
The MPU and TC clocks restart automatically. 9) The OMAP5912 chip to sleep state transition For OMAP5912 the MPU domain sleep state is not a true domain state in the sense that it cannot be entered or exited without the intervention of another device.
Page 622 OMAP5912 Power Management Software User Guide 15) Configure the ARM_IDLECT3 register to turn off the TC2, TC1, L3OCP clocks when the MPU enters idle state: Command WR32 0xFFFE CE24 0x0000 FFFF 16) Configure the DSP_IDLECT1 register to turn off GPIO, internal timer,...
Page 623 95 low voltage with chip shut down 93 Reduced clock frequency 22 Leakage current management 21 Low voltage operation 22 Low voltage with chip down 93 Low voltage with chip running 95 Static clock management 72 SPRU753A OMAP5912...
Page 624 18 ULPD power modes management 85 interrupt generation 50 ULPD registers 50 leakage current management 21 ULPD reset inputs 45 low transitions between power modes 23 low voltage at reduced clock frequency 22 ULPD setup counters 18 OMAP5912 SPRU753A...
Page 625 OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support Reference Guide Literature Number: SPRU755B October 2004...
Page 626 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 627 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments Documentation that describes the OMAP5912 device, related peripherals, and other technical collateral, is available in the OMAP5912 Product Folder on TI’s website: www.ti.com/omap5912. Trademarks OMAP and the OMAP symbol are trademarks of Texas Instruments.
Page 628 ........... . OMAP5912...
Page 629 ........DMA LCD Bottom Address B2 Registers ....... SPRU755B OMAP5912...
Page 630 4.24.9 DMA Operation in Power-Down Mode ........OMAP5912 SPRU755B...
Page 631 ......... . SPRU755B OMAP5912...
Page 632 DMA Software Compatible Register (DMA_GSCR) ....... . . OMAP5912 SPRU755B...
Page 633 DMA LCD Top Address B1 U Register (TOP_B1_U) ....... SPRU755B OMAP5912...
Page 634 ..........Channel Element Number Registers (DMA_CEN0...DMA_CEN5) ....OMAP5912 SPRU755B...
Page 635 Channel Destination Frame Index Registers (DMA_CDFI0...DMA_CDFI5) ... . DSP DMA DMA_CCR.AUTOINIT, END_PROG and REPEAT Bit Effects ... . . SPRU755B OMAP5912...
Page 636 ............OMAP5912...
Page 637: Dma Overview
The system DMA can support up to 31 hardware DMA requests. The DSP DMA supports 19 hardware DMA requests. In OMAP5912, up to 56 different hardware DMA requests can be generated by MPU and shared peripherals. An embedded crossbar, called MPU GDMA handler, allows mapping any of these 56 requests to any of 31 the system DMA request.
Page 638 System DMA The default configuration after reset ensures compatibility with the previous OMAP5912 generation. Programmers have flexibility to remap up to 31 requests according to the application task requirements. Table 1 describes the mapping between MPU and shared peripherals DMA requests and the MPU GDMA handler inputs.
Page 639 GDMA Handlers Table 1. MPU GDMA Handler Mapping MPU GDMA Handler Input Line Peripheral Request REQ1 MCSI1 TX REQ2 MCSI1 RX REQ3 C RX REQ4 C TX REQ5 External DMA request 0 REQ6 External DMA request 1 REQ7 µWire TX REQ8 McBSP1 DMA TX REQ9...
Page 640 GDMA Handlers Table 1. MPU GDMA Handler Mapping (Continued) MPU GDMA Handler Input Line Peripheral Request REQ30 USB W2FC TX1 REQ31 USB W2FC TX2 REQ33 SPI TX REQ34 SPI RX REQ38 CMT-APE TX (channel 0) REQ39 CMT-APE RV (channel 0) REQ40 CMT-APE TX (channel 1) REQ41...
Page 641: Mpu Gdma Handler Configuration
GDMA Handlers Table 1. MPU GDMA Handler Mapping (Continued) MPU GDMA Handler Input Line Peripheral Request REQ62 Unconnected REQ63 Unconnected REQ64 Unconnected 2.1.1 MPU GDMA Handler Configuration The mapping of the system DMA requests is done through the GDMA registers (shown in Table 2), which are implemented in the configuration module.
Page 642 GDMA Handlers Table 3. Functional Multiplexing MPU DMA A Register (FUNC_MUX_MPU_DMA_A) Base Address = 0xFFFE 1000, Offset Address = 0xEC Name Function Reset 31:30 RESERVED Reserved. 29:24 CONF_ARM_DMA_REQ_05 Writing value n in this register maps DMA 0x04 request source n+1 to system DMA controller DMA_REQ(5).
Page 643 GDMA Handlers Table 4. Functional Multiplexing MPU DMA B Register (FUNC_MUX_MPU_DMA_B) Base Address = 0xFFFE 1000, Offset Address = 0xF0 Name Function Reset 31:30 RESERVED Reserved. 29:24 CONF_ARM_DMA_REQ_10 Writing value n in this register maps DMA 0x09 request source n+1 to system DMA controller DMA_REQ(10).
Page 644 GDMA Handlers Table 5. Functional Multiplexing MPU DMA C Register (FUNC_MUX_MPU_DMA_C) (Continued) Name Function Reset 17:12 CONF_ARM_DMA_REQ_13 Writing value n in this register maps DMA 0x0C request source n+1 to system DMA controller DMA_REQ(13). n is between 0 and 55. 11:6 CONF_ARM_DMA_REQ_12 Writing value n in this register maps DMA...
Page 645 GDMA Handlers Table 7. Functional Multiplexing MPU DMA E Register (FUNC_MUX_MPU_DMA_E) Base Address = 0xFFFE 1000, Offset Address = 0xFC Name Function Reset 31:30 RESERVED Reserved. 29:24 CONF_ARM_DMA_REQ_25 Writing value n in this register maps DMA 0x18 request source n+1 to system DMA controller DMA_REQ(25).
Page 646: Dsp Gdma Handler
DSP DMA request. The default configuration from reset ensures compatibility with the previous OMAP5912 generation. Programmers have the flexibility to remap up to 19 requests according to the application task requirements. See Figure 2 for a description of the DSP GDMA handler and Table 10 for DSP GDMA mapping.
Page 647 GDMA Handlers Figure 2. DSP GDMA Handler OMAP5912 MPU and shared peripherals REQ1 REQ28 OMAP5912 configuration registers MPU GDMA handler REQ_01 REQ_19 System DMA Table 10. DSP GDMA Mapping DSP GDMA Handler Input Line Peripheral Request REQ1 MCSI1 TX REQ2...
Page 648: Dsp Gdma Handler Configuration
GDMA Handlers Table 10. DSP GDMA Mapping (Continued) DSP GDMA Handler Input Line Peripheral Request REQ18 UART3 TX REQ19 UART3 RX REQ20 CMT-APE TX (channel 1) REQ21 CMT-APE RV (channel 1) REQ22 CMT-APE TX (channel 2) REQ23 CMT-APE RV (channel 2) REQ25 SPI TX REQ26...
Page 649 GDMA Handlers Table 12. Functional Multiplexing DSP DMA A Register (FUNC_MUX_DSP_DMA_A) Base Address = 0xFFFE 1000, Offset Address = 0xD0 Name Function Reset 31:30 RESERVED Reserved 29:25 CONF_DSP_DMA_REQ_06 Writing value n in this register maps DMA 0x05 request source n+1 to DSP DMA controller DMA_REQ(6).
Page 650 GDMA Handlers Table 13. Functional Multiplexing DSP DMA B Register (FUNC_MUX_DSP_DMA_B) Base Address = 0xFFFE 1000, Offset Address = 0xD4 Name Function Reset 31:30 RESERVED Reserved 29:25 CONF_DSP_DMA_REQ_12 Writing value n in this register maps DMA 0x0B request source n+1 to DSP DMA controller DMA_REQ(12).
Page 651 GDMA Handlers Table 14. Functional Multiplexing DSP DMA C Register (FUNC_MUX_DSP_DMA_C Base Address = 0xFFFE 1000, Offset Address = 0xD8 Name Function Reset 31:30 RESERVED Reserved 29:25 CONF_DSP_DMA_REQ_18 Writing value n in this register maps DMA 0x11 request source n+1 to DSP DMA controller DMA_REQ(18).
Page 652: System Dma
System DMA System DMA The system DMA is designed to off-load the block data transfer function from the MPU. The OMAP 3.2 system DMA controller consists of: Sixteen logical channels plus one LCD logical channel Seven physical ports plus one for configuration Three physical channels plus one LCD dedicated physical channel The ports are connected to the OCP-T1 and OCP-T2 targets, the external memory, the TIPB bridge, the MPUI, and one dedicated port connected to an...
Page 653 System DMA Two choices of logical channel arbitration of physical resources: round robin or fixed Two levels of logical channel priority Constant fill Transparent copy Rotation 0°, 90°, 180°, and 270° Seven ports enabling: Memory-to-memory transfers Peripheral-to-memory transfers Memory-to-peripheral transfers Peripheral-to-peripheral transfers Binary backward-compatible by default configuration Up to four logical channels active in parallel...
Page 654: Functional Description
System DMA Figure 3. System DMA Controller Simplified Block Diagram TIPB Memory interface TIPB config port Logical channel arbitration Data bus Channel control Logical channel interleaving Port control bus EMIFS I/F P Ch-2 Logical channel prefetch Logical channel linking control EMIFS Arbiter Memory access control...
Page 655: Logical Channel Types
System DMA 3.1.1 Logical Channel Types The OMAP system DMA is based on logical channels (LChs). Each generic LCh can be configured to one of four different logical channel types; the dedicated LCD LCh can only be configured to LCh type D. Logical channel types (LCh types) supported are: LCh-2D for nonsynchronized transfers (memory transfers, 1D and 2D) LCh-P for synchronized transfers (mostly peripheral transfers)
Page 656: Omap 3.2 System Dma Instances
System DMA Table 16. Summary of Features Per Logical Channel Type (Without LCh-D) Supported Transfer Features LCh-2D LCh-P LCh-PD LCh-G (2D) (PD) LCh Control Transfer type Synchronized √ √ √ √ Two levels of priority √ √ √ √ Preemption at element boundary √...
Page 657: Synchronized Channel
System DMA The fourth channel, PCh-D, is specifically designed for transfers to the display and can only be used by the dedicated LCh-D. LCh-D must always be configured as type LCh-D. Table 17. Associated Physical Channels Per Logical Channel Type LCh-Type PCh Assigned LCh-2D...
Page 658 System DMA Each time a DMA request is received for a synchronized channel, the logical channel is activated and a block of data is transferred when a physical channel is assigned to it. This block of data can be: An element A complete element, which is defined by Data_type.
Page 659: Physical Ports
System DMA To configure an LCh to transfer one block per DMA request: 1) Configure the element size as described above. 2) Configure the element number as described above. This represents the number of elements sent per frame. 3) Configure the frame number as described above. This represents the number of frames sent per block.
Page 660 System DMA TIPB configuration interface: Used by the MPU to control/configure the system DMA. Cannot be used as source or destination in a DMA transfer. External slow memory interface (Flash/ROM): DMA accesses can be either single (8/16/32-bit) or burst (4x32-bit). If burst access is used and data packets are not 16-byte aligned, then single accesses (8/16/32-bit) are performed.
Page 661: Port Channel Scheduling
System DMA Table 19. Possible Data Transfer EMIFS EMIFF OCP-T1 OCP-T2 TIPB MPUI Bridge EMIFS EMIFF OCP-T1 OCP-T2 TIPB bridge MPUI † Used for the OMAP internal LCD controller. The port to use for source respective destination is configured in the channel source destination parameters register, DMA_CSDP.
Page 662: Logical Channel Scheduling
System DMA The system DMA port arbiters use a round robin scheme, but they are also dependent on the LCh priority. For more information about LCh priority, see the section on Logical Channel Priorities. The arbiters use the following scheme each time the previous DMA port access has finished: 1) Service all high-priority PChs using a round robin scheme.
Page 663: Logical Channel Scheduling Scheme
System DMA Logical Channel Scheduling Scheme Each physical channel can only serve one logical channel at a time. If several logical channels are active and waiting to be served, they are interleaved based on an arbitration scheme in a TDMA manner. The supported arbitration schemes are: Round robin scheduling Fixed scheduling from low LCH ID to high LCH ID...
Page 664: Logical Channel Interleaving For Synchronized Transfers
System DMA 3.1.7 Logical Channel Interleaving For Synchronized Transfers LCh Types Supporting this Feature LCh Types Supporting this Feature √ √ Logical channel interleaving is a term used when more than one synchronized channel shares the same physical channel. A synchronized channel is only active and requesting access to a physical channel when a DMA request is received.
Page 665: Linking Logical Channels
System DMA 3.1.8 Linking Logical Channels LCh Types Supporting This Feature LCh Types Supporting This Feature √ √ √ √ Software can configure DMA logical channels to an LCh chain. To configure and start a linked LCh chain: 1) To link the LChs, configure the NEXTLCH_ID bit in the logical channel link control register DMA_CLNK_CTRL to indicate the next logical channel to be enabled as soon as the current logical channel has finished the transfer.
Page 666 System DMA Constraint 2: It is the software’s responsibility to make sure that only the head of chained logical channel is enabled. Undefined effects occur if the software enables a logical channel that is inside a chain. Constraint 3: It is the software’s responsibility to ensure the chained logical channels have the same priority level;...
Page 667: Logical Channel Preempting
System DMA 3.1.9 Logical Channel Preempting LCh Types Supporting this Feature LCh Types Supporting this Feature √ √ √ A logical channel can be preempted on the element boundary, so that the current element and any ongoing bursts are fully transferred before the channel gets preempted.
Page 668: Addressing Modes
System DMA 3.1.10 Addressing Modes An addressing mode is an address computation algorithm that a DMA channel uses to find where to access data. The system DMA supports four types of addressing modes: Constant index mode Post-incremented mode Single-indexed (element index) mode Double-indexed (element and frame index) mode Based on LCh types, the summary of addressing modes is as follows: Table 20.
Page 669: Data Alignment
System DMA An element (data type) can be: 8-bit scalar data, s8 (which means that ES = 1) 16-bit scalar data, s16 (which means that ES = 2) 32-bit scalar data, s32 (which means that ES = 4) To set up a channel for a transfer, the software must program two addressing modes: The source addressing mode, source index size The destination addressing mode, destination index size...
Page 670: Constant Addressing Mode
System DMA In summary, the general constraints are: Start address (SA), Element_Index (EI), and Frame_Index (FI) must be aligned on data type (ES): mod ES= (FI-1) mod ES= (EI-1) mod ES= Constant Addressing Mode Address remains constant for each element to be transferred. A(n+1) = A(n) where: A(n): Byte address of the element n within the transfer.
Page 671: Single-Indexed Addressing Mode
System DMA Figure 6. Post-Incremented Addressing Mode Memory Accesses Memory Byte @ addr 00 Element n Element size (can be 1, 2, 4) Byte @ 01 Frame m Byte @ 02 Block (full data transfer, BSi) Element n+1 Byte @ 03 Byte @ 04 Element n+2 Byte @ 05...
Page 672: Single-Indexed Addressing Mode Memory Accesses
System DMA Figure 7 illustrates how the memory accesses are performed if a LCh is configured with single indexed addressing mode and: Starting address: 00 Element size: 2 (16 bits) Element number: 2 Element index: 3 Frame number: 2 Frame index: Ignored Figure 7.
Page 673: Double-Indexed Addressing Mode
System DMA Double-Indexed Addressing Mode Address is incremented by element size and a frame index if the end of the current frame is reached. Address is incremented by element size and an element index if the end of the current element is reached but the end of frame is not reached.
Page 674: Double-Indexed Addressing Mode Memory Accesses
System DMA Figure 8 illustrates how the memory accesses are performed if an LCh is configured with double-indexed addressing mode and: Starting address: 00 Element size: 2 (16 bits) Element number: 2 Element index: 3 Frame number: 2 Frame index: 5 Figure 8.
Page 675: Data Packing And Bursting
System DMA Note: For all addressing modes, independent element and frame indexing were not supported for OMAP 3.0 and 3.1. The EI and FI configuration is depen- dent on the OMAP3_1_Compatible_Disable bit in the DMA_CCR register. If DMA_CCR[OMAP3_1_Compatible_Disable]= 0: EI(source) = EI(destination) = DMA_CSEI register FI(source) = FI(destination) = DMA_CSFI register If DMA_CCR[OMAP3_1_Compatible_Disable] = 1: EI(source) = DMA_CSEI register...
Page 676 System DMA Burst 4x32 bits if bursting is enabled and the accessed source or destination port supports it. Software can enable or disable bursting with the bit-fields SRC_BURST_EN and DST_BURST_EN in the DMA_CSDP register. These bit-fields are ignored if the accessed port does not support bursting and hence, result in single accesses.
Page 677 System DMA All elements must be transferred continuously within a frame. That means that it cannot be synchronized on element boundary, and if single/dual-indexed addressing mode is used, element index (EI) must be set to 1. No packing or bursting can be done over frame boundary. It does not help to set frame index FI_ to 1.
Page 678 System DMA Another sort of packing groups bytes or word16 accesses within an element. This is always done if the LCh is configured as such. Packing within an element is done if the access types are smaller than the element sizes (data_type). For instance, if the data_type is set to s32 but the source target port only supports 16 bits, then two consecutive word16 source accesses are packed to build the word32 element.
Page 679 System DMA Table 22. Channel Data Block to Transfer Address Byte 0 Byte 1 Byte 2 Byte 3 element 2,5 element 2,4 element 2,3 element 2,2 element 2,1 element 1,5 element 1,4 element 1,3 element 1,2 element 1,1 The computed addresses and access type are: Table 23.
Page 680 System DMA If the frame size is increased by doubling the element size, EN = 10, the example is as follows (assumed that the targeted source support 4x32 bits burst): A logical channel is set up for a transfer with the following parameters for its source: Number of frames in the block: FN = 2 elements.
Page 681: Interrupt Generation
System DMA Table 25. Channel Addresses and Access Types Frame Element Address Number j Number i [byte] Access Access Type 16 bits 4x32 bits 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits 16 bits End of transfer In this example the first word16 is not packed to word32 because the address is not aligned on word32.
Page 682 System DMA Time-out error: An access error occurred in the transfer to the source or the destination, enabled with bit TOUT_IE in register DMA_CICR. The countdown values are configured at the source and destination ports. No countdown value can be specified in the system DMA. Note: Configure the interrupt(s) to be generated for each generic LCh in the chan- nel interrupt control register (DMA_CICR).
Page 683: System Dma Interrupt Mapping
System DMA When a status event occurs and the corresponding interrupt enable bit is enabled, the following happens: The status register bit is activated. An interrupt is generated. No new interrupts can be generated until the status register is read and thereby cleared.
Page 684: System Idle Request
System DMA All internal clocks are in idle mode, disabled, when the following is fulfilled: 1) Clock_Autogating_on = 1 in DMA_GCR. 2) No nonsynchronized LChs are enabled. 3) Either no synchronized LChs are enabled, or synchronized LChs are enabled but no DMA request is received or pending. The system DMA wakes up if software enables a new LCh or if a DMA request is received.
Page 685: Dma Debug State
System DMA 3.1.14 DMA Debug State During debug mode the MPU can send a request to suspend the DMA. This is useful if, for instance, the MPU is halted by a breakpoint. How the system DMA responds to this request is controlled by software by configuring the FREE bit in the DMA global control register, DMA_GCR.
Page 686 System DMA Figure 9. 2-D Transparent Color Block Diagram 2-D graphic transparent color block diagram Source element Destination element Match Match No write No write Color key This feature is enabled by setting the TRANSPARENT_COPY_ENABLE bit in the channel control 2 register, DMA_CCR2. If this bit is enabled, the DMA color parameter registers, DMA_COLOR_L and DMA_COLOR_U, are used to specify the color key.
Page 687 System DMA This feature is enabled by setting the bit Constant_Fill_Enable in the channel control register 2, DMA_CCR2. If this bit is enabled, the register DMA color parameter, DMA_COLOR_L and DMA_COLOR_U, is used to specify the color key. If the data type, ES, is 8 or 16 bits, only the DMA_COLOR_L register is used; if the data type is 32 bits, register DMA_COLOR_U is also used.
Page 688 System DMA To enable the new features introduced beyond OMAP 3.1, the following configuration register bits must be configured: OMAP 3_1_MAPPING_DISABLE in register DMA_GSCR OMAP3_1_COMPATIBLE_DISABLE in register DMA_CCR/DMA_LCD_CCR LCh register bit that enables/disables the OMAP 3.2 programming model. Table 26. Summary Table of Different Compatibility Modes LCh Register Bit Global Register Bit OMAP3_1com-...
Page 689 System DMA Autoinitialization of Logical Channels In OMAP 3.0/3.1 compatible mode, autoinitialization is supported. If a logical channel is autoinitialized, then the logical channel is automatically enabled itself again when a transfer is ended. A new or old logical channel configuration register set is loaded, and a new block of data is transferred.
Page 690: Dma Packed Channel Status Register For Compatible Mode
System DMA To control the mappings: OMAP 3.2 Mapping: DMA_CCR.OMAP3_1_Mapping_Disable = 1 OMAP 3.1 Mapping: DMA_CCR.OMAP3_1_Mapping_Disable = 0 See the Multimedia Processor Interrupts Reference Guide (SPRU757) for more details about interrupts. Table 28. Interrupt Mapping per LCh for Both Compatible Modes Interrupt Line OMAP 3.2 Mapping OMAP 3.1 Mapping...
Page 691 System DMA LCD Channel 3.2.1 Display Logical Channel The display logical channel, LCh-D, transfers data to the LCD controller from a video block buffer stored in memory. In the OMAP 3.2 system, the memory source for the transfer can be Test RAM (OCP-T1), or EMIFF. These transfers can be arranged to have the source in one or two blocks.
Page 692 System DMA Separate element/frame index and number of elements between the two buffers are also supported in the dual-block mode. The LCD channel sends the read request to the relevant port, defined by the lcd_source_port bit in the DMA LCD control register (DMA_LCD CTRL) just as the destination port is selected by the lcd_destination_port in the same register.
Page 693 System DMA Source Address and Block Size Alignment On the destination side, the accesses are fixed to 32 bits for external LCD controller and 16 bits for OMAP LCD controller. There is no address alignment because the LCD controller does not use addresses to access data from the LCD channel.
Page 694 System DMA Element_counter_B2: Counter that is (re)initiated with the number of ele- ments per frame inside block 2. Decreased by one at each element trans- ferred. Initial value EN_B2 is configured in register DMA channel element number, DMA_CEN. Frame_counter_B1: Counter that is (re)initiated with the number of frames inside block 1.
Page 695 System DMA When block 1 is active: A(0) = TB1. A(n+1) = A(n) + ES_B1 until the end of block 1. Then, when A(n) reaches BB1, A(n+1) = TB2: block 2 becomes active. When block 2 is active: A(n) = TB2. A(n+1) = A(n) + ES_B2 until the end of block 2.
Page 696 System DMA A(n) is incremented in this way until the end of block 2. Then, when A(n) reaches BB2, A(n+1) = TB1: block 1 becomes active again. Note: Stride_EI_B1/2 = 1 (equivalent to EI_B1/2 = 1) give consecutive element ac- cesses, hence the same behavior as with the Post_Incremented addressing mode.
Page 697 System DMA A(n+1) = A(n) + ES_B1 + (FI_B1 – 1) where FI_B1 = ((Stride_FI_B1 – 1) * ES_B1) + 1 When A(n) reaches BB1, A(n+1) = TB2: block 2 becomes active. When block 2 is active: A(0) = TB2A. A(n+1) = A(n) + ES_B2 + (EI_B2 –...
Page 698 System DMA 3.2.4 DMA LCD Channel Rotation This DMA LCD channel supports four types of rotation: 0°, 90°, 180°, and 270°, by using the double indexed addressing mode in LCD channel source port. This feature allows the use of display screens that are not oriented as they were designed.
Page 699 System DMA Table 30. Autoinitialization Bits Summary for LCD Channel in Noncompatible Mode Auto_init Repeat end_prog Autoinitialization Behavior No autoinitialization. Don’t It waits until enable = 1 to enable the LCD logical channel, and loads the Don’t care care physical LCD channel with its programming register set. However, the LCD logical channel is active only when the LCD controller enables it.
Page 700 System DMA 3.2.7 LCD Channel Usage Restrictions Exclusive Blocks The hardware design does not detect any overlap between two block buffers; that is, the start and stop addresses of each buffer must represent two different physical parts into the memory. In dual-block mode, the top address of the second block must be greater (and not equal to) than the bottom address of the first block.
Page 701 System DMA Step 1: Registers are set as: DMA_LCD_CTRL BLOCK_MODE = 0 (one block) BLOCK_IT_IE = 1 BUS_ERROR_IT_IE = 1 LCD_SOURCE_PORT = 0 (SDRAM) DMA_LCD_TOP_B1_U = 0x000B DMA_LCD_TOP_B1_L = 0x0000 DMA_LCD_BOT_B1_U = 0x000B DMA_LCD_BOT_B1_L = 0x00DE DMA_LCD_TOP_B2_U = irrelevant DMA_LCD_TOP_B2_L = irrelevant DMA_LCD_BOT_B2_U = irrelevant DMA_LCD_BOT_B2_L = irrelevant Step 2: The transfer starts when the enable (hardware) signal from the...
Page 702 System DMA Example 4. LCD Transfer: OCP_T1 (Test RAM) → LCD, Two Blocks Example 4 shows a transfer from two video blocks located in memory connected to the OCP_T1 port to the LCD controller. The size for the LCD display is 6 x 16 pixels with 16 bits per pixels. So the length of one video block is 6 x 16 x 2 (in bytes) + 32 bytes for the palette = 224 bytes.
Page 703 System DMA Figure 13. LCD Dual-Block Mode Transfer Scheme Frame buffer 0x0B 0000 Video frame 1 0x0B 00DE controller 0x0C 0000 Video frame 2 0x0C 00DE DMA_LCD_CTRL [4] = BLOCK_2_IT_COND = 1: end of block 2 is reached. The DMA restarts at the top address of block 1, and DMA_LCD_CTRL [4] is reset to be able to detect a next interrupt.
Page 704 System DMA A(n+1) = A(n) + ES_B1/2 if TB1/2 ≤ A(n+1) ≤ BB1/2 where: A(n) is the byte address of element n within the transfer. ES_B1/2 is block1/2 element size. TB1/2 is top address for block1/2 and BB1/2 is bottom address for block1/2.
Page 705 System DMA Table 31. Autoinitialization Configuration Bits Summary for LCD Channel in Compatible Mode Auto_init Repeat End_prog Autoinitialization Behavior At the end of the current transfer, the logical LCD channel immediately loads the physical LCD channel with its programming register set, when physical LCD channel is granted (end_prog = 1 allows loading the new context, Hardwired 1 Hardwired 1...
Page 706 System DMA Table 32. LCD Channel Register Mapping for OMAP 3.2 Respectively OMAP 3.0/3.1 Compatible Modes (Continued) Offset Register Mapping in OMAP 3.2 Register Mapping in OMAP Mapping Mode 3.0/3.1 Mapping Mode E3D0 DMA_LCD_TOP_B2_L DMA_LCD_BOT_B2_U E3D2 DMA_LCD_TOP_B2_U E3D4 DMA_LCD_BOT_B2_L E3D6 DMA_LCD_BOT_B2_U E3D8 DMA_LCD_SRC_EI_B1...
Page 707 System DMA Table 33. DMA Global Control Registers Base Address = 0xFFFE DC00 Name Description Offset DMA_GCR DMA global control 0x00 DMA_GSCR DMA software compatible 0x04 DMA_GRST Software reset control 0x08 DMA_HW_ID DMA version ID 0x42 DMA_PCh2_ID Physical channel 2 version ID 0x44 DMA_PCh0_ID Physical channel 0 version ID...
Page 708 System DMA Table 34. DMA Global Control Register (DMA_GCR) Base Address = 0xFFFE DC00, Offset = 0x00 Name Function Reset 15:5 RESERVED Reserved ROUND_ROBIN_DISAB DMA physical channel scheduler round robin scheduling disable: 0: DMA physical channel scheduler uses round robin scheduling scheme to schedule next available logical channel.
Page 709 System DMA Table 35. DMA Software Compatible Register (DMA_GSCR) Base Address = 0xFFFE DC00, Offset = 0x04 Name Function Reset 15:4 RESERVED Reserved OMAP3_1_MAPPING OMAP3.1 mapping disable DISABLE 0 = DMA compatible with OMAP 3.0/3.1 system DMA interrupt line mapping and logical channel configuration register address mapping (system DMA I/O space).
Page 710 System DMA Table 39. PCh-0 Version ID Register (DMA_PCh0_ID) Base Address = 0xFFFE DC00, Offset = 0x46 Name Function Reset 15:0 PCH0_ID DMA PCh-0 version ID number 0x0001 Table 40. PCh-1 Version ID Register (DMA_PCh1_ID) Base Address = 0xFFFE DC00, Offset = 0x48 Name Function Reset...
Page 711 System DMA Table 43. Global DMA Capability U Register 0 (DMA_ CAPS_0_U) (Continued) Base Address = 0xFFFE DC00, Offset = 0x4E Name Function Reset Overlap detection capability (not available in OMAP3.2): 0: PCh-G cannot do overlap detection. 1: PCh-G can do overlap detection. DBLTC Directional BLT capability (not available in OMAP3.2): 0: PCh-G cannot do directional BLT copy.
Page 712 System DMA Table 46. Global DMA Capability L Register 1 (DMA_CAPS_1_L) Base Address = 0xFFFE DC00, Offset = 0x54 Name Function Reset 15:2 RESERVED Reserved 1-bit palletized capability (not available in OMAP 3.2): 0: PCh-G cannot do 1-bit color expansion. 1: PCh-G can do 1-bit color expansion.
Page 713 System DMA Table 47. Global DMA Capability Register 2 (DMA_CAPS_2) (Continued) Base Address = 0xFFFE DC00, Offset = 0x56 Name Function Reset SSIAC Source single-index address capability: 0: Does not support single-index address mode in source port. 1: Supports single-index address mode in source port. SPIAC Source post-increment address capability: 0: Does not support post-increment address mode in source port.
Page 714 System DMA Table 48. Global DMA Capability Register 3 (DMA_CAPS_3) (Continued) Base Address = 0xFFFE DC00, Offset = 0x58 Name Function Reset Frame synchronization capability: 0: Does not support synchronization transfer on frame boundary. 1: Supports synchronization transfer on frame boundary. Element synchronization capability: 0: Does not support synchronization transfer on element boundary.
Page 715 System DMA Table 49. Global DMA Capability Register 4 (DMA_CAPS_4) (Continued) Base Address = 0xFFFE DC00, Offset = 0x5A Name Function Reset EDIC Event drop interrupt capability (request collision): 0: Does not support event drop interrupt generation capability. 1: Supports event drop interrupt generation capability. TOIC Time-out interrupt capability (time-out error): 0: Does not support time-out interrupt generation capability.
Page 716 System DMA Table 51 lists the logical channel configuration registers. Table 52 through Table 96 describe the register bits. Table 51. DMA Logical Channel Configuration Registers Base Address = FFFE D800 Name Description Offset † DMA_CSDP Channel source destination parameters 0x00 + (n*0x40) DMA_CCR Channel control register...
Page 717 System DMA Table 52. Channel Source Destination Parameters Register (DMA_CSDP) Base Address = 0xFFFE D800, Offset Address = 0x00 + n*0x40 Name Function Reset 15:14 DST_BURST_EN Destination burst enable DST_PACK Destination packing 12:9 Transfer destination 0000 SRC_BURST_EN Source burst enable SRC_PACK Source packing Transfer source...
Page 718 System DMA src: Transfer source A unique identifier is given to each port. This field identifies the port origi- nator of the transfer. OMAP Source Port 0000 EMIFF 0001 EMIFS 0010 OCP_T1 0011 TIPB 0100 OCP_T2 0101 MPUI Others Illegal (cause undefined effects) SRC_PACK: source packing The DMA ports can have a data bus width different from the type of data...
Page 719 System DMA Table 54. DMA Channel Control Register (DMA_CCR) Base Address = 0xFFFE D800, Offset Address = 0x02 + n*0x40 Name Function Reset 15:14 DST_AMODE Destination addressing mode 13:12 SRC_AMODE Source addressing mode END_PROG End of programming status bit OMAP_3_1_COMPATIB OMAP 3.0/3.1 channel compatibility control LE_DISABLE REPEAT...
Page 720 System DMA fs = 0 and bs = 1: An entire block is transferred each time a DMA_request is made. This block can be interleaved on the DMA port with other channel requests. fs = 0 and bs = 0: An element is transferred each time a DMA_request is made.
Page 721 System DMA Repeat = 1: When DMA channel is in autoinitialization mode and end_prog = 0, once the current transfer is complete, the channel automatically rein- itializes itself and starts a new transfer. Repeat = 0: When DMA channel is in autoinitialization mode and end_prog = 0, once the current transfer is complete, the channel automatically rein- itializes itself and starts a new transfer.
Page 722 System DMA DST_AMODE: Destination addressing mode This field is used to choose the addressing mode on the destination port of a channel. dst_amode = 00: Constant address dst_amode = 01: Post-incremented address dst_amode = 10: Single index (element index) dst_amode = 11: Double index (element index and frame index) Table 55.
Page 723 System DMA DROP_IE: Synchronization event drop interrupt enable (request collision) drop_ie = 1: The channel sends an interrupt to the processor if the channel transfer is synchronized on DMA requests and two successive DMA re- quests drop. This occurs when a new DMA request is made while the ser- vice of the previous one has not been finished yet.
Page 724 System DMA Table 56. DMA Channel Status Register (DMA_CSR) Base Address = 0xFFFE D800, Offset Address = 0x06 + n*0x40 Name Function Reset 15:7 RESERVED Reserved SYNC Synchronization status BLOCK End block (end of block) LAST Last frame (start of last frame) FRAME Frame (end of frame) HALF...
Page 725 System DMA SYNC: Synchronization status Set to 1 when a DMA request is made in a synchronized channel. When there is a TIPB read access to DMA_CSR register, this bit returns to zero. Sync = 1: Logical channel is servicing synchronized DMA request. Sync = 0: Logical channel is not servicing a synchronized channel, or DMA request has not been scheduled.
Page 726 System DMA Table 60. DMA Channel Destination Start Address Upper Bits Register (DMA_CDSA_U) Base Address = 0xFFFE D800, Offset Address = 0x0E + n*0x40 Name Function Reset 15:0 DSAU Destination start address, upper bits Destination start address, upper bits Upper bits for the source start address, expressed in bytes. The destina- tion start address is made of the concatenation of DMA_CDSA_U and DMA_CDSA_L.
Page 727 System DMA Channel source frame index Contains the channel source frame index, expressed as signed value in bytes, which is used to compute addresses when double indexed ad- dressing mode is used in DMA source port. Table 64. DMA Channel Source Element Index Register (DMA_CSEI) Base Address = 0xFFFE D800, Offset Address = 0x16 + n*0x40 Name Function...
Page 728 System DMA This register can be used to monitor the progress of a DMA transfer on channel destination port: It is a snapshot of the destination address generated by the channel destination address counter, which is scheduled in the channel destination port.
Page 729 System DMA Table 69. DMA COLOR Parameter Register (DMA_COLOR_L) Base Address = 0xFFFE D800, Offset Address = 0x20 + n*0x40 Name Function Reset 15:0 Channel BLT foreground color (LSW) This register can be used to provide parameter for DMA constant fill and transparent copy features.
Page 730 System DMA Table 71. DMA Channel Control Register 2 (DMA_CCR2) Base Address = 0xFFFE D800, Offset Address = 0x24 + n*0x40 Name Function Reset 15:3 RESERVED Reserved Block Synchronization Transparent copy enable Constant fill enable BS: Block synchronization This bit and the fs bit in the DMA_CCR register are used to program the way that a DMA_request is serviced in a synchronized transfer.
Page 731 System DMA Used to control logical channel linked queue. NEXTLCH_ID Defines the NEXTLCH_ID, which is used to build logical channel chaining queue. The LOGICAL_CHANNEL_I is enabled, after the current logical channel finishes transfer (i = 0-15). STOP_LNK: Disables the logical channel on channel linked queue. 1: The logical channel, defined by NEXTLCH_ID, is disabled, and EN- ABLE_LNK is disabled.
Page 732 System DMA 3.3.3 LCD Channel Dedicated Registers Table 74 lists the DMA channel dedicated registers. Table 75 through Table 96 describe the register bits. Table 74. DMA Logical Channel Configuration Registers Base Address = FFFE EC00 Name Description Offset † DMA_LCD_CSDP DMA LCD channel source destination 0xC0...
Page 733 System DMA Table 74. DMA Logical Channel Configuration Registers (Continued) Base Address = FFFE EC00 † Name Description Offset DMA_LCD_SRC_FN_B2 DMA LCD source frame number B2 0xE6 DMA_LCD_LCH_CTRL DMA LCD logical channel control 0xEA † Note: Some offsets are not in numerical order to facilitate the relationship between the upper and lower words of some regis- ters.
Page 734 System DMA Start_Address must be aligned on the boundary of the type of data moved. For example, if data_type is s32 the source start address must be aligned on a word32. If data_type is s8, source start_address can have any value. It is the software’s responsibility to make sure that start address is aligned with channel data_type.
Page 735 System DMA Table 76. DMA LCD Channel Control Register (DMA_LCD_CCR) (Continued) Name Function Reset OMAP3_1_Compatible_ OMAP3.1 channel compatibility control. disable REPEAT Repetitive operation. (Tie off = 1) AUTOINIT Autoinitialize at the end of the transfer. (Tie off = 1) ENABLE Enable transfer.
Page 736 System DMA Prio_0 : Channel priority Prio_0 = 1: The channel has the high-priority level. Prio_0 = 0: The channel has the low-priority level. Enable: This bit is used to enable/disable the transfer in the DMA LCD channel when OMAP external LCD controller is selected. Enable = 1: The transfer starts.
Page 737 System DMA OMAP3_1_COMPATIBLE_DISABLE: Omap3.1 channel compatibility control. This bit is used to set DMA LCD channel programming model. omap3_1_compatible_disable = 1: The LCD channel is in OMAP3.2 com- patible mode. omap3_1_compatible_disable = 0: The LCD channel is in OMAP3.1 com- patible mode.
Page 738 System DMA Table 77. DMA LCD Control Register (DMA_LCD_CTRL) (Continued) Base Address = 0xFFFE E300, Offset Address = 0xC4 Name Function Reset BUS_ERROR_IT_ Bus error interrupt condition. COND (read as 0) BLOCK_2_IT_COND Block 2 interrupt condition. BLOCK_1_IT_COND Block 1 interrupt condition. BUS_ERROR_IT_IE Buss error interrupt enable.
Page 739 System DMA BLOCK_1_IT_COND: status LCD channel bit. Users must write to this register to clear the status bits. 0: No end of block 1 interrupt detected. 1: End of block 1 interrupt detected. BLOCK_2_IT_COND: status LCD channel bit. Users must write to this register to clear the status bits.
Page 740 System DMA DMA LCD Top Address B1 Registers The LCD top address B1 registers are two 16-bit registers, which contain the start address for the video RAM buffer 1. The 32-bit address is obtained by the concatenation of the two word16 as described here: LCD_TOP_B1 = DMA_LCD_TOP_B1_U &...
Page 741 System DMA Table 81. DMA LCD Bottom Address B1 U Register (BOT_B1_U) Base Address = 0xFFFE E300, Offset Address = 0xCE Name Function Reset 15:0 LCD BOT address for block buffer 1 upper bits DMA LCD Top Address B2 Registers The LCD top address B2 registers are two 16-bit registers that contain the start address for the video RAM buffer 2.
Page 742 System DMA Note: The LSB of the word32 is equal to zero. Address of video buffer must always be even. Table 84. DMA LCD Bottom Address B2 L Register (BOT_B2_L) Base Address = 0xFFFE E300, Offset Address = 0xD4 Name Function Reset 15:1...
Page 743 System DMA LCD channel source frameindex for block 1 These registers contain the channel source frame index for video RAM buffer 1, expressed as a signed value in bytes, which is used to compute addresses when double-indexed addressing mode is used. Table 89.
Page 744 System DMA Table 93. DMA LCD Source Frame Number B1 Register (DMA_LCD_SRC_FN_B1) Base Address = 0xFFFE E300, Offset Address = 0xE4 Name Function Reset 15:0 LCD channel source frame number for block 1 LCD channel source frame number for block 1 Number of frames within a block (unsigned) for the video RAM buffer 1.
Page 745: Dsp Dma
DSP DMA System DMA / DSP DMA Used to control logical channel access. The OMAP_3.1_mode tie-off values are those values given to the bits in OMAP 3.1 compatible mode, because the DMA_LCD_CCR, DMA_LCH_CTRL, and DMA_LCD_CSDP registers do not exist in the compatible mode. These values are tied off/on in hardware. (For LCH_TYPE, the tie-off value is 0000).
Page 746 DSP DMA Figure 14. DSP DMA and Ports DSP 5-Port DMA MPU/DSP shared peripherals Mailbox TMS320C55x DSP Endianism MPU/DSP static conversion EMIF Internal shared memory 8 x GPTIMERS TMS320C55x buses DSP core I-cache UART1,2,3 MMCSDIO2 Memory McBSP2 Shared Private DARAM TIPB TIPB MPU/DSP...
Page 747: Dsp Dma Controller Features
DSP DMA DSP DMA Controller Features The DSP DMA controller has the following features: Operation independent of the MPU. Four standard ports, one for each data resource: DARAM, SARAM, external memory via EMIF, and peripherals via the shared TIPB bridge. An auxiliary port to enable certain transfers between the MPUI and memory.
Page 748 DSP DMA Data transfers among the SARAM, DARAM, EMIF, and PERIPH ports can occur in six independent DMA channels (see Section 4.2, Channels and Port Accesses). Transfers between the MPUI port and memory ports (SARAM, DARAM, and EMIF) occur on a unique seventh channel dedicated to MPU operations.
Page 749 DSP DMA Figure 15. Example of DMA Configuration SARAM DARAM EMIF Peripheral bus bridge MPUI P B C D E F P B C D E F P B C D E F IOD IOE SARAM port DARAM port EMIF port Peripheral MPUI port controller...
Page 750: Channels And Port Accesses
DSP DMA Channels and Port Accesses The DSP DMA controller has six paths, or channels, to transfer data among the four standard ports (for DARAM, SARAM, external memory, and peripherals). Each channel reads data from one port (the source) and writes data to that same port or another port (the destination).
Page 751: Channel Autoinitialization
DSP DMA The following registers immediately impact the DMA channel operation and must only be modified while the channel is disabled: DMA_CSDP DMA_CCR DMA_CICR DMA_CSR 4.2.1 Channel Autoinitialization Three control bits within the DMA_CCR register configure automatic reinitialization of the DMA channel (see Table 98): The AUTOINIT bit: If AUTOINIT is set, then under certain conditions the channel reinitializes at the end-of-block by copying the configuration registers into the working set.
Page 752: Mpui Access Configurations
DSP DMA Figure 17 shows the registers for controlling channel context. Figure 17. Registers for Controlling Channel Context Configuration registers Working registers (programmed by code) (used by DMA controller) DMA_CSDP DMA_CSDP copy DMA_CCR DMA_CCR copy Automatically copied DMA_CICR DMA_CICR copy when channel enabled DMA_CSR DMA_CSR copy...
Page 753: Service Chain
DSP DMA Figure 18. MPUI Access Configurations MPUI EXCL = 0 Port Read/Write Port Read/Write requests requests MPUI DARAM port DMA channels SARAM port External memory port Peripherals port Service Chain Each of the standard ports can arbitrate simultaneous access requests sent by the six DMA channels and the MPUI.
Page 754 DSP DMA The channels and the MPUI have a programmable priority level. Each channel has a priority bit in DMA_CCR for selecting a high priority or a low priority. The MPUI is assigned a high priority or a low priority with the MPUI_PRIO bit in DMA_GCR.
Page 755: Service Chain Example
DSP DMA 4.4.1 Service Chain Example Figure 20 shows a DMA service chain applied to the DARAM port, the external memory port, and the peripherals port. The service chain has the following programmed characteristics. A list of activity in the ports is provided after Figure 20.
Page 756 DSP DMA Figure 20. Service Chain Applied to Three DMA Ports Configuration for High-priority: 0, 2, 5 Disabled: 0, 3, 5 MPUI shares with channels the service chains Low-priority: 1, 3, 4, MPUI Enabled: 1, 2, 4 DARAM port: Only used by channel 2, channel 4, and MPUI MPUI Ch 0 Ch 2...
Page 757: Units Of Data
DSP DMA In this example Ch1: PERIPH -> External memory, Ch2: PERIPH -> DARAM, Ch4: DARAM -> Ext mem. Table 99. Activity Shown in Figure 20 Port This Port Arbitrates DARAM Write access requests from channel 2 Read access requests from channel 4 Read or write access requests from the MPUI External memory Write access requests from channel 1...
Page 758: Start Addresses In A Channel
DSP DMA Start Addresses in a Channel During a data transfer in a DMA channel, the first address at which data is read is called the source start address. The first address to which the data is written is called the destination start address. These are byte addresses. From the standpoint of the DMA controller, every 8 bits in memory or I/O space has its own address.
Page 759: Start Address In I/O Space
DSP DMA Figure 21. High-Level Memory Map for DSP Word addresses Byte addresses (Hexadecimal ranges) (Hexadecimal ranges) Memory 00 0000-00 005F 00 0000-00 00BF MMRs Main data page 0 00 0060-00 FFFF 00 00C0-01 FFFF Main data page 1 01 0000-01 FFFF 02 0000-03 FFFF Main data page 2 02 0000-02 FFFF...
Page 760: Updating Addresses In A Channel
DSP DMA Figure 22. High-Level I/O Map for DSP Word addresses Byte addresses (Hexadecimal range) I/O space (Hexadecimal range) 0000-FFFF 0 0000-1 FFFF Updating Addresses in a Channel During data transfers in a DMA channel, the DMA controller begins its read and write accesses at the start addresses you specify (as described in Section 4.6, Start Addresses in a Channel).
Page 761: Addressing Modes
DSP DMA 4.9.1 Addressing Modes Figure 23 illustrates the address index management. Figure 23. Memory Representation Block (full data transferred) (4 segments) byte @address 00 byte @ 01 Element size Element n byte @ 02 (Can be 1, 2, 4) byte @ 03 Ç...
Page 762: Constant Addressing Mode
DSP DMA The byte size of this data block is: BS = FN x EN x ES where: BS is the block size in bytes. FN is the number of frames in the block, 1 . FB . 65535. EN is the number of elements per frame, 1 . EN . 65535. ES is the number of bytes per element, ES .
Page 763: Post-Incremented Addressing Mode
DSP DMA 4.9.3 Post-Incremented Addressing Mode Address is always incremented by 1. a(0) =SA a(i) = a(i – 1) + 1, 1 . i . BS –1 where: a(i) is the address of the byte number i within the transfer. SA is the start address of the transfer.
Page 764: Data Packing
DSP DMA a(0) = SA a(i) = a(i – 1) + 1 if (I mod ES) = 0 and (i mod FS) ⎯0, 1 . i . BS – 1 a(i) = a(i – 1) + EI if (i mod ES) = 0 and (i mod FS) ⎯0, 1 . i . ℜS – 1 a(i) = a(i –...
Page 765: Bursting
DSP DMA Split a single word transfer into several byte accesses. This occurs when DMA port size is less than the size of the element type. For example, when the element size is programmed as 32 bits and the destination port is 16 bits wide, the transfer write operation is split into two 16-bit write operations.
Page 766 DSP DMA Frame index in bytes: FI = 13 Element index in bytes: EI = 1 Source start address: SA = 2 The source port is a 32-bit port with byte word16 and word32 access capability. Bursts are disabled. The memory block to transfer is as identified in Table 103 (element i, j is the element number j of frame i).
Page 767: Data Alignment
DSP DMA 4.12 Data Alignment During a transfer, all the addresses computed by the DMA must be aligned on the type of data transferred: If the data type is s8 (8 bits scalar data), addresses can have any value. If the data type is s16 (16 bits scalar data), addresses must be aligned on 16-bit word boundary (the least bit of the address is always 0).
Page 768: Read Synchronization Vs. Write Synchronization
DSP DMA 4.13.1 Read Synchronization vs. Write Synchronization When a DMA channel is configured for synchronization, the synchronization event is tied to the element read operation or the element write operation, depending on the source and destination ports. There are three general cases (see Table 105): Case 1: Source port is peripheral;...
Page 769: Checking The Synchronization Status
DSP DMA 4.14 Checking the Synchronization Status Each channel has a synchronization flag (synchronization) in its status register, DMA_CSR. When the synchronization event occurs, the DMA controller sets the flag (SYNCHRONIZATION = 1). The flag is cleared (SYNCHRONIZATION = 0) when the DMA controller has completed the first read access (transfer from source port to channel buffer) after receiving synchronization.
Page 770: Channel Interrupt
DSP DMA All interrupts generated by the DSP DMA controller are level-sensitive interrupts, that is, the interrupt line is held active low for two DSP clock cycles after the CPU reads the associated channel status register (see Table 106). Table 106. DMA Controller Operational Events and Associated Bits/Interrupts Operational Event Interrupt Enable Bit Status Bit...
Page 771: Time-Out Conditions
DSP DMA Figure 24. Triggering a Channel Interrupt Request DROP IE Á Á DROP event Á Á BLOCK IE Á Á BLOCK event Á Á Á Á FRAME IE Á Á Channel interrupt FRAME event Á Á Á Á HALF IE Á...
Page 772: Dma Transfer Latency
DSP DMA External memory port: A time-out counter in the external memory interface (EMIF) keeps track of how many cycles the external ready pin has been sampled low. The external memory map is divided into four memory spaces, each of which has a programmable time-out value up to 255 DSP cycles.
Page 773: Dma Power Reduction
DSP DMA The timing of synchronization events (if the channel is synchronized). The DMA controller cannot service a synchronized channel until the synchronization event has occurred. For details, see Section 4.13, Synchronizing Channel Activity. 4.20 DMA Power Reduction The DSP is divided into idle domains that can be programmed to be idle or active.
Page 774 DSP DMA Table 107. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 0 (Continued) DMA_CSR0 Channel 0 status 0C03h DMA_CSSA_L0 Channel 0 source start address, lower bits 0C04h DMA_CSSA_U0 Channel 0 source start address, upper bits 0C05h DMA_CDSA_L0 Channel 0 destination start address, lower bits 0C06h DMA_CDSA_U0...
Page 775 DSP DMA Table 107. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 1 (Continued) DMA_CSEI1 Channel 1 source element index 0C2Bh DMA_CSAC1 Channel 1 source address counter 0C2Ch DMA_CDAC1 Channel 1 destination address counter 0C2Dh DMA_CDEI1 Channel 1 destination element index 0C2Eh DMA_CDFI1 Channel 1 destination frame index...
Page 776 DSP DMA Table 107. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 3 (Continued) DMA_CICR3 Channel 3 interrupt control 0C62h DMA_CSR3 Channel 3 status 0C63h DMA_CSSA_L3 Channel 3 source start address, lower bits 0C64h DMA_CSSA_U3 Channel 3 source start address, upper bits 0C65h DMA_CDSA_L3 Channel 3 destination start address, lower bits...
Page 777 DSP DMA Table 107. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 4 (Continued) DMA_CSFI4 Channel 4 source frame index 0C8Ah DMA_CSEI4 Channel 4 source element index 0C8Bh DMA_CSAC4 Channel 4 source address counter 0C8Ch DMA_CDAC4 Channel 4 destination address counter 0C8Dh DMA_CDEI4 Channel 4 destination element index...
Page 778 DSP DMA Table 108. Global Control Register (DMA_GCR) Name Function Type Reset 31:4 Reserved AUTOGATING_ON DMA autoidle bit. Controls whether DMA circuits are automatically idled when DMA is inactive. 0: DMA clocks are free running. 1: Allows the DMA clocks to autoidle when inactive.
Page 779 DSP DMA Table 109. Global Time-Out Control Register (DMA_GTCR) Name Function Type Reset 31:2 DARAM_TE DARAM time-out enable 0: DARAM port time-out counter is disabled. 1: DARAM port time-out counter is enabled. SARAM_TE SARAM time-out enable 0: SARAM port time-out counter is disabled. 1: SARAM port time-out counter is enabled.
Page 780 DSP DMA 4.23 DMA Channel Configuration Registers The register bit descriptions in Table 111 through Table 125 are generic in that the register sets for each of the six DMA channels (0-5) are identical. Table 111. Channel Source Destination Parameters Registers (DMA_CSDP0...DMA_CSDP5) Name Function...
Page 781 DSP DMA Table 111. Channel Source Destination Parameters Registers (DMA_CSDP0...DMA_CSDP5) (Continued) Name Function Type Reset SRC_BURST_EN Source burst enable A burst in the DMA controller refers to four consecutive 32-bit accesses at a DMA port. SRC_BURST_EN determines whether the DMA controller performs a burst transfer at the source port of the channel.
Page 782: Data_Type Bit
DSP DMA 4.23.1 DATA_TYPE Bit DATA_TYPE: Defines the type of the data moved in the channel; used for endianism adaptation. 00b 8-bit The DMA controller makes 8-bit accesses at the source and at the destination of the channel. The source and destination start address- es have no alignment constraint, as follows: Start address: XXXX XXXX XXXX XXXXb (X can be 0 or 1).
Page 783 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) Name Function Type Reset 31:16 Reserved 15:14 DST_AMODE Destination addressing mode This field determines the addressing mode used by the DMA controller when it writes to the source port of the channel. 00: Constant address.
Page 784 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued) Name Function Type Reset 13:12 SRC_AMODE Source addressing mode This field determines the addressing mode used by the DMA controller when it reads from the source port of the channel. 00: Constant address. The same address is used for each element transfer.
Page 785 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued) Name Function Type Reset END_PROG End of programming bit. Each DMA channel has two sets of registers: configuration registers and working registers. When block transfers occur repeatedly because of autoinitialization (AUTO_INIT = 1), change the context for the next DMA transfer by writing to the configuration registers during the current block transfer.
Page 786 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued) Name Function Type Reset REPEAT Repeat condition bit. If autoinitialization is selected for a channel (AUTO_INIT = 1), REPEAT specifies one of two special repeat conditions: 0: Repeat only if END_PROG = 1. Once the current DMA transfer is complete, autoinitialization occurs only if the end of the programming bit is set (END_PROG = 1).
Page 787 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued) Name Function Type Reset Channel enable bit Use EN to enable or disable transfers in the channel. The DMA controller clears EN once a block transfer in the channel is complete. 0: Channel is disabled.
Page 788 DSP DMA Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued) Name Function Type Reset Frame synchronization This bit determines whether the synchronization event initiates the transfer of an element or an entire frame of data. 0: When the selected synchronization event occurs, one element is transferred in the channel.
Page 789 DSP DMA Table 113. DSP DMA Mapping Synchronization [4:0] DSP DMA Request Settings DSP Request Source Line MCSI1 TX DMA_REQ_01 00001 MCSI1 RX DMA_REQ_02 00010 MCSI2 TX DMA_REQ_03 00011 MCSI2 RX DMA_REQ_04 00100 Ext_nDMA_req_0 (MPUIO2) DMA_REQ_05 00101 Ext_nDMA_req_1 (MPUIO4) DMA_REQ_06 00110 FREE DMA_REQ_07...
Page 790 DSP DMA Table 114. Channel Interrupt Control Registers (DMA_CICR0...DMA_CICR5) (Continued) Name Function Type Reset LAST_IE Last frame interrupt enable. LAST_IE determines how the DMA controller responds when it starts transferring the last frame from the source port to the destination port. 0: Do not record the last frame event.
Page 791 DSP DMA Each channel has an interrupt control register DMA_CICR that specifies one or more DMA controller events triggering an interrupt. If an event occurs and its interrupt enable (IE) bit is 1, an interrupt request is sent to the DSP CPU where it can be serviced or ignored.
Page 792 DSP DMA Table 115. Channel Status Registers (DMA_CSR0...DMA_CSR5) (Continued) Name Function Type Reset BLOCK Whole block status bit. The DMA controller sets BLOCK only if BLOCK_IE=1 in the DMA_CICR and all of the current block has been transferred from the source port to the destination port. 0: Current block transfer has not finished yet.
Page 793: Channel Source Start Address
DSP DMA Table 115. Channel Status Registers (DMA_CSR0...DMA_CSR5) (Continued) Name Function Type Reset DROP Synchronization event drop status bit. If a DMA synchronization event occurs again before the DMA controller is done servicing the previous DMA request, an error has occurred (a synchronization event drop).
Page 794: Channel Destination Start Address
DSP DMA Note: Load the source start address registers with a byte address. For a word address, shift left by 1 before loading the registers. For a 16-bit or 32-bit data type, the start address must be aligned properly. See the description of the data type bits of DMA_CSDP. Table 116.
Page 795 DSP DMA Table 118. Channel Destination Start Address, Lower Bits Register (DMA_CDSA_L0...DMA_CDSA_L5) Name Function Type Reset 31:16 Reserved 15:0 Destination start Lower bits for the destination start address are Undefined address, lower bits expressed in bytes. The destination start address is up to a 32-bit byte address, made of the concatenation of DMA_CDSA_U and DMA_CDSA_L.
Page 796 DSP DMA Table 121. Channel Frame Number Registers (DMA_CFN0...DMA_CFN5) Name Function Type Reset 31:16 Reserved 15:0 Channel frame number Frame number Undefined Number of frames within the block to be transferred. The maximum frame number is 65535. The size in bytes of the data block to transfer is DMA_CFN x DMA_CEN x DMA_CES, where DMA_CES is (1, 2, or 4 bytes) as set by DMA_CSDP bits 1:0.
Page 797 DSP DMA Table 123. Channel Source Element Index Registers (DMA_CSEI0...DMA_CSEI5) Name Function Type Reset 31:16 Reserved 15:0 Source element index Element index Undefined Contains the channel source element index, expressed in bytes, which is used to compute the addresses when single-indexed addressing mode is used.
Page 798 DSP DMA Table 125. Channel Destination Address Counter Registers (DMA_CDAC0...DMA_CDAC5) Name Function Type Reset 31:16 Reserved 15:0 Destination This register can be used to monitor the progress Undefined element/frame address of a DMA transfer on channel destination port. It is 16 LSB a snapshot of the current destination address generated by the channel destination address...
Page 799: Dsp Dma Programming Guidelines
DSP DMA Table 127. Channel Destination Frame Index Registers (DMA_CDFI0...DMA_CDFI5) Name Function Type Reset 31:16 Reserved 15:0 Destination frame index Channel destination frame index Undefined Contains the channel source element index, expressed in bytes, which is used to compute the addresses when double-indexed addressing mode is used.
Page 800: Autoinitialization
DSP DMA All of the transfers can be synchronized to DMA requests, whatever their sources and destinations. The DMA requests come from signals PENDMAREQ(19:0) located on the DSP boundary. One DMA request can trigger several channels at the same time. 4.24.3 Autoinitialization A DMA channel (synchronized or not) can operate in two modes: Single...
Page 801: Addressing Modes
DSP DMA The following registers are part of the working set and are accessible to the user. They always have an effect on the current transfer. DMA_CSDP DMA_CCR DMA_CICR DMA_CSR An error can occur if the CPU accesses a channel to program it while it is reloading.
Page 802: Data Packaging And Bursting
DSP DMA The data block to transfer is split into frames and elements. The byte size of this data block is: BS = FN x EN x ES where: BS is the block size in bytes. FN is the number of frames in the block, 1 ≤ FB ≤ 65535. EN is the number of elements per frame, 1 ≤...
Page 803: Data Alignment
DSP DMA 4.24.6 Data Alignment During a transfer, all of the addresses computed by the DMA must be aligned on the type of data transferred if: Data type is s8 (8-bit scalar data); addresses can have any value. Data type is s16 (16-bit scalar data); addresses must be aligned on 16-bit word boundary (the lowest bit of the address is always 0).
Page 804: Memory Space Issues
DSP DMA If the time-out counter reaches its threshold before the request is acknowledged, the request is discarded and an error is reported in the DMA channel by setting the relevant bit in DMA_CSR (channel status register) and sending an interrupt to the processor. The channel is stopped.
Page 805 175 channels and port accesses 126 DSP DMA service chain 129 MPUI access 128 DSP DMA start address 134 checking synchronization status 145 I/O space 135 configuration registers 149 data alignment 143 DSP DMA time out conditions 147 SPRU755B OMAP5912...
Page 806 DSP DMA transfer latency 148 DSP GDMA handler 24 notational conventions 3 DSP subsystem, DMA controller 121 related documentation from Texas Instruments 3 Interrupt generation, DSP DMA 179 Synchronizing DSP DMA channel activity 143 Memory, map, high−level DSP 135 Memory space, DSP DMA 180...
Page 807 OMAP5912 Multimedia Processor Memory Interfaces Reference Guide Literature Number: SPRU756A March 2004...
Page 808 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 809 Preface Read This First About This Manual This chapter describes the memory interfaces of the OMAP5912 multimedia processor. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
Page 810 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 811 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU756A...
Page 812 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 813 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 814 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 815 Contents Contents Introduction ..............SDRAM Interface .
Page 816 ..............OMAP5912...
Page 817 Software NFC with Non-Multiplexed NOR and CFC ....... . . SPRU756A OMAP5912...
Page 818 Legal Values for NND_ECC_SELECT Registers ........OMAP5912 SPRU756A...
Page 819 ............. SPRU756A OMAP5912...
Page 820 OMAP5912 SPRU756A...
Page 821: Introduction
Memory Interfaces This document describes the memory interfaces of the OMAP5912 multimedia processor. Introduction This document describes the following interfaces: SDRAM (external memory interface fast, or EMIFF) Asynchronous and synchronous burst memory (external memory interface slow, or EMIFS) NAND flash (hardware controller or software controller)
Page 822: Omap1612 Stacked Ddr Support
Introduction Program the SDRAM_TYPE field of the EMIFF interface SDRAM configuration register to specify the physical configuration of the devices. The SDRAM type selection is the first action required from the software driver, using the SDRAM_TYPE field of the EMIF SDRAM operation register. The SDRAM controller supports: The self-refresh mode (idle), autorefresh, and other operating modes (HPHB, LPLB, and POM0 modes)
Page 823 Introduction 16Mx16 mobile DDR SRAM Four-bank operation Differential clock inputs MRS cycle with address key programs CAS latency (3) Burst length (2, 4, 8) Burst type (Sequential or Interleave) Partial self refresh type (1, 2, 4 banks) Temperature compensated self refresh 1.1.2 EMIFF Configuration for OMAP1612 Stacked DDR The recommended configuration sequence for using the OMAP1612 stacked...
Page 824: Asynchronous And Synchronous Burst Memory Interface (Emifs)
Introduction 11) Set DLL_LRD_CONTROL register to 0x06 (LRD DLL enabled, at 90_ C). 12) Set DLL_WRT_CONTROL register to 0x06 (LRD DLL enabled, at 90_ C). Asynchronous and Synchronous Burst Memory Interface (EMIFS) The synchronous/asynchronous external memory interface slow (EMIFS) supports most common memory interface protocols through a flexible programming and timing signals control.
Page 825: Memory Interfaces For The Emifs
The EMIFS supports dynamic local idle mode control. The EMIFS also supports IC deep power-down mode request synchronization. OMAP5912 can also support CompactFlash devices through the EMIFS. Memory Interfaces for the EMIFS There are a number of different memory types that can connect with the EMIFS interface.
Page 826: Hardware Nand Flash Controller
Memory Interfaces for the EMIFS 16−bit NAND flash—controlled by EMIFS directly (software NAND flash controller) CompactFlash—controlled by the compact flash controller (CFC) Some of these controllers can be used simultaneously. See Figure 23, Figure 24, and Figure 25 for details on simultaneous connections of these memory types.
Page 827 Memory Interfaces for the EMIFS Figure 1. NAND Flash Controller Overview OCP timing Memory timing Sequencer module Controller timing Address commands N.F.M.C Interface To host Memory Write interface module data module FIFO Read data Select and ECC result enable module NAND flash controller The external NAND flash (NFMC) is an 8-bit interface (byte addressable).
Page 828 Memory Interfaces for the EMIFS Table 1. Command Operations Function First Cycle Second Cycle Third Cycle Read 1 (lower half-page or Area A) 0x00 Read 1 (upper half-page or Area B) 0x01 Read 2 (spare or Area C) 0x50 Read ID 0x90 Reset 0xFF...
Page 829 Memory Interfaces for the EMIFS A, the command 0x00 is sent to the flash core. To access area B, the command 0x01 is sent. To access the spare area, the command 0x50 is sent (see Table 2). Table 2. Pointer Operation Command Accessed Address Area...
Page 830 Memory Interfaces for the EMIFS pulse on RE_ and data is read and stored in the NAND controller access register (NND_ACCESS). The interrupt bit must be cleared by software. Another solution to waiting for data to be ready is to poll the ready bit in the NAND controller ready register (NND_READY).
Page 831: Read Operation
Memory Interfaces for the EMIFS Figure 2. Read Operation Start read Writing to this register, sends also Write 0x70, Write start address, NND_ADDR_SRC the address to the flash core. NND_COMMAND_SEC To select the area: − 0x00: 0−255 Write 0x00, NND_COMMAND or −...
Page 832: Multiplane
Memory Interfaces for the EMIFS Figure 3. Write Operation Start program Write start address, NND_ADDR_SRC To select the area: Write 0x00, NND_COMMAND_SEC 0x00: 0−255 Write 0x01, NND_COMMAND_SEC 0x01: 256−511 0x50: 512−527 Write 0x50, NND_COMMAND_SEC Writing to this register, sends also the address Write 0x80, NND_COMMAND to the flash core While writing, accumulate the...
Page 833: Restriction In Addressing With Multiplane Page Program
Memory Interfaces for the EMIFS Restriction in Addressing With Multiplane Page Program Although any block in each plane can be addressable for the multiplane page program, the page address in the selected block must be the same. This means that, given four addresses (one for each plane), bits 9 to 13 of those addresses must be the same because bits 9 to 13 select the address of the page in a block (see Figure 4).
Page 834 Memory Interfaces for the EMIFS A22-A13 A12-A9 A7-A0 A23-A14 A13-A9 A7-A0 A24-A14 A13-A9 A7-A0 A25-A14 A13-A9 A7-A0 1024 A26-A14 A13-A9 A7-A0 The address of the erase block must be properly formatted in the address register NN_ADDR_SRC. Bits that correspond to the address page in the selected block must be sent, but they are discarded by the internal logic of the NFMC (see Table 5).
Page 835 Memory Interfaces for the EMIFS 00000000 000000-A25-A24 A23-A17-0 A16-A9 1024 00000000 00000-A26-A24 A23-A17-0 A16-A9 Figure 5. Erase Operation Start erase Write (erase block address), NND_ADDR_SRC Writing to this register, also sends Write 0x60, NND_COMMAND the address to the flash core. Write 0xD0, NND_COMMAND_SEC This reads the status register Write 0x70, NND_COMMAND_SEC...
Page 836 Memory Interfaces for the EMIFS bit 6 (Ready/Busy_) of the NFMC status register. When the erase is completed, the pass/fail status of each block is examined by reading the extended pass/fail status of the NFMC status register (bit 1 to bit 4) using the read multi-plane status command (0x71).
Page 837 Memory Interfaces for the EMIFS Figure 7. Copy-Back Operation Start copy−back Write 0x70, NND_COMMAND_SEC Writing to this register, sends also Write source address, NND_ADDR_SRC the address to the flash core. Status = read There is a latency after the address Write 0x00, NND_COMMAND NND_ACCESS is sent, for the to be ready.
Page 838 Memory Interfaces for the EMIFS address, R/B_ remains in a busy state for a short period of time. When the last command operation 0x10 is sent, thel programming of the NFMC starts and the NFMC drives its R/B_ signal low. A read status operation (command 0x70 or 0x71) can be issued to find out when the NFMC returns to ready state by polling the Ready/Busy_ bit in the status register (bit 6).
Page 839 Memory Interfaces for the EMIFS Reserved Reserved Reserved Reserved Reserved Program/erase 0: Pass 1: Fail Table 8. Status Register Mapping for 512, 1024 Megabits Definition Read Status (70h) Read Multiplane Status (71h) Write protect Write protect 0: Protected 0: Protected 1: Not protected 1: Not protected Device operation...
Page 840 Memory Interfaces for the EMIFS read/program/erase) after the reset command is written. If the NFMC is already in reset state, the flash memory command register does not accept a new reset command. It is recommended, after a hardware reset, to start any access to the NFMC by sending a reset command.
Page 841 Memory Interfaces for the EMIFS 2.1.10 Error Code Correction To better protect data, the NFC provides an error code correction (ECC) logic. The algorithm for ECC is the one that Samsung recommends (see Figure 10). It can be used on 256 bytes or 512 bytes (selectable by a control bit in the NND_CTRL register), and can detect errors and correct one bit error.
Page 842 Memory Interfaces for the EMIFS Figure 10. ECC Pointer Management 1 in bit 0 of NND_RESET RESET NND_ECC_SELECT = others NND_ECC_SELECT = 0x5 NND_ECC_SELECT = 0x4 NND_ECC_SELECT = 0x1 NND_ECC_SELECT = 0x3 NND_ECC_SELECT = 0x2 Pointer on the NN D_ECCx register. The pointer transition from one state to another is made after either 256 or 512 data has been read (control bit ECC_256 in the NND_STATUS register).
Page 843 Memory Interfaces for the EMIFS Figure 11. Single Page Read Host Mode Interrupt to host to signal data ready to be read. Reset NND_ECC1, Software clears the interrupt. Flintn (interrupt) NND_ECC2. ECC 256 Spare read with previous ECC. Read data from flash and Read data from flash and ECC check done in software.
Page 844 Memory Interfaces for the EMIFS Figure 12. Single-Page Write Host Mode Write NND_ECC1, Reset Host to check NND_ECC2 in spare. NND_ECC1, the status of NND_ECC2. write operation Î Î ECC 256 Î Î Write data in flash and Write data in flash and accumulate ECC in accumulate ECC in NND_ECC1.
Page 845 Memory Interfaces for the EMIFS 2.1.11 Invalid Block Management Over time, reading/programming/erasing NFMC can introduce errors in data. ECC can protect the data, but if there is more than one error, ECC cannot correct any errors. Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not ensured by the NFMC manufacturer.
Page 846 Memory Interfaces for the EMIFS Figure 13. Invalid Block Mapping Start invalid block table To access 6th byte of the spare Write 0x00000005h, NND_ADDR_SRC area of page 0. Writing to this register, also sends Write 50h, NND_COMMAND the address to the flash core. There is a latency after the Wait for t r time address is sent, for the...
Page 847 Memory Interfaces for the EMIFS 2.1.12 FIFO (Prefetch and Postwrite) A FIFO with prefetch and postwrite functions prevents stalling the processor for too many cycles when reading or programming the NFMC. The host either writes or reads this FIFO directly; the NFC state machine handles the actual programming or reading of the NFMC.
Page 848 Memory Interfaces for the EMIFS When the FIFO is full with FIFO_SIZE byte(s), the NFC signals it by asserting low an interrupt (event FIFO_FULL is 1 and MSK_FULL is 1) and the counter is decremented. The host can read the FIFO through the register NND_FIFO access(es).
Page 849 Memory Interfaces for the EMIFS When prefetch goes from 1 to 0: Prefetch is aborted. Before accessing a new page, software must successively write 0 and then 1 in the prefetch bit. At reset, the prefetch bit is set to 0. Figure 14.
Page 850 Memory Interfaces for the EMIFS the NFC asserts low the interrupt (if event FIFO_EMPTY is unmasked). The CPU refills the FIFO and clears the interrupt. When the counter reaches zero, the interrupt is also asserted (if event COUNT_ZERO is unmasked). To finish programming the NFMC, the command 0x10 must be sent.
Page 851 Memory Interfaces for the EMIFS Figure 15. Single-Page Program in Postwrite Mode Software programs the address. Software program the program command. Software programs the NND_FIFOCTRL register (FIFO_SIZE and BLOCK_COUNT field). Software enables events if needed. Software enables postwrite. N.F.C writes the data to N.F.M.C and empties Host sends “end Host can check the FIFO.
Page 852 Memory Interfaces for the EMIFS Figure 16. Single Page Read DMA Software sends the read command. DMA ends. Software sends the address. Cleared by software. Reset NND_ECC1, FldmaReqn NND_ECC2. Flintn Main area ECC 256 spare The host can decide to Read data from flash and Read data from flash and read the NND_ECC1 and...
Page 853 Memory Interfaces for the EMIFS read past the last byte of the buffer returns the last byte of the FIFO. When the FIFO is fully read, the DMA request is asserted high and the NFC state machine can fill the FIFO again. When the internal counter reaches zero, the FIFO is filled a last time, and when the FIFO is full, the DMA request is asserted low.
Page 854 Memory Interfaces for the EMIFS Figure 17. Single-Page Read DMA in Prefetch Mode Software programs the address. Software programs the read command. Software programs NND_FIFOCTRL register. (FIFO_SIZE and BLOCK_COUNT field). Software enables DMA in system DMA. Software enables prefetch. N.F.C fetches the data from the N.F.M.C and fills the FIFO.
Page 855 Memory Interfaces for the EMIFS for the last time. To finish the programming of the NFMC, the command 0x10 must be sent. DMA writes the data in the FIFO: Once the FIFO is full, any access is stalled. When the FIFO is full, the internal counter is decremented, and the NFC sends the data from the FIFO to the NFMC.
Page 856 Memory Interfaces for the EMIFS Figure 18. Single-Page Program DMA in Postwrite Mode Software programs the address. Software programs the program command. Software programs the NND_FIFOCTRL register (FIFO_SIZE and BLOCK_COUNTER field). Software enables events if needed. Software enables DMA in system DMA. Software enables postwrite.
Page 857 Memory Interfaces for the EMIFS Table 12. Characteristics of Supported NFMCs (Continued) 1Gb/ 512Mb/ 256Mb/ 128Mb/ 64Mb/ 32Mb/ 128 MB 64 MB 32 MB 16 MB 8 MB 4 MB Number of pages per block Block size 16K+512 16K+512 16K+512 16K+512 8K+256 8K+256...
Page 858 Memory Interfaces for the EMIFS Table 13. Supported Operations on NFMCs (Continued) Supported Operations 1Gb/ 512Mb/ 256Mb/ 128Mb/ 64Mb/ 32Mb/ 128MB 64MB 32MB 16MB Block erase multiple Read status Read status multiple Note: Note: This table summarizes the supported operations for the current NFMCs. These operations may change in the fu- ture when new NFMCs are introduced in the market.
Page 859 Memory Interfaces for the EMIFS Table 15. NAND Flash Registers (Continued) Register Description Offset NND_CTRL NAND controller 0x10 NND_MASK Used to mask event sources 0x14 NND_STATUS Used to mask event sources 0x18 NND_READY Used to poll the readiness of the NFMC 0x1C NND_COMMAND Used to write a specific command to the NFMC...
Page 860 Memory Interfaces for the EMIFS Table 16. NAND Controller Revision Register (NND_REVISION) Name Description 31-8 Reserved Reserved NND_REVISION Revision number The NND_REVISION field indicates the current revision number of the NFC. This value is fixed by hardware. The 4 LSB indicate a minor revision. The 4 MSB indicate a major revision.
Page 861 Memory Interfaces for the EMIFS This register also holds the block erase address, which must be properly formatted before being written in this register (see Table 5). Because an access to NND_COMMAND also sends this address to the NFMC, the software first must write the new address in the NND_ADDR_SRC, and then write a command through NND_COMMAND.
Page 862 Memory Interfaces for the EMIFS Table 20. NAND Controller Control Register (NND_CTRL) (Continued) Name Description CHIPEN0 ChipEnable0. When 0, NFMC device is selected. Reserved Reserved ADRCNT[1] Address counter for sending bytes to NFMC ADRCNT[0] Address counter for sending bytes to NFMC When 0, bit A8 of address register is not sent to NFMC.
Page 863 Memory Interfaces for the EMIFS Table 22 shows the resulting read data from the NAND flash memory core. Table 22. Byte Packing Function of MBYTEEN and Little/Big Endianism (NND_ACCESS/NND_FIFO) MBYTEEN BE = 0 BE = 1 [31:24] [23:16 [15:8] [7:0] [31:24] [23:16 [15:8]...
Page 864 Memory Interfaces for the EMIFS Future NFMCs have a different page addressing configuration and bit 8 is part of the address. When control bit A8 is 0, bit 8 of NND_ADDR_SRC is not sent to NFMC. When control bit A8 is 1, bit 8 of NND_ADDR_SRC is sent to NFMC. Table 24.
Page 865 Memory Interfaces for the EMIFS Table 27. Address Counter for Sending Bytes ADRCNT[1]-ADRCNT[0] Number of Byte Address Sent 4 bytes sent (with least significant byte first) 3 bytes sent (with least significant byte first) 2 bytes sent (with least significant byte first) 1 byte sent (with least significant byte first) Bit 7: Reserved Bit 8: The ChipEn0 directly controls the NFMC selection control.
Page 866 Memory Interfaces for the EMIFS direct access to ChipEn2 signal, it must be set to low when access is performed and not set back to high before all operations to the NFMC are terminated. Bit 13: The WriteProt2 bit provides inadvertent write/erase protection during power transitions.
Page 867 Memory Interfaces for the EMIFS These masks are ANDed with the corresponding bits in the NND_STATUS register. Then, all of these contributions are ORed again to form the global interrupt at the boundary of the NFC. Table 29. NAND Controller Status Register (NND_STATUS) Name Description 31-4...
Page 868 Memory Interfaces for the EMIFS Table 30. How to Clear Pending Event Previous Event State Write Next Event State 1 or 0 Bit 1: When the NFC is either in prefetch or postwrite mode, an interrupt is generated when the internal counter reaches zero. This interrupt is cleared by software according to the scheme shown in Table 30.
Page 869 Memory Interfaces for the EMIFS Read 1 (upper) 00000001 Read 2 (spare) 01010000 Read ID 10010000 Page program/page program (multiple) 10000000 Copy-back program (source address) 00000000 Copy-back program (destination address) 10001010 Multiple copy-back program 00000011 Block erase/multiplane block erase 01100000 No action others This register writes a specific command to the NFMC.
Page 870 Memory Interfaces for the EMIFS Table 33. NAND Controller Second Command Register (NND_COMMAND_SEC) (Continued) Name Description Reset Type Read multiplane status 01110001 No action others Writing to this register does not send any address to the NFMC. The command operation codes are primarily to indicate the end of the current operation. For instance, for program operation, after the last data is sent, a delimiter is needed, so command 0x10 (page program end) is sent through the NND_COMMAND_SEC register because there is no need to send the...
Page 871 Memory Interfaces for the EMIFS Table 35. Legal Values for NND_ECC_SELECT Registers (Continued) NND_ECC_SELECT[2:0] ECC Selected All registers above + NND_ECC6 All registers above + NND_ECC7 All registers above + NND_ECC8 Any other value All registers above + NND_ECC9 Table 36. NAND Controller ECC Registers (NND_ECC1...NND_ECC9) Name Description Type...
Page 872 Memory Interfaces for the EMIFS Table 36. NAND Controller ECC Registers (NND_ECC1...NND_ECC9) (Continued) Name Description Type Reset P16e Holds ECC code parities accumulated on row Holds ECC code parities accumulated on row Holds ECC code parities accumulated on column Holds ECC code parities accumulated on column Holds ECC code parities accumulated on column These registers hold the ECC code calculated while reading/writing the NFMC.
Page 873 Memory Interfaces for the EMIFS This register is used to access the FIFO when prefetch or postwrite mode is selected. Any access to this register is stalled when FIFO is busy. Access to this register in host mode has no effect; the return value in case of a read is 0x00000000.
Page 874 Memory Interfaces for the EMIFS Table 42. Values for Divider PSC Value Division PSC Value Division Divided by 1 Divided by 9 Divided by 2 Divided by 10 Divided by 3 Divided by 11 Divided by 4 Divided by 12 Divided by 5 Divided by 13 Divided by 6...
Page 875 Memory Interfaces for the EMIFS Table 43. NAND Controller System Test Register (NND_SYSTEST) Name Description Type Reset 31-16 Reserved Reserved TEST-UNLO To unlock test features 14-3 Reserved Reserved When 1, the internal FIFO is mapped as registers. ACCESS If 1, unlock registers for read/write access ALLOW_INT If 1, can initiate an interrupt This register tests some features of the NFC.
Page 876 0x00000000. Software NAND Flash Controller This section describes how to connect OMAP5912 to a NAND flash using only the EMIFS logic (referred to throughout this chapter as the Software NAND flash controller). The software NAND flash controller can connect to either 8-bit or 16-bit NAND flashes.
Page 877 2.2.2 EMIFS Interface With NAND CE Care Flash Device Option The interface of a NAND CE Care flash device to the OMAP5912 is possible by using FLASH.CS2UOE (output enable) and FLASH.CS2UWE (write enable). The only exception to this policy is that several signals that are used for the NAND flash interface are muxed on signals that are needed for support of synchronous burst flash memories.
Page 878 The source data can reside in any memory space available in the system. The MPU is the processor controlling the write operations. Figure 20. NAND Flash Write Sequence OMAP5912 Step 2 Step 2 NAND flash EMIFS...
Page 879 Software NAND Flash Controller Step 1: Calculate ECC The MPU programs the system DMA as follows: Transfers the data in 8-, 16-, or 32-bit word format from SDRAM into the NAND flash controller Transfer mode (single mode= > channel stop when current transfer finishes) The DMA creates an interrupt on completion of the transfer.
Page 880 Software NAND Flash Controller The DMA interrupts the processor when the transfer is complete. The processor reads the ECC calculation from the NAND flash controller peripheral. The calculated ECC results are written in SDRAM. Step 2: Configure EMIFS and NAND Flash for a Write The associated EMIFS CS chip-select control register is programmed.
Page 881 Data can be saved in any memory space available in the system. The MPU is the processor controlling the read operations. Figure 21. NAND Flash Read Sequence OMAP5912 Step 1 NAND flash Step 1 EMIFS...
Page 882 Software NAND Flash Controller The MPU programs the system DMA: Transfer the data in 8-,16-, or 32-bit word format from theNAND_FLASH device to SDRAM. Transfer mode (single mode= > channel stop when current transfer finishes) The DMA creates an interrupt on completion of the transfer. The processor MPU configures the NAND flash controller peripheral as follows: Selects the number of blocks to calculate ECC on (1-9) the...
Page 883 Software NAND Flash Controller The R/B signal goes low to signify that the NAND flash is busy with the internal operation. The R/B signal goes high, creating an interrupt to the processor that signifies that the block read has been completed (new block can be read). Step 3: Calculate ECC The MPU programs the system DMA: Transfer the data in 8-, 16-, or 32-bit word format from SDRAM into the...
Page 884 Software NAND Flash Controller Figure 22. NAND Flash Device Interface Schematic NAND flash device OMAP5912 Config register FLASH.CS2U cs2b GPIOx VDDSHV5 Config register FLASH.RDY GPIO FLASH.CS2UWE cs2b EMIFS FLASH.WE FLASH.CS2UOE cs2b FLASH.OE FLASH.WP FLASH.A[1] FLASH.A[2] FLASH.D[7:0] or FLASH.D[15:0] I/O7−0 or IO15−0...
Page 885 GPIO of the OMAP161X device. If another GPIO is used, the interface voltage range must be considered between the open drain output of the NAND flash and the OMAP5912. Otherwise, it is possible to remove this input requirement by the use of timers to create the delay and/ or the use polling of the NAND flash device status register.
Page 886 Software NAND Flash Controller ac Specifications and Issues A review of the Samsung K9K1G08U0M NAND flash device ac specifications versus the EMIFS interface has resulted in the following findings: All timings required for write accesses are acceptable. WP (WE pulse width) minimum is 25 ns, which implies a maximum rate of 40 MHz.
Page 887 Software NAND Flash Controller Figure 23. Software NFC with Non-multiplexed NOR and CFC OMAP5912 Up to 64MB memory space for each CS Async NOR_FLASH FLASH.A[17:25] FLASH.A[1:16] FLASH.D[0:15] FLASH.A[1:25] FLASH.OE FLASH.D[0:15] FLASH.WE FLASH.OE core FLASH.WP FLASH.WE FLASH.RDY FLASH.WP FLASH.BE[0] FLASH.CS FLASH.BE[1]...
Page 888 If this solution is chosen, the NOR flash interface must be configured with ADDRESS and DATA multiplexed. This solution reuses ADD(1:16) for the hardware NAND flash controller. Figure 24. Hardware NFC with Multiplexed NOR Flash Add On Option OMAP5912 up to 64MB memory space for each CS mux NOR_FLASH 54 pins FLASH.A[17:25] FLASH.A[1:16]...
Page 889 CompactFlash Controller 2.4.1 CFC Connection The CFC interfaces the slow memory interface block and memories. When CompactFlash access is required, the CFC generates CompactFlash signals and processes the CompactFlash protocol. Figure 25 shows how to connect external compact flash to CFC. SPRU756A Memory Interfaces...
Page 890 CompactFlash Controller Figure 25. Software NFC with Non-Multiplexed NOR and CFC OMAP5912 Up to 64MB memory space for each CS Async NOR_FLASH FLASH.A[17:25] FLASH.A[1:16] FLASH.D[0:15] FLASH.A[1:25] FLASH.OE FLASH.D[0:15] FLASH.WE FLASH.OE core FLASH.WP FLASH.WE FLASH.RDY FLASH.WP FLASH.BE[0] FLASH.CS FLASH.BE[1] FLASH.CS3 FLASH.CS2 FLASH.CS1...
Page 891 CFLASH.CD2 Card detect CFLASH.IREQ RDY/BSY Ready for new data IREQ The I/O values are signals from OMAP5912. 2.4.3 Memory Access Mode Selection The CompactFlash card supports the following access modes: Common memory Attribute memory The controller manages access to the different modes of the CompactFlash (access protocol in these modes follows the CompactFlash standard).
Page 892 CompactFlash Controller Table 49 lists the memory mapping used to select the access mode. Table 49. CFC Memory Mapping Space Name Start Address and CS Address Stop Address Size CF memory space 0000:0000 0000:07FF 2K bytes CF attribute space 0000:0800 0000:0FFF 2K bytes CF I/O space...
Page 893 CompactFlash Controller Table 51. CFC Status Register (CF_STATUS_REG) Name Function Reset 15:3 Unused 0x1FFF Last read access Bad read access (active low) When a CompactFlash read access is performed and the CompactFlash card is not correctly connected (Card Detect is high), the CFC asserts this bit low. Last write access Bad write access (active low) When a CompactFlash write access is performed and the...
Page 894 Frame Buffer Table 52. CFC Configuration Register (CF_CFG_REG) (Continued) Name Function Reset Chip-select 1 Chip-select is actually connected on chip-select 1 (active configuration low). Any transfer to CS_1 is a CompactFlash access. Chip-select 0 Chip-select is actually connected on chip-select 0 (active configuration low) Any transfer to CS_0 is a CompactFlash access.
Page 895 Frame Buffer System DMA (DMA OCPT1 port) The frame buffer only supports READ/WRITE/IDLE accesses: an error is generated in other cases or if the address is incorrect. The frame buffer only supports 8-, 16-, and 32-bit access in little endian. Data Bus Access Size System Address...
Page 896 Memory Interfaces SPRU756A...
Page 897 Index Index NAND flash registers 52 postwrite 43 prefetch 41 Asynchronous/synchronous burst memory 18 read ID 34 read operation 23 read status and read multiplane status 32 reset 33 write operation 25 CompactFlash connection 83 CompactFlash controller 82 connection 83 interface registers 86 memory access mode selection 85 Invalid block management, NAND flash 39...
Page 898 Index Software NAND flash controller 70 EMIFS with NAND CE care 71 EMIFS with NAND CE don’t care 80 Postwrite, NAND flash 43 peripheral/NOR add−on option 82 Prefetch, NAND flash 41 read data sequence 75 write data sequence 72 Read ID operation, NAND flash 34 Read operation, NAND flash 23 Read status and multiplane status, NAND flash 32 Test RAM, memory interfaces 88...
Page 899 OMAP5912 Multimedia Processor Interrupts Reference Guide Literature Number: SPRU757B October 2004...
Page 900 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 901 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments Documentation that describes the OMAP5912 device, related peripherals, and other technical collateral, is available in the OMAP5912 Product Folder on TI’s website: www.ti.com/omap5912. Trademarks OMAP and the OMAP symbol are trademarks of Texas Instruments.
Page 902 Contents Contents Interrupt Overview ..............DSP Interrupt Mapping .
Page 903 ..........SPRU757B OMAP5912...
Page 904 ..........OMAP5912...
Page 905 ........... . SPRU757B OMAP5912...
Page 906 ........Interrupt Level Register for Interrupt Number x [0−15] (DSP_ILRx) ....OMAP5912 SPRU757B...
Page 907: Interrupt Overview
Interrupts This document describes the interrupts of the OMAP5912 multimedia processor. Interrupt Overview Three level 2 interrupt controllers are used in OMAP5912: One MPU level 2 interrupt handler (also referred to as MPU interrupt level 2) is implemented outside of OMAP3.2 and can handle 128 interrupts.
Page 908 Interrupt Overview Figure 1. Interrupt Interconnect MPUIO McBSP1 GPIOs wake up McBSP3 OS TIMER UART1 1− Wire UART2 MMC/SDIO 1 GPIO2 ULPD 8XGPTIMER GPIO3 UART3 GPIO4 McBSP2 µWire MCSI1 MMC/SDIO2 Keyboard MCSI2 GPIO1 CompactFlash DSP interrupt MPU interrupt handler level 2.1 handler level 2 DSP interrupt handler level 2.0...
Page 909: Dsp Interrupt Mapping
Interrupt Overview DSP Interrupt Mapping On the DSP side are 98 interrupt input lines, 18 on the first level, and 80 on the second level. Table 1. DSP Level 1 Interrupt Mapping DSP Soft DSP Hard Location Vectors Interrupt Interrupt (Hex/Byte) Priority Function...
Page 910: Dsp Level 2 Interrupt Handler
Interrupt Overview Table 1. DSP Level 1 Interrupt Mapping (Continued) DSP Soft DSP Hard Location Vectors Interrupt Interrupt (Hex/Byte) Priority Function SINT23 INT23 DSP timer 1 interrupt SINT24 INT24 Bus error interrupt # 25 BERR SINT25 INT25 Emulator interrupt # 26 DLOG SINT26 INT26 Emulator interrupt # 27 RTOS...
Page 911 Interrupt Overview Table 2. DSP Level 2 Interrupt Mapping Default Sensitivity Configuration Level 2.0 Interrupt Line Mapping IRQ_0 McBSP3 TX Level IRQ_1 McBSP3 RX Level IRQ_2 McBSP1 TX Level IRQ_3 McBSP1 RX Level IRQ_4 UART2 Level IRQ_5 UART1 Level IRQ_6 MCSI1 TX Level IRQ_7...
Page 912: Mpu Interrupt Mapping
Interrupt Overview Table 3. DSP Level 2.1 Interrupt Mapping (Continued) Level 2.1 Interrupt Default Sensitivity Line Configuration Mapping IRQ_7 GPTIMER7 Level IRQ_8 GPTIMER8 Level IRQ_9 Reserved −−−−− IRQ_10 McBSP2 TX Level IRQ_11 McBSP2 RX Level IRQ_12 MCSI1_RST_INT Level IRQ_13 MCSI2_RST_INT Level IRQ_14 MMC/SDIO2...
Page 913 Interrupt Overview Table 4. MPU Level 1 Interrupt Mapping (Continued) Level 1 Interrupt Line OMAP 5912 Mapping Sensitivity IRQ_4 McBSP2 TX Edge IRQ_5 McBSP2 RX Edge IRQ_6 IRQ_RTDX (emulation event) Edge IRQ_7 IRQ_DSP_MMU_ABORT Level IRQ_8 IRQ_HOST_INT Edge IRQ_9 IRQ_ABORT Level IRQ_10 IRQ_DSP_MAILBOX1 Level...
Page 914: Arm926Ejs Level 2 Interrupt Mapping
Interrupt Overview Table 4. MPU Level 1 Interrupt Mapping (Continued) Level 1 Interrupt Line OMAP 5912 Mapping Sensitivity IRQ_28 Public TIPB abort Level IRQ_29 Reserved −−−−− IRQ_30 IRQ_TIMER2 Edge IRQ_31 IRQ_LCD_CTRL Level † These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime- dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
Page 915 Interrupt Overview Table 5. MPU Level 2 Interrupt Mapping (Continued) Level 2 Interrupt Line Mapping Sensitivity IRQ_12 McBSP1 TX Edge IRQ_13 McBSP1 RX Edge IRQ_14 UART1 Level IRQ_15 UART2 Level IRQ_16 MCSI1 combined TX/RX/Frame error/RST Level IRQ_17 MCSI2 combined TX/RX/Frame error/RST Level IRQ_18 Free...
Page 916 Interrupt Overview Table 5. MPU Level 2 Interrupt Mapping (Continued) Level 2 Interrupt Line Mapping Sensitivity IRQ_37 GPTIMER6 Level IRQ_38 GPTIMER7 Level IRQ_39 GPTIMER8 Level IRQ_40 IRQ1_GPIO2 Level IRQ_41 IRQ1_GPIO3 Level IRQ_42 MMC/SDIO2 Level IRQ_43 CompactFlash Edge IRQ_44 COMMRX (emulation event) Level IRQ_45 COMMTX (emulation event)
Page 917: Interrupt Controllers (Mpu Level 2 And Dsp Level 2.1)
Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 5. MPU Level 2 Interrupt Mapping (Continued) Level 2 Interrupt Line Mapping Sensitivity IRQ_63 Reserved −−−−− IRQ_64 Reserved (USB HHC2 suspend) −−−−− IRQ_65 Reserved −−−−− IRQ_66 Free −−−− IRQ_67− Reserved −−−−−...
Page 918: Functional Description
Interrupt Controllers (MPU Level 2 and DSP Level 2.1) The interrupt controller can be programmed to assign different priorities and mask each interrupt independently. Each interrupt line can be programmed to be either level sensitive or edge triggered. The interrupt handler also provides an asynchronous signal to the host in order to have a way to wake up the system, in case an interrupt occurs when the clocks are turned off (system in idle state).
Page 919 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Figure 2. Interrupt Controller External interrupts Interrupt set register (SISR) Merge Edge detection Level or edge detected Interrupt input register (ITR) Mask interrupt register (MIR) Interrupt level register 0 (ILR0) Process next pending IRQ Interrupt level register 1 (ILR1) Process next pending FIQ Generate IRQ...
Page 920: Interrupt Processing Sequence
Interrupt Controllers (MPU Level 2 and DSP Level 2.1) 2.1.1 Interrupt Processing Sequence Although only the IRQ is discussed here, the sequence is the same for FIQ. The sequence depends, however, on the interrupt sensitivity (level or edge). 2.1.2 Edge-Triggered Interrupts 1) The interrupt controller module receives incoming interrupts and registers them in the ITR register.
Page 921: Interrupt Latency
Interrupt Controllers (MPU Level 2 and DSP Level 2.1) 4) Within the interrupt routine, the host reads the SIR_IRQ register in the interrupt controller to determine which interrupt line caused the interrupt. Reading the SIR_IRQ has no effect on the ITR register for the level-sensitive interrupt, because the interrupt is still asserted at this point.
Page 922: Going To Sleep
Interrupt Controllers (MPU Level 2 and DSP Level 2.1) 2.1.6 Going to Sleep The procedure used for going to sleep depends on the IDLE_MODE value. Smart Idle Mode In SMART_IDLE mode, when the IDLE_REQ signal is asserted (high level), the interrupt handler goes into an idle state on the next functional clock cycle, if no IRQ/FIQ is currently pending.
Page 923 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) When the interrupt controller functional clock is eventually turned on, the interrupt controller goes out of idle state and generation of IRQ/FIQ is enabled again. The interrupt waking up the system is not lost (although reading the SIR register does not necessarily give the waking interrupt number, if another higher priority interrupt was pending when the system was awakened).
Page 924 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Figure 3. Global Mask Bit Effect Mask all incoming Process any IRQ/FIQ interrupts currently active GLOBAL_MASK bit asserted Standard ASSERT_IRQ_SECURE_MASK_N functionality signal Unmask all Wait for GLOBAL_MASK Deassert incoming interrupts IRQ_SECURE_MASK_N signal deassertion (masking is controlled by MIR)
Page 925 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) All unused register bits are read as 0. The OMAP programming model ensures that no posted write occurs in any writeable register. Table 6 lists the interrupt controller registers. Table 7 through Table 20 describe the register bits.
Page 926 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 6. Interrupt Controller Registers (Continued) Register Description Offset ILR Registers (Continued) ILR10 Interrupt priority level register bit 10 0x44 ILR11 Interrupt priority level register bit 11 0x48 ILR12 Interrupt priority level register bit 12 0x4C ILR13 Interrupt priority level register bit 13...
Page 927 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 6. Interrupt Controller Registers (Continued) Register Description Offset ILR Registers (Continued) ILR31 Interrupt priority level register bit 31 0x98 Status and ID Register SISR 0x9C Software interrupt set register STATUS Status register 0xA0 OCP_CFG...
Page 928 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) In case of an edge-sensitive interrupt, when the host accesses the SIR_IRQ or SIR_FIQ register, the bit corresponding to the currently active interrupt is reset. For level-sensitive interrupts, this bit is simply the interrupt line current state (after resynchronization).
Page 929 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) This register stores the currently active IRQ interrupt number (in hexadecimal). Reading this register clears the corresponding bit in the ITR register if the interrupt is set as edge sensitive. Unused bits are read as 0. In case a priority calculation is ongoing for IRQ, read to this register is stalled until priority calculation completion.
Page 930 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 12. Control Register Bit Descriptions Name Function GLOBAL_MASK Setting this bit to 1 has the following effect (in this order): All incoming or software generated (through SISR) interrupts are still stored in ITR, but neither FIQ nor IRQ are.
Page 931 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 14 describes the interrupt level register bits. Table 14. Interrupt Level Register Bit Descriptions Name Function PRIORITY Defines the priority level when the corresponding interrupt is routed to IRQ or FIQ. 0 is the highest priority level.
Page 932 Interrupt Controllers (MPU Level 2 and DSP Level 2.1) Table 17. Status Register Bit Description Name Function RESET_DONE 0: Reset has not occurred (functional logic is currently being reset). 1: Reset has occurred. This bit concerns only the functional and OCP clock domains. When OCP clock domain is being reset, OCP accesses are stalled and this bit cannot be read.
Page 933 Level 1 MPU Interrupt Handler Table 20. Interrupt Revision Register (INTH_REV) DW-1… 8 † @0xA8 Reserved MAJOR_REV MINOR_REV Access Default Revision dependent Revision dependent † DW = 32 for the MPU interrupt handler; DW = 16 for the DSP interrupt handler. This register provides the revision number of the interrupt controller block.
Page 934 Level 1 MPU Interrupt Handler One interrupt level register (ILR) is associated with each incoming interrupt. ILR determines whether the interrupt is to be edge-triggered or level-sensitive and assigns it a priority level: 0 (the highest priority), 1, ... 30, 31 (the lowest priority).
Page 935 Level 1 MPU Interrupt Handler Figure 4. MPU Interrupt Handler 32 external interrupts Interrupt set register (SIR) Edge detection FLIP_FLOPS Level or edge detected Interrupt input register (ITR) itmr Mask interrupt register (MIR) Interrupt level register 0 (ILR0) Process next pending IRQ Process next pending FIQ Interrupt level register 1 (ILR1) Generate IRQ...
Page 936 Level 1 MPU Interrupt Handler 3.1.3 Interrupt Sequence Table 21 shows the MPU interrupt sequence for an IRQ interrupt only. The FIQ interrupt sequence is identical. Table 21. MPU Interrupt Sequence Step Interrupt Handler Action MPU Action One or several If one active interrupt occurs and the interrupts occur that set IRQ is not already active, the interrupt...
Page 937 Level 1 MPU Interrupt Handler 3) If the IRQ (interrupt from interrupt handler to the MPU) is not active, the interrupt handler sends the interrupt in N_IRQ register to the MPU as an IRQ signal. Then the source IRQ register (SIR_IRQ) is updated with contents of the N_IRQ register (the SIR_IRQ contains encoded information that conveys the interrupt line number of the IRQ).
Page 938 Level 1 MPU Interrupt Handler 6) The ISR code must be capable of doing one of the following things: Letting the peripheral know that the interrupt generated by it has been serviced so the peripheral can deassert the interrupt request Writing to interrupt handler mask interrupt register (MIR) to mask the level-sensitive interrupt Here the peripheral has to deassert the interrupt before the mask to...
Page 939 Level 1 MPU Interrupt Handler Table 23. Interrupt Register (ITR) Offset: 0x00 Name Function Reset 31:0 ACT_IRQ Sets corresponding bit in ITR for edge-sensitive and 0x0000 0000 level-sensitive interrupts. When the MPU accesses SIR_IRQ or SIR_FIQ, the ITR bit corresponding to the interrupt that has requested MPU action is reset.
Page 940 Level 1 MPU Interrupt Handler Table 27. Interrupt Control Register (CONTROL_REG) Offset: 0x18 Name Function Reset 31:2 Reserved NEW_FIQ_AGR New FIQ agreement. Writing a 1 resets the FIQ output, clears the SIR_FIQ, and enables a new FIQ generation. The corresponding bit of the ITR must be cleared first.
Page 941 DSP Level 1 and Level 2.0 Interrupt Handler and Interface The user can program the SIR register to emulate the interrupt generation. The corresponding ILR must be programmed as edge-sensitive while using SIR register. The procedure to generate an edge-sensitive interrupt is: SIR(bit i) = 0 −...
Page 942 Description Each incoming interrupt can be masked individually by setting the corresponding bit in DSP_MIR to 1. One interrupt level register (DSP_ILR) is associated with each incoming interrupt. The DSP_ILR sets whether the interrupt is to be edge-triggered or level-sensitive and assigns it a priority level: 0 (the highest priority level), 1, ... 14, 15 (the lowest priority level).
Page 943 Interrupt Sequence 4.1.4 Interrupt Interface The DSP interrupt interface augments DSP interrupt handler capability by enabling you to define edge-triggered or level-sensitive implementations for each of external interrupt lines. The DSP interrupt interface allows you to program the edge- or level-sensitivity of the two level 1 interrupts where IRQ and FIQ are routed.
Page 944 Interrupt Handler Software Table 31. DSP Interrupt Sequence Step Interrupt Handler Action DSP Action One or several interrupts occur If one active interrupt occurs and that set the corresponding bits in the IRQ is not already active, the DSP_ITR register interrupt handler sends an IRQ.
Page 945 Interrupt Handler Software 3) If the IRQ (interrupt from DSP interrupt handler to the DSP) is not active, the DSP interrupt handler sends the highest priority interrupt (interrupt in N_IRQ register) to the DSP as an IRQ signal. Then the DSP_SIR_IRQ register is updated with contents of the N_IRQ register (the DSP_SIR_IRQ contains encoded information that conveys the interrupt line number of the IRQ).
Page 946 Registers 6) The ISR code must be capable of doing one of the following things: Letting the peripheral know that the interrupt generated by it has been serviced so the peripheral can deassert the interrupt request Writing to the DSP mask interrupt register (DSP_MIR) to mask the level-sensitive interrupt Here the peripheral must deassert the interrupt before the mask to the interrupt can be removed, so that the next interrupt can be recognized.
Page 947 Registers Table 33. Incoming Interrupt High Register (EDGE_EN_HI) Offset: 0x00 Name Function Reset 15:8 Reserved HOST_INTERRUPT Defines whether the host interrupt from DSP to MPU is edge-triggered or level-sensitive: 0: HOST_INTERRUPT is level-sensitive. 1: HOST_INTERRUPT is edge-sensitive. Defines whether the nonmaskable interrupt is edge or level sensitive: 0: NMI is level-sensitive.
Page 948 Registers Table 35. DSP Interrupt Registers Name Description Offset DSP_ITR DSP interrupt 0x00 DSP_MIR DSP mask interrupt 0x02 DSP_SIR_IRQ Interrupt encoded source for IRQ 0x04 DSP_SIR_FIQ Interrupt encoded source for FIQ 0x06 DSP_CONTROL_REG DSP interrupt control 0x08 DSP_SISR DSP software interrupt set 0x0A DSP_ILRx DSP interrupt level for interrupt number x...
Page 949 Registers Table 39. Interrupt Encoded Source Register for FIQ (DSP_SIR_FIQ) Offset: 0x06 Name Function Reset 15:4 Reserved FIQ_NUM Indicates the encoded interrupt number that has an 0000 FIQ request. Reading this register clears the corresponding bit in the DSP_ITR if the interrupt is set as edge-sensitive.
Page 950 Registers Table 42. Interrupt Level Register for Interrupt Number x [0−15] (DSP_ILRx) Offset: 0x0C Name Function Reset 15:6 Reserved PRIORITY Defines the priority level when the corresponding 0000 interrupt is routed to IRQ or FIQ. 0 is the highest priority level. 15 is the lowest priority level.
Page 951 MPU interrupt mapping 14 Interrupt controller 19 description 20 external interrupt asynchronous path 24 global masking 25 related documentation from Texas Instruments 3 interrupt latency 23 interrupt processing sequence 22 registers 26 Interrupt controller registers 26 Interrupt global masking 25...
Page 952 OMAP5912 Multimedia Processor Peripheral Interconnects Reference Guide Literature Number: SPRU758A March 2004...
Page 953 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 954 OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
Page 955 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
Page 956 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU758A...
Page 957 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
Page 958 Eight data output lines of the GPIO3 are ORed together to generate a global output line at the OMAP5912 boundary. This global output line can be used in conjunc- tion with the SSI to provide a CMT−APE interface to the OMAP5912.
Page 959 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.
Page 960 Contents Contents Shared Peripherals ............. . . Layer 4 Interconnect .
Page 961 ..........On-Chip/Off-Chip Memory and Peripheral Access Latencies ......OMAP5912 SPRU758A...
Page 962 ............. . . SPRU758A OMAP5912...
Page 963 ..........OMAP5912...
Page 964 Shared Peripherals Outside OMAP 3.2, the OMAP5912 includes several peripherals. They can be considered shared by the MPU and the DSP, or can be DSP or MPU private. Privacy is mainly driven by the performance requested by the peripheral.
Page 965: Shared Peripherals
Shared Peripherals Figure 1. Peripherals Access L4 controller Protocol DSP private peripherals converter Protocol Shared DSP peripherals converter Private DSP peripherals Dynamic shared Dynamic MPU/DSP muxing peripherals Semi-static shared MPUI Semi static MPU/DSP muxing peripherals Protocol Shared MPU peripherals converter Private Protocol MPU private peripherals...
Page 966 Shared Peripherals Table 1. MPU/DSP Peripheral Access (Continued) MPU Domain DSP Domain Module MPU Start MPU End MPU TIPB L4 Controler DSP Start DSP End DSP TIPB Name Bus Type Switch Bus Type OMAP FFFE 1000 FFFE 17FF Private 5912 configuratio 32-kHz FFFB...
Page 967 L4 Controler DSP Start DSP End DSP TIPB Name Bus Type Switch Bus Type L3 OCP T1 FFFE FFFE C1FF Private interface C100 OMAP5912 FFFB FFFB Shared Semi-static E101 C800 E101 Shared TIPB switch C800 CBFF CBFF TIPB bridge FFFE...
Page 968 Shared Peripherals Table 1. MPU/DSP Peripheral Access (Continued) MPU Domain DSP Domain Module MPU Start MPU End MPU TIPB L4 Controler DSP Start DSP End DSP TIPB Name Bus Type Switch Bus Type MPU level FFFE 0000 FFFE 07FF Private 2 interrupt handler MPUIO...
Page 969 Shared Peripherals Table 1. MPU/DSP Peripheral Access (Continued) MPU Domain DSP Domain Module MPU Start MPU End MPU TIPB L4 Controler DSP Start DSP End DSP TIPB Name Bus Type Switch Bus Type FFFB FFFB D7FF Shared Semi-static E101 D400 E101 Shared timer 8...
Page 970 Shared FFFB FFFB C3FF Shared 1-Wire C000 FFFE A000 FFFE A7FF Private Dynamic E101 A400 E101 Shared (reserved) A7FF OMAP5912 FFFE 5800 FFFE 5FFF Private JTAG (test) BCM (test) FFFE 3800 FFFE 3FFF Private Production FFFE 2000 FFFE 27FF Private...
Page 971: Layer 4 Interconnect
The SSI and the GDD modules are on the L3-OCP2 port and thus are seen as part of memory port interface. Layer 4 Interconnect The layer 4 interface manages accesses to OMAP5912 peripherals through the MPU shared TIPB bridge, DSP shared TIPB bridge, MPU private TIPB bridge, and DSP private TIPB bridge.
Page 972 Layer 4 Interconnect MPU private TIPB router to MPU private TIPB bridge DSP private TIPB router to DSP private TIPB bridge Figure 2. Layer 4 Interface Layer 4 Interface Peripheral j VIA-TIPB wrapper j VIA protocol TIPB router L4_BUS_CLK shared TIPB bridge Peripheral k Static switch...
Page 973 OMAP 5912 Peripheral Interface TIPB Router DSP level 2 interrupt handler Wrapper OCP Private DSP ULPD (clock and reset) TIPB Private MPU OMAP5912 configuration TIPB Private MPU Secure watchdog Wrapper OCP Private MPU 32-kHz watchdog Wrapper OCP Private MPU MPU level 2 interrupt handler...
Page 974: Protocols
Layer 4 Interconnect Table 4. DSP Peripherals Connected to DSP Shared TIPB Bridge OMAP 5912 Peripheral Interface TIPB Router 2 x MCSI TIPB Shared DSP 2 x McBSP Wrapper OCP Shared DSP Table 5. DSP and MPU Shared Peripherals OMAP 5912 Peripheral Interface TIPB Router MMCSD/IO2...
Page 975: Bus Allocation
Layer 4 Interconnect Dynamic Switch Figure 3. Dynamic Switch for OCP Peripheral Synchronization with dynamic switch clock allocation module TIPB bridge TIPB to OCP to TIPB peripheral interface interface TIPB bridge Synchronization with MPU strobe *Default values Synchronization with DSP strobe Note: Default value: To simplify the TIPB router implementation and reduce the toggling on buses, a default value is returned to the host, which does not access the peripheral.
Page 976: Mpu/Dsp Tipb Bridge To Peripherals
Layer 4 Interconnect Figure 4. Transfer from Host to Peripheral MPU TIPB bridge signals PERIPHERAL DSP TIPB bridge signals Bus allocation module MPU/DSPTIPB bridge to peripherals Peripherals to MPU/DSP TIPB Bridge All peripherals can send data back on a dedicated bus (one bus per peripheral—8-, 16-, or 32-bit according to each peripheral requirement), either to the MPU or to the DSP.
Page 977 Layer 4 Interconnect 2.4.3 Conflicting Transaction When one host requires an access to the peripheral, an enable host signal is set (synchronously with the host strobe). With the DSP TIPB bridge strobe, a DSP TIPB bridge enable is generated, and with the MPU TIPB bridge strobe an MPU TIPB bridge enable is generated.
Page 978 Layer 4 Interconnect Static Switch Figure 6. Static Switch for OCP Peripheral SSW−DSP−CONF SSW−MPU−CONF register register allocation module TIPB bridge TIPB to peripheral Interface TIPB bridge OCP to TIPB interface Synchronization with MPU_STROBE *Default values Synchronization with DSP_STROBE Note: Default value: To simplify the TIPB router implementation and reduce the toggling on buses, a default value is returned to the host which does not access the peripheral.
Page 979 Layer 4 Interconnect To perform an MPU access, the MPU software must first set (write 1) the SWITCH bit in the SSW_MPU_CONF register. Then all the MPU TIPB bus signals are connected either to the TIPB bus peripheral signals (for a TIPB peripheral), or to the dedicated wrapper TIPB bus interface (for OCP peripheral).
Page 980 Layer 4 Interconnect Depending on the host interface protocol for the peripheral, a dedicated wrapper is connected between the host and the peripheral bus. Two different peripheral protocols are supported: TIPB 2.5.1 Simultaneous Access Setting both the DSP SWITCH bit and MPU SWITCH bits is impossible, by design.
Page 981 Layer 4 Interconnect Table 6. Static Switch Configuration Registers Offset Addresses (Continued) Register Name # Bits Offset UART2_SSW_DSP_CONF UART3_SSW_MPU_CONF 16/32 0x040 UART3_SSW_DSP_CONF McBSP_SSW_MPU_CONF 16/32 0x090 McBSP_SSW_DSP_CONF I2C_SSW_MPU_CONF 16/32 0x0A0 I2C_SSW_DSP_CONF SPI_SSW_MPU_CONF 16/32 0x0B0 SPI_SSW_DSP_CONF TIMER1_SSW_MPU_CONF 16/32 0x0C0 TIMER1_SSW_DSP_CONF TIMER2_SSW_MPU_CONF 16/32 0x0D0 TIMER2_SSW_DSP_CONF TIMER3_SSW_MPU_CONF...
Page 982 Layer 4 Interconnect Table 6. Static Switch Configuration Registers Offset Addresses (Continued) Register Name # Bits Offset NFCtrl_SSW_DSP_CONF MMCSD2_SSW_MPU_CONF 16/32 0x160 MMCSD2_SSW_DSP_CONF For each static-shared peripheral, two registers are defined (Table 7 and Table 8): one is dedicated to MPU accesses, and the other to DSP accesses. Table 7.
Page 983 Layer 4 Interconnect 2.7.1 Reset Methodology An MPU or a DSP initiator reset is always used internally by the static switch. A reset on the static switch configuration register resets the DSP_SWITCH bit and sets the MPU SWITCH bit, which turns the static switch in the MPU position.
Page 984: Tipb-Ocp/Ocp-Tipb Wrapper For Usbotg
Layer 4 Interconnect 2.9.3 MPU TIPB to OCP This wrapper is sensitive to MPU watchdog reset or MPU peripheral reset in order to clear the internal state machine. 2.10 TIPB-OCP/OCP-TIPB Wrapper for USBOTG The synchronous OCP protocol requires a free-running clock and synchronous signals relative to this clock.
Page 985 Layer 4 Interconnect 2.11 TIPB Router Figure 7. TIPB Router Block Diagram L4_HOST_CS [4:0] L4_PERIPH_DI [31:0] L4_PERIPH_OE L4_PERIPH_READY L4_PERIPH_PERHMAS [1:0] L4_HOST_OE L4_HOST_DI [31:0] TIPB L4_HOST_READY Up to 32 peripherals router L4_HOST_PERHMAS [1:0] L4_PERIPH_DI [31:0] L4_PERIPH_OE L4_PERIPH_READY L4_PERIPH_PERHMAS [1:0] The TIPB router is a simple multiplexer that returns information coming from peripherals to the host (DSP or MPU).
Page 986: Tipb Router
3 DSP level 2 TIPB Byte − − Private DSP interrupt handler ULPD (clock TIPB Byte − − Private MPU and reset) OMAP5912 TIPB Byte − − Private MPU configuration Secure Wrapper Byte − Private MPU watchdog 32-kHz Wrapper Byte −...
Page 987 Layer 4 Interconnect Table 10. MPU Peripherals Connected to the MPU Shared TIPB Bridge Instantiation OMAP 5912 Peripheral Interface Instantiation TIPB Router Access Size Access Size Address Bus Address Bus Alignment Data HDQ/1-Wire TIPB Byte − − Shared MPU µWIRE TIPB Byte −...
Page 988: Ocp Interconnect
OCP Interconnect Table 11. DSP Peripherals Connected to the DSP Shared TIPB Bridge Instantiation OMAP 5912 Peripheral Interface Instantiation TIPB Router Access Size Access Size Address Bus Address Bus alignment Data 2 x MCSI TIPB Byte − − Shared DSP 2 x McBSP Wrapper OCP Byte...
Page 989 OCP Interconnect SSI DMA transfers are handled by the generic distributed DMA (GDD). Because the SSI uses a proprietary bus interface (versatile interconnection architecture (VIA)), bridges are implemented in the SSI interconnect to perform data transfers between the SSI VIA bus and the OMAP3.2 OCP bus. VLYNQ is also a full duplex interface, using a VBUS 1.0 protocol.
Page 990 OCP Interconnect All interfaces are 32-bit data width and support burst and nonburst operations. Because the OMAP OCP_I port does not support split bursts, the buffer block translates split burst (master can insert wait states between valid commands during burst) into a simple burst action (the master cannot insert wait states between valid commands during burst).
Page 991 OCP Interconnect Module Features The OCP interconnect arbiter provides the following features: One OCP master port 32-bit width, 1x balanced clock, 4x32 (FOUR-TWO-TWO-LAST incremented burst only) nonsplit burst and nonburst accesses (OMAP OCP_I interconnect) One OCP slave port 32-bit width, 1x balanced clock, 4x32 split burst and nonburst accesses (GDD OCP_I interconnect) One OCP slave port 32-bit width, 1/2x balanced clock, 4x32 split burst and nonburst accesses (USB_OTG OCP_I interconnect)
Page 992: 1X Ocp Master Port
OCP Interconnect 1x OCP Master Port The OCP interconnect arbiter 1x OCP master port has the following features: OCP interface (master) Synchronous Balanced 100-MHz clock 32-bit data width only Support 4x32 burst (4−2−2−LAST only) and non-burst accesses Non-split burst only This port is directly connected to the OMAP OCP_I slave interface.
Page 993: Ssi Interconnect
OMAP OCP_I interface. SSI Interconnect Introduction The SSI interconnect manages accesses to OMAP5912 peripherals through GDD, acting as a bridge between external serial peripherals (using VIA buses) and the internal parallel bus (OCP). On one side it is connected to SSI, using two VIA buses, and on the other to GDD, using an OCP bus (see Figure 9).
Page 994: Ocp To Via Asynchronous Bridge
SSI Interconnect Clock and reset module The clock and reset module manages clock and reset signals for the SSI interconnect module and the SSI (SSR and SST) module. This module re- synchronizes reset signals and implements the AUTOIDLE mechanism for the SSI interconnect module. Figure 10.
Page 995: Ocp To Via Synchronous Bridge
SSI Interconnect OCP to VIA Synchronous Bridge OCP to the VIA synchronous bridge is a connection bridge between an OCP bus and a VIA bus. This submodule is a target on the OCP bus and a master on the VIA bus. On the OCP part, this bridge provides only basic functionality signals plus slave error.
Page 996: Clock And Reset Module
Bit [25] of MOD_CONF_CTRL_1 in OMAP5912 configuration enables the OCP interconnect to use its autoidle features. Reset value is 0x1. Bit [26] of MOD_CONF_CTRL_1 in OMAP5912 configuration enables the SSI interconnect to use its autoidle features. Reset value is 0x1.
Page 997 Secure ROM and RAM initial read latency (TC cycles) @100 MHz Secure ROM and RAM access clock cycles in (TC cycles) @ 100 MHz † ‡ Datum per cycle func (memory type) OMAP5912 Peripherals GDD functional clock (ns) SSR functional/interface clock (ns) SST functional/interface clock (ns) VLYNQ clock (ns) Computing †...
Page 998 On-Chip/Off-Chip Memory and Peripheral Access Latencies Table 15. OMAP3.2 Timing Parameters (Continued) System DMA clock (ns) DSP DMA clock (ns) CCP clock (ns) CCP cycle † Timing parameters are calculated for a mobile DDR. ‡ Timing parameters are calculated for a standard SDRAM. Table 16 lists access time calculations for different class of peripherals.
Page 999 On-Chip/Off-Chip Memory and Peripheral Access Latencies Table 16. Peripheral Access Time Calculations (Continued) Burst Read Single Read Single Write Line Fill First Data initiato initiator initiato initiator cycles cycles cycles cycles OCP-T2 Peripherals MPU to SSR Read MPU to SST Write OCP-I Interconnect MPU to GDD Read/write...
Page 1000 On-Chip/Off-Chip Memory and Peripheral Access Latencies Table 16. Peripheral Access Time Calculations (Continued) Burst Read Single Read Single Write Line Fill First Data GDMA Accesses GDMA GDMA pipeline pipeline latency latency(initial, intermediate, close) GDMA From request peripheral to 4*32-bit latency read from §...