Write Mode Selection - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Write Mode Selection

The CPU cannot serve interrupts, increasing the interrupt latency.

An interconnect including time-out logic to detect erroneous transactions

can generate an unwanted system abort event.

This stall period can be quantified as follows:

T (stall) = 3 MPU peripheral clocks + 5 timer clocks

The same full resynchronization scheme is used for a read transaction. The

same stall period applies.

A register read following a write to the same register is always coherent.

This mode is functional regardless of the ratio between the OCP interface

frequency and the functional clock frequency.

The choice between the synchronization modes must consider the frequency

ratio and the stall periods that can be supported by the system without affecting

the global performance.

Dual-Mode Timer

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