On-Chip Memory; Power Conservation - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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On-Chip Memory

Unified program/data memory architecture

Dual 17-bit x17-bit multipliers coupled to 40-bit dedicated adders for

non-pipelined single-cycle multiply accumulate (MAC) operations

Add/compare/select (CSSU) unit for the add/compare section of the

Viterbi operator

Exponent encoder to compute an exponent value of a 40-bit accumulator

value in a single cycle

Two address generators with eight auxiliary registers and two auxiliary

8M x 16-bit (16M bytes) total addressable memory space

Single-instruction repeat or block repeat operations for program code

Conditional execution

Seven-stage pipeline for high instruction throughput

Instruction buffer unit that loads, parses, queues, and decodes

instructions to decouple the program fetch function from the pipeline

Program flow unit that coordinates program actions among multiple

parallel CPU functional units

Address data flow unit that provides data address generation and includes

a 16-bit arithmetic unit capable of performing arithmetic, logical, shift, and

saturation operations

Data computation unit containing the primary computation units of the

CPU, including a 40-bit arithmetic logic unit, two MAC units, and a shifter

Features include:

DARAM that supports two memory accesses per cycle per block

SARAM that supports one memory access per cycle per block

PDROM that provides nonvolatile storage for program or data

Features include:

TMS320C55x DSP CPU Overview

DSP Subsystem

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