Table of Contents
Advertisement
Figure 3.
Release of LOW_PWR
CLK32K_IN
CK_REF
ULPD_STATE
LOW_PWR
System clock request
Must be OMAP wake
up or a peripheral
request
1.6.2
Behavior of LOW_PWR
1.7
Leakage Current Management
SPRU753A
Deep sleep
The LOW_PWR signal is used in oscillator clock mode to control an external
power management device.
When high, the signal LOW_PWR drives the external core voltage supply in
low voltage (1.1 V) operations.
LOW_PWR can be set by software so that two types of operations are allowed:
-
Reduction of leakage current
-
Low-voltage operation at reduced clock frequency, also known as
dynamic voltage scaling (DVS)
The conditions below cause the listed events:
-
POWER_CTRL_REG[0] set to 1: Enable LOW_PWR feature
-
POWER_CTRL_REG[4] set to 1: Enable transition to deep sleep mode
or
POWER_CTRL_REG[10] set to 0: DVS disabled
LOW_PWR switches to active high whenever the ULPD enters deep sleep
state. In this way, the external core voltage supply can be driven in low-voltage
operation by the external power management device.
When the ULPD exits deep sleep mode, LOW_PWR switches back to inactive
low and the external core voltage supply ramps up to a nominal 1.5 V.
Awake sequence
Power Management
Ultralow-Power Device
Awake state
21
Advertisement
Chapters
Table of Contents
