3
MicroWire Interface
Figure 34.
Block Diagram
MPU_PER_CLK
Clock
enable
Setup register
Control and status
register
TIPB
3.1
MicroWire Registers
Table 38. MicroWire Registers
Register
Description
TDR
Transmit data
RDR
Receive data
CSR
Control and status
SR1
Setup 1
SR2
Setup 2
SR3
Setup 3
SR4
Setup 4
SR5
Setup 5
SPRU760B
This serial synchronous interface can drive up to four serial external
components. For the external devices, this interface is compatible with the
µWire standard and is seen as the master (see Figure 34).
A transmit DMA mode is available.
Clock register
Clock
divide
Control
logic
UWIRE.CS[3:0]
Start address in the peripheral range (hex): FFFB:3000
Table 38 lists the MicroWire registers. Table 39 through Table 46 describe the
individual registers.
DMA_REQ to system DMA_REQ[6:0]
2
Inth lvl2 (2,3) - edge
Transmit data register
Receive data register
UWIRE.SCLK
R/W
Size
W
16 bits
R
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
MicroWire Interface
UWIRE.SDO
(16 bits)
UWIRE.SDI
(16 bits)
Address
Offset
FFFB:3000
0x00
FFFB:3000
0x00
FFFB:3000
0x04
FFFB:3000
0x08
FFFB:3000
0x0C
FFFB:3000
0x10
FFFB:3000
0x14
FFFB:3000
0x18
Serial Interfaces
99