External 32-Khz Clock With Reset Mode 1 - Texas Instruments OMAP5912 Reference Manual

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External 32-kHz Clock with Reset Mode 1

External CMOS Clock Connections (Reset Mode 1)

32kHz Ext. CMOS clk

19.2 MHz external

The OSC1_IN pin (ball Y2) must be driven to VSS either by a pulldown

or tied directly.

The OSC1_OUT pin (ball W3) must be left unconnected.

Software considerations:

Before setting the COMP_MODE_CTRL_0 register to 0x0000EAEF,

the FUNC_MUX_CTRL_D(2:0) register bits must be set to 110 to

ensure that ball Y4 is pin multiplexed as the SYS_CLK_IN.

The ULPD OSC1 delay timer is bypassed in reset mode 1.

Consequently, there is no delay in the ULPD due to the delay timer.

If CONF_OSC1_GZ_R = 1, the OSC1_IN pin requires a pulldown,

because it is configured as output.

The OMAP5912 32-kHz clock can be driven by an external clock. See

Figure 12 for the hardware connections of the external 32-kHz clock. This

figure applies to reset mode 1 only.

Hardware considerations:

The external clock is applied to the CLK32K_IN pin (ball P13).

OSC32K_IN must be tied to CVDDRTC.

OSC32K_OUT must be tied to VSS.

Software considerations:

Set OSC32K_PWRDN_R to 1 in RTC_OSC_REG for power-saving

CMOS clk only

OMAP5912 Clock Architecture

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