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Texas Instruments TMS320C6201 Manuals
Manuals and User Guides for Texas Instruments TMS320C6201. We have
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Texas Instruments TMS320C6201 manuals available for free PDF download: Reference Manual, Manual, Errata
Texas Instruments TMS320C6201 Reference Manual (477 pages)
TMS320C6000 series Peripherals
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 2.15 MB
Table of Contents
Table of Contents
11
Read this First
3
Figures
15
Table of Contents
21
Typical Applications for the TMS320 Dsps
27
TMS320C6000 Peripherals
32
TMS320C6201/C6202/C6701 Block Diagram
33
TMS320C6211/C6711 Block Diagram
34
Tms320C6201/C6701
37
TMS320C6201/C6701 Program Memory Controller in the Block Diagram
38
Internal Program Memory Mode Summary
40
Logical Mapping of Cache Address
41
Tms320C6X Block Diagram
43
Data Memory Access
44
Data Memory Organization (TMS320C6201 Revision 2)
45
Data Memory Controller Interconnect to Other Banks (TMS320C6201 Revision 2)
46
Data Memory Organization (TMS320C6201 Revision 3)
47
Data Memory Controller Interconnect to Other Banks (TMS320C6201 Revision 3)
48
Conflicting Internal Memory Accesses to the same Block
52
(TMS320C6201 Revisions 2 and 3)
52
Register Contents after Little-Endian or Big-Endian Data Loads
55
(TMS320C6201 and TMS320C6701)
55
(TMS320C6701 Only)
56
Memory Contents after Little-Endian or Big-Endian Data Stores
56
Peripheral Bus
57
TMS320C6201/C6701/C6202 Cache Architectures
60
TMS320C6202 Program Memory Controller Block Diagram
61
TMS320C6201/C6701/C6202 Internal Memory Configurations
60
Internal Program RAM Address Mapping in Cache Mode
63
Cache Operation
63
TMS320C6202 Data Memory Controller Block Diagram
65
TMS320C6211/C6711 Block Diagram
67
TMS320C6211/C6711 Cache Architectures
67
TMS320C6211 Internal Memory Block Diagram
68
TMS320C6711 Internal Memory Block Diagram
69
TMS320C6211/C6711 Internal Memory Configurations
67
Internal Memory Control Register Addresses
70
L1P Direct Mapped Cache Diagram
72
L1P Flush Base Address Register Fields (L1PFBAR)
73
L1P Flush Word Count Register Fields (L1PFWC)
73
L1D Address Allocation
74
Level 1 Data Cache Mode Settings
75
L1D 2-Way Set Associative Cache Diagram
76
L1D Flush Base Address Register Fields (L1DFBAR)
77
L1D Flush Word Count Register Fields (L1DFWC)
77
Cache Configuration Register Fields (CCFG)
78
L2 Memory Configuration
79
L2 Cache Data Request Flow Chart
82
L2 CE Space Allocation Register Fields
83
Memory Attribute Register Functions
85
L2 Flush Register Fields (L2FLUSH)
87
L2 Clean Register Fields (L2CLEAN)
87
L2 Flush Base Address Register Fields (L2FBAR)
87
L2 Clean Register Fields Description
87
L2 Flush Word Count Register Fields (L2FWC)
88
L2 Clean Base Address Register Fields (L2CBAR)
88
L2 Clean Word Count Register Fields (L2CWC)
88
DMA Controller Interconnect to TMS320C6201/C6202/C6701 Memory-Mapped Modules
92
Dma Registers
93
L2 Flush Register Fields Description
87
DMA Control Registers by Address
94
DMA Control Registers by Register Name
95
DMA Channel Primary Control Register
96
DMA Channel Primary Control Register Field Descriptions
96
DMA Channel Secondary Control Register
98
DMA Channel Secondary Control Register Field Descriptions
98
TMS320C6202 Secondary Control Register
99
Synchronization Configuration Options
99
Memory Map
100
DMA Global Count Reload Register Used as Transfer Counter Reload
104
Synchronization Events
105
Synchronization Flags
108
DMA Channel Source Address Register
110
DMA Channel Destination Address Register
110
Address Generation
110
DMA Global Index Register
111
Sorting Example in Order of DMA Transfers
114
Sorting in Order of First by Address
115
DMA Global Address Register Used for Split Address
117
DMA Auxiliary Control Register
119
DMA Auxiliary Control Register Field Descriptions
119
Generation of DMA Interrupt for Channel X from Conditions
121
DMA Channel Condition Descriptions
122
DMA Controller Data Bus Block Diagram
123
TMS320C6211/C6711 Block Diagram
128
EDMA Controller
129
Event Register
133
Event Enable Register (EER)
133
EDMA Parameter RAM Contents
136
Parameter Storage for an EDMA Event
138
EDMA Channel Association with Sync Events
144
Non-2D R/W Sync EDMA Transfer Without Frame Sync
147
Non-2D EDMA Transfer with Frame Sync
148
Read/Write Synchronized 2-D Transfer (no Frame Sync)
149
Frame Synchronized 2-D Transfer
149
Link Conditions
152
EDMA Element and Frame/Array Count Updates
154
EDMA SRC Address Parameter Updates
156
EDMA DST Address Parameter Updates
157
Transfer Complete Code (TCC) to DMA Interrupt Mapping
159
Channel Chain Enable Register (CCER)
161
Priority Queue Status Register(PQSR)
163
TMS320C6211/C6711 Block Diagram
170
HPI Block Diagram
171
HPI Block Diagram of TMS320C6211/C6711
172
HPI External Interface Signals
174
HPI Data Write Access
175
HPI Input Control Signals Function Selection Descriptions
175
Byte Enables for HPI Data Write Access
177
Select Input Logic
178
HPI Read Timing (HAS Not Used, Tied High)
181
HPI Read Timing (HAS Used)
181
HPI Write Timing (HAS Not Used, Tied High)
182
HPI Write Timing (HAS Used)
182
HPI Registers
183
HPIC Register
184
HPI Control Register (HPIC) Bit Descriptions
184
Initialization of HWOB = 1 and HPIA
186
Initialization of HWOB = 0 and HPIA
187
Data Read Access to HPI Without Autoincrement: HWOB
188
Read Access to HPI with Autoincrement: HWOB
189
Read Access to HPI with Autoincrement: HWOB
190
Data Write Access to HPI Without Autoincrement: HWOB
191
Write Access to HPI with Autoincrement: HWOB
192
Write Access to HPI with Autoincrement: HWOB
193
The Expansion Bus Interface in the TMS320C6202 Block Diagram
198
Expansion Bus Signals
199
Expansion Bus Memory Mapped Registers
200
Expansion Bus Host Port Registers
201
Expansion Bus Global Control Register
202
Expansion Bus Global Control Register Field Description
202
XCE Space Control Registers
203
Expansion Bus XCE(0/1/2/3) Space Control Register Diagram
203
Expansion Bus XCE(0/1/2/3) Space Control Register Field Description
203
8.4 Expansion Bus I/O Port Operation
204
Example of the Expansion Bus Interface to Four 8-Bit Fifos
205
Addressing Scheme - Case When Expansion Bus Is Interfaced to Four 8-Bit Fifos
205
Asynchronous Mode
206
Addressing Scheme - Case When the Expansion Bus Is Interfaced to Two 16-Bit Fifos
206
Synch FIFO Modes
207
Synch FIFO Pin Description
208
Glueless Write FIFO Interface
209
Read and Write FIFO Interface with Glue
210
FIFO Write Cycles
210
Glueless Read FIFO Interface
211
FIFO Read Mode - Read Timing (Glueless Case)
211
FIFO Read Mode - with Glue
212
DMA Transfer Examples
214
Content of Relevant Registers (Single Frame Transfer)
214
Content of DMA Channel Primary Control Register Fields
214
Content of Relevant Registers (Multiple Frame Transfer)
215
Content of TMS320C6202 DMA Primary Control Register
215
Content of TMS320C6202 DMA Secondary Control Register
215
8.5 Expansion Bus Host Port Operation
216
Expansion Bus Host Port Registers Description
217
Expansion Bus Data Register
217
Expansion Bus Internal Slave Address Register (XBISA)
217
XBISA Register Description
217
Expansion Bus External Address Register
218
Expansion Bus Host Port Interface Control (XBHC) Register
218
XBHC Register Description
219
Synchronous Host Port Mode
220
Expansion Bus Pin Description (Synchronous Host Port Mode)
220
Read Transfer Initiated by the TMS320C6202 and Throttled by
223
XWAIT and XRDY (Internal Bus Arbiter Disabled)
223
Write Transfer Initiated by the TMS320C6202 and Throttled by
225
XWAIT and XRDY (Internal Bus Arbiter Disabled)
225
External Device Requests the Bus from the TMS320C6202 Using XBOFF
227
The Expansion Bus Master Writes a Burst of Data to the TMS320C6202
231
The Bus Master Reads a Burst of Data from the TMS320C6202
233
Asynchronous Host Port Mode
235
Timing Diagrams for Asynchronous Host Port Mode of the Expansion Bus
237
8.6 Expansion Bus Arbitration
238
Internal Bus Arbiter Enabled
238
XARB Bit Value and XHOLD/XHOLDA Signal Functionality
238
Internal Bus Arbiter Disabled
239
(Internal Bus Arbiter Disabled)
239
Timing Diagrams for Bus Arbitration-XHOLD/XHOLDA
239
(Internal Bus Arbiter Enabled)
239
XHOLD Timing When the External Host Starts a Transfer to DSP Instead of
240
Granting the DSP Access to the Expansion Bus(Internal Bus Arbiter Disabled)
240
Possible Expansion Bus Arbitration Scenarios (Internal Bus Arbiter Disabled)
240
Expansion Bus Requestor Priority
242
8.7 Boot Configuration Control Via Expansion Bus
243
Resistors on
244
External Memory Interface
245
9.1 Overview
246
TMS320C6201/C6701 External Memory Interface
248
TMS320C6202 External Memory Interface
249
TMS320C6211/C6711 External Memory Interface
250
EMIF Signal Descriptions
251
9.2 Resetting the EMIF
252
9.3 EMIF Registers
253
Global Control Register
253
EMIF Memory-Mapped Registers
253
EMIF Global Control Register Field Descriptions
254
EMIF CE Space Control Registers
256
TMS320C6201/C6202/C6701 EMIF CE Space Control Register Diagram
256
TMS320C6211/C6711 EMIF CE Space Control Register
256
EMIF CE Space Control Registers Field Descriptions
257
TMS320C6211/C6711 Byte Alignment by Endianness
258
EMIF SDRAM Control Register
259
TMS320C6201/C6202/C6701 EMIF SDRAM Control Register
259
TMS320C6211/C6711 EMIF SDRAM Control Register
259
EMIF SDRAM Timing Register
261
EMIFSDRAM Timing Register Field Descriptions
261
TMS320C6211/C6711 SDRAM Extension Register
262
TMS320C6211/C6711 SDRAM Extension Register Field Descriptions
263
9.4 SDRAM Interface
264
TMS320C6201/C6202/C6701 EMIF SDRAM Commands
264
TMS320C6201/C6202/C6701 EMIF to 16M-Bit SDRAM Interface
265
TMS320C6211/C6711 EMIF to 16M-Bit SDRAM Interface
265
TMS320C6201/C6202/C6701 EMIF to 64M-Bit SDRAM Interface
266
TMS320C6201/C6202/C6701 SDRAM Memory Population
266
SDRAM Control Pins
267
SDRAM Initialization
269
Monitoring Page Boundaries
269
SDRAM Refresh
270
Mode Register Set
272
SDRAM Refresh
272
TMS320C6201/C6202/C6701 Mode Register Value
273
TMS320C6201/C6202/C6701 Implied SDRAM Configuration by MRS Value
273
TMS320C6211/C6711 Mode Register Value (0032H)
274
TMS320C6211/C6711 Mode Register Value (0022H)
274
TMS320C6211/C6711 Implied SDRAM Configuration by MRS
274
SDRAM Mode Register Set: MRS Command
275
Address Shift 9
276
TMS320C6201/C6202/C6701 Byte Address to EA Mapping for SDRAM RAS and CAS
276
Timing Requirements
278
TMS320C6201/C6202/C6701 SDRAM Timing Parameters
278
SDRAM Deactivation
279
SDRAM DCAB - Deactivate All Banks
279
TMS320C6211/C6711 SDRAM DEAC - Deactivate Single Bank
280
SDRAM Read
281
TMS3206201/C6202/C6701 SDRAM Read
281
TMS320C6211 SDRAM Read
282
SDRAM Write
283
TMS320C6201/C6202/C6701 SDRAM Three Word Write
283
TMS320C6211/C6711 SDRAM Three Word Write
284
9.4.10 TMS320C6211/C6711 Seamless Data Access
285
Burst Reads to 2 Pages of SDRAM
285
Seamless SDRAM Write
286
9.5 SBSRAM Interface
287
SBSRAM in Linear Burst Mode
287
TMS320C6201/C6202/C6701 SBSRAM Interface
288
TMS320C6211/C6711 SBSRAM Interface
288
SBSRAM Reads 9
289
SBSRAM Four-Word Read
289
EMIF SBSRAM Pins
289
TMS320C6211/C6711 SBSRAM Six-Word Read
290
SBSRAM Writes 9
291
TMS320C6201/C6202/C6701 SBSRAM Four Word Write
291
TMS320C6211/C6711 SBSRAM Write
292
9.6 Asynchronous Interface
293
EMIF Asynchronous Interface Pins
293
TMS6201/C6202/C6701 EMIF to 32-Bit SRAM Interface
294
TMS320C6211/C6711 EMIF to 16-Bit SRAM (Big Endian)
294
EMIF to 8-Bit ROM Interface
295
EMIF to 16-Bit ROM Interface
295
EMIF to 32-Bit ROM Interface
295
TMS320C6201/C6202/C6701 ROM Modes
296
Byte Address to EA Mapping for Asynchronous Memory Widths
296
Programmable ASRAM Parameters
297
Asynchronous Read Timing Example
299
Asynchronous Write Timing Example
301
TMS320C6201/C6202/C6701 Ready Operation
302
TMS320C6211/C6711 Ready Operation
303
TMS320C6201/C6202/C6701 EMIF Prioritization of Requests
305
TMS320C6211/C6711 EMIF Prioritization of Requests
306
Power down
308
Device Reset
310
Boot Configuration Summary
311
TMS320C6201/C6701 Memory Map Summary
313
TMS320C6211/C6711 Boot Configuration Summary
313
TMS320C6202 Memory Map Summary
314
TMS320C6211/C6711 Memory Map Summary
315
DLL Multiplier Select
318
Device Configuration
318
Mcbsp Block Diagram
321
Mcbsp Interface Signals
323
Mcbsp Registers
324
TMS320C6211/C6711 Data Receive and Transmit Registers (DRR/DXR) Mapping
324
Mcbsp CPU Interrupts and DMA Synchronization Events
325
Serial Port Control Register (SPCR)
326
Serial Port Control Register (SPCR) Field Descriptions
326
Pin Control Register (PCR)
329
Pin Control Register (PCR) Field Descriptions
329
Receive Control Register (RCR)
332
Receive/Transmit Control Register (RCR/XCR) Field Descriptions
333
Reset State of Mcbsp Pins
337
Frame and Clock Operation
341
Receive Data Clocking
343
Dual-Phase Frame Example
344
RCR/XCR Fields Controlling Elements Per Frame and Bits Per Element
344
Inter-IC Sound (IIS) Timing
345
Mcbsp Receive/Transmit Frame Length 1/2 Configuration
345
Mcbsp Receive/Transmit Element Length Configuration
346
Single-Phase Frame of Four 8-Bit Elements
347
Receive Operation
352
Timer Registers
409
Timer Interrupts
416
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Texas Instruments TMS320C6201 Errata (29 pages)
Digital Signal Processor Silicon Errata
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0.29 MB
Table of Contents
Table of Contents
2
1 Introduction
4
Quality and Reliability Conditions
4
TMX Definition
4
TMP Definition
4
TMS Definition
4
Revision Identification
5
2 Changes to the TMS320C6201 Data Sheet (Literature Number SPRS051)
6
3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications
8
Advisory 3.1.1
8
Issues When Pausing at a Block Boundary
8
DMA: Transfer Incomplete When Pausing a Synchronized Transfer in MID-Frame
8
Advisory 3.1.3
9
DMA Multiframe Split-Mode Transfers Source Address Indexing Not Functional
9
DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync
9
DMA Freezes if Postincrement/Decrement Across Port Boundary
9
Advisory 3.1.6
10
DMA Paused During Emulation Halt
10
DMA: RSYNC = 10000B (DSPINT) Does Not Wait for Sync
10
EMIF: Invalid SDRAM Access to Last 1K Byte of CE3
10
Advisory
11
Cache During Emulation with Extremely Slow External Memory
11
4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications
12
Advisory 3.0.8
12
EMIF: Inverted SDCLK and SSCLK at Speeds above 175 Mhz
12
Advisory 3.0.9
14
CPU: L2-Unit Long Instructions Corrupted During Interrupt
14
5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications
15
Advisory 2.1.1
15
EMIF: CE Space Crossing on Continuous Request Not Allowed
15
EMIF: SDRAM Invalid Access
15
Advisory 2.1.4
16
DMA: RSYNC Cleared Late for Frame-Synchronized Transfer
16
Mcbsp: DXR to XSR Copy Not Generated
16
Advisory 2.1.6
18
DMA Split-Mode End-Of-Frame Indexing
18
Advisory 2.1.8
19
DMA Channel 0 Multiframe Split-Mode Incompletion
19
Timer Clock Output Not Driven for External Clock
19
Power-Down Pin PD Not Set High for Power-Down 2 Mode
19
Advisory 2.1.10 EMIF: RBTR8 Bit Not Functional
19
Advisory 2.1.11 Mcbsp: Incorrect Mlaw Companding Value
20
Advisory 2.1.12 False Cache Hit - Extremely Rare
20
Advisory 2.1.13 EMIF: HOLD Feature Improvement on Revision 3
20
Advisory 2.1.14 EMIF: HOLD Request Causes Problems with SDRAM Refresh
21
Advisory 2.1.15 DMA Priority Ignored by PBUS
21
Advisory 2.1.16 DMA Split-Mode Receive Transfer Incomplete after Pause
22
Advisory 2.1.17 DMA Multiframe Transfer Data Lost During Stop
22
Advisory 2.1.18 Bootload: HPI Feature Improvement on Revision 3
22
Advisory 2.1.19 PMEMC: Branch from External to Internal
23
Advisory 2.1.21 DMA: DMA Data Block Corrupted after Start Zero Transfer Count
23
6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications
24
Advisory
24
Program Fetch: Cache Modes Not Functional
24
Bootload: Boot from 16-Bit and 32-Bit Asynchronous Roms Not Functional
24
DMA Channel 0 Split Mode Combined with Autoinitialization Performs Improper Reinitialization
24
Dma/Program Fetch: Cannot DMA into Program Memory from External
24
Advisory 2.0.5
25
Sequenced Wrong
25
EMIF: Reserved Fields Have Incorrect Values
25
EMIF: SDRAM Refresh/Dcab Not Performed Prior to HOLD Request Being Granted
25
Advisory 2.0.9
26
Mcbsp New Block Interrupt Does Not Occur for Start of Block 0
26
Advisory 2.0.11 Dma/Internal Data Memory: First Load Data Corrupted When DMA in High Priority
26
Advisory 2.0.12 Mcbsp: FRST Improved in 2.1 over 2.0
26
Advisory 2.0.13 Mcbsp: XEMPTY Stays Low When DXR Written Late
27
Advisory 2.0.14 EMIF: Multiple SDRAM CE Spaces: Invalid Access after Refresh
27
Advisory 2.0.18 Dma/Internal Data Memory: Conflict Data Corruption
27
Advisory 2.0.19 EMIF: Data Setup Times
28
Advisory 2.0.24 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur
28
7 Documentation Support
28
Texas Instruments TMS320C6201 Manual (70 pages)
FIXED-POINT DIGITAL SIGNAL PROCESSOR
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1.08 MB
Table of Contents
GJC/GJL BGA Packages (Bottom View)
1
Table of Contents
2
Description
2
Device Characteristics
3
Functional and CPU (DSP Core) Block Diagram
4
CPU (DSP Core) Description
5
Signal Groups Description
7
Signal Descriptions
9
Development Support
20
Documentation Support
23
Clock PLL
24
Power-Down Mode Logic
25
Power-Supply Sequencing
27
Absolute Maximum Ratings over Operating Case Temperature Ranges
28
Recommended Operating Conditions
28
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature
29
Parameter Measurement Information
30
Input and Output Clocks
31
Asynchronous Memory Timing
33
Synchronous-Burst Memory Timing
35
Synchronous DRAM Timing
39
HOLD/HOLDA Timing
43
Reset Timing
44
External Interrupt Timing
46
Host-Port Interface Timing
47
Multichannel Buffered Serial Port Timing
50
DMAC, Timer, Power-Down Timing
61
JTAG Test-Port Timing
62
Revision History
63
Thermal/Mechanical Data
64
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