Dma Debug State - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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DMA Debug State

Other Logical Channel Features

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During debug mode the MPU can send a request to suspend the DMA. This

is useful if, for instance, the MPU is halted by a breakpoint. How the system

DMA responds to this request is controlled by software by configuring the

FREE bit in the DMA global control register, DMA_GCR. When the FREE bit

is set to 0, all current transfers are suspended when a request is received from

the MPU. The transfers resume when the MPU releases the debug request

signal. If the FREE bit is set to 1, the DMA continues to run as usual, even if

the MPU is sending a debug request signal. The channel status of the DMA

interrupts is read on the DMA_CSR register bits. In contrast with the functional

mode, the DMA_CSR bits are not cleared after an emulation read.

The LCh-G type channel not only transfers data, but also provides hardware

with 2-D graphic data processing features to improve 2-D graphic processing

speed and graphic quality. It supports the following graphic features:

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Constant fill (or constant solid color fill)

LCh-2D also supports constant fill and rotation. Rotation is supported by all

LCh types supporting separate element and frame indexed addressing (2

dimension addressing).

LCh Types Supporting this Feature

It is often desirable to transfer irregular shapes, especially in software for

games. The system DMA supports the COLOR KEY feature for 8 BPP, 16 BPP,

and 32 BPP from source to destination; that is, each element of channel

source is compared to a color key and those data bits (pixels) that match the

color key are not written to the destination.

Direct Memory Access (DMA) Support

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