Multiplane - Texas Instruments OMAP5912 Reference Manual

Memory Interfaces for the EMIFS
Figure 3. Write Operation
While writing, accumulate the
column and row parities for ECC
computation. ECC is
accumulated and stored in
NND_ECCx registers.
Bit 6 is the ready/busy bit
Bit 0 indicates that program
Write ECC in spare area
2.1.3 Multiplane Page Program
26 Memory Interfaces
Write start address, NND_ADDR_SRC
Write 0x00, NND_COMMAND_SEC
Write 0x01, NND_COMMAND_SEC
Write 0x50, NND_COMMAND_SEC
Write 0x80, NND_COMMAND
Write data, NND_ACCESS
Write 0x10, NND_COMMAND_SEC
Write 0x70, NND_COMMAND_SEC
Status = read NND_ACCESS
operation has been
succesfully done.
The multiplane page program is an extension of the page program operation
in which up to four pages (and for each page, up to 528 bytes) are
programmed. This operation is available only on 512M-bit and 1G-bit NFMCs.
For the 1G-bit NFMC, multiplane page programming accesses pages in plane
0, 1, 2, and 3 or plane 4, 5, 6, and 7.
Start program
or
or
NO
bit 6 = 1 ?
YES
YES
bit 0 = 1 ?
NO
End program
To select the area:
0x00: 0−255
0x01: 256−511
0x50: 512−527
Writing to this register,
sends also the address
to the flash core
The access to
NND_ACCESS will trigger
the WE_ SIGNAL to the NAND
flash.
This reads the status register
of the flash core.
Flash core is busy
programming the data
Program error
SPRU756A