Mcsi1 Interrupt Mapping - Texas Instruments OMAP5912 Reference Manual

MCSI1 and MCSI2
Figure 58. MCSI1 Interface
DSP
DMA
Frame error (IRQ_10)
DSP level 2
interrupt handler
System
DMA
MPU level 2
interrupt handler
DSP peripheral
bridge
Clock generation
and management
5.2

MCSI1 Interrupt Mapping

138 Serial Interfaces
TX (DMA_REQ_1)
RX (DMA_REQ_2)
TX interrupt (IRQ_6)
RX interrupt (IRQ_7)
TX (DMA_REQ_1)
RX (DMA_REQ_2)
TX/RX/frame error
Interrupt (IRQ_16)
DSP public
peripheral bus 16
DSPPER_nRST
PWRON_RESET
DSPXOR_CK
Table 57 identifies the MCSI1 interrupt mappings. MCSI1 generates level-2
interrupts for both the DSP and the MPU. Only one MPU MCSI1 interrupt
covers TX, RX, and frame error conditions; software must check the MCSI1
status register to determine the interrupt source.
MCSI1
clk_out
DMA
requests
Clk_out_z
clk_in
Fsynch_out
Fsynch_out_z
Fsynch_in
Interrupts
txd
txd_z
Rxd
MPU
I/F
vfsrx
Reset
OMAP5912
MCSI1.CLK
MCSI1.SYNC
MCSI1.DOUT
0
MCSI1.DIN
Tie-off
SPRU760B