Tipb Bridge - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Table 12. DSP Peripheral Mapping (Continued)

Start Byte Address (hex)

† All other I/O memory addresses are reserved.

‡ Internal wait states for accessing peripherals are set by strobe fields in TIPB CM register (see Section 4.1, Control Mode

TIPB Bridge

32-kHz synchronization timer

OMAP5912 TIPB switch

MGS3 MPUI control register

The TIPB bridge module manages access to peripheral control and data

registers by the DSP CPU, DSP DMA controller, and MPUI via two peripheral

buses (see Figure 10):

Private TIPB: peripherals connected here (timers and interrupt handler)

cannot be accessed by the MPU via the MPUI.

Public TIPB: peripherals connected here (McBSP1, McBSP2, MCSI1,

MCSI2, mailbox, and GPIO UART1-3) can be accessed by the MPU via

the MPUI port.

The TIPB bridge consists of two components:

DSP Subsystem

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