Omap 3.2 Resets - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Global Resets (Continued)

OMAP 3.2 Resets

OMAP 3.2 Resets

DSP-MMU SW reset bit in CNTL_REG of DSP-MMU module must also be set correctly for DSP-MMU to be reset.

SDRAM is in self-refresh; some of the registers controlled by SDRAM FSM do not reset.

See Table 3 for a listing of all cold/warm resets.

DPLL is reset by

Reset Description

Reset the DSP, excluding the

configuration settings (config registers

of EMIF internal to DSP and the MPUI

is cleared to

control logic internal to DSP).

Reset peripheral Class 3 modules.

is cleared to

Reset the priority registers (TIPB)

module, EMIF configuration register,

and the MPUI control logic in the DSP.

is set to 1.

In conjunction with the reset status register in OMAP3.2, the user can poll the

ULPD reset status register to determine whether the reset was caused by a

32K watchdog time-out. See Table 3.

Table 4 shows how OMAP3.2 components are affected by various reset

sources. The MPU and DSP peripheral resets are not included in this table as

they are not part of OMAP3.2 (see Table 5 for peripheral resets).

or 32-kHz WD. Other warm resets do not reset the DPLL.

Reset Architecture

DSP Software

Initialization

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