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Manuals and User Guides for Texas Instruments TMS320C3x. We have
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Texas Instruments TMS320C3x manual available for free PDF download: User Manual
Texas Instruments TMS320C3x User Manual (757 pages)
Texas Instruments Computer Hardware User's Guide
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
12
Read this First
3
Related Documentation from Texas Instruments
5
CPU Registers/Interrupt Latency
25
1 Introduction
30
Tms320C3X Devices
31
Tms320C30
32
TMS320C31 and TMS320LC31
32
Tms320C3X Key Specifications
32
Tms320C3X Devices Block Diagram
32
Tms320C32
33
TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison
34
Typical Applications
36
Typical Applications of the TMS320 Family
36
2 Architectural Overview
37
Overview
38
TMS320C30 Block Diagram
39
TMS320C31 Block Diagram
40
TMS320C32 Block Diagram
41
Central Processing Unit (CPU)
42
Floating-Point/Integer Multiplier
42
Central Processing Unit (CPU)
43
Arithmetic Logic Unit (ALU) and Internal Buses
44
Auxiliary Register Arithmetic Units (Araus)
44
Floating-Point/Integer Multiplier
44
CPU Primary Register File
45
Primary CPU Registers
45
Other Registers
48
Memory Organization
49
RAM, ROM, and Cache
49
Memory Organization of the TMS320C30
50
Memory Organization of the TMS320C31
51
Memory Organization of the TMS320C32
52
Memory Addressing Modes
53
Internal Bus Operation
54
External Memory Interface
55
TMS320C32 16- and 32-Bit Program Memory
55
TMS320C32 8-, 16-, and 32-Bit Data Memory
56
TMS320C32-Supported Data Types and Sizes and External Memory Widths
56
Interrupts
57
Peripherals
58
Peripheral Modules
58
Serial Ports
59
Timers
59
Direct Memory Access (DMA)
60
DMA Controller
61
TMS320C30, TMS320C31, and TMS320C32 Differences
62
Feature Set Comparison
63
CPU Registers
64
Cpu Multiport Register File
65
Extended-Precision Register Floating-Point Format
66
Extended-Precision Register Integer Format
66
Status (St) Register
68
Status Register (TMS320C30 Andtms320C31)
68
Status Register (TMS320C32 Only)
68
Status Register Bits
69
CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31)
72
CPU/DMA Interrupt-Enable (IE) Register (TMS320C32)
72
IE Bits and Functions
73
Cpu Interrupt Flag (If) Register
74
TMS320C30 CPU Interrupt Flag (IF) Register
75
TMS320C31 CPU Interrupt Flag (IF) Register
75
TMS320C32 CPU Interrupt Flag (IF) Register
75
IF Bits and Functions
76
Effective Base Address of the Interrupt-Trap Vector Table
77
Interrupt and Trap Vector Locations
78
I/O Flag (IOF) Register
79
IOF Bits and Functions
79
Reserved Bits and Compatibility
82
TMS320C30 Memory Maps
86
TMS320C31 Memory Maps
88
TMS320C32 Memory Maps
90
TMS320C30 Peripheral Bus Memory-Mapped Registers
92
TMS320C31 Peripheral Bus Memory-Mapped Registers
93
TMS320C32 Peripheral Bus Memory-Mapped Registers
95
Reset/Interrupt/Trap Vector Map
96
Reset, Interrupt, and Trap Vector Locations for the TMS320C30 Microprocessor Mode
97
Reset, Interrupt, and Trap Vector Locations for Thetms320C31 Microprocessor Mode
98
Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode
99
Interrupt and Trap Vector Locations for TMS320C32
100
Instruction Cache
101
Address Partitioning for Cache Control Algorithm
101
Instruction-Cache Architecture
102
Combined Effect of the CE and CF Bits
105
Integer Formats
107
Short-Integer Format and Sign-Extension of Short Integers
107
Single-Precision Integer Format
107
Unsigned-Integer Formats
108
Short Unsigned-Integer Format and Zero Fill
108
Single-Precision Unsigned-Integer Format
108
General Floating-Point Format
109
Floating-Point Format
109
Short Floating-Point Format
110
TMS320C32 Short Floating-Point Format for External 16-Bit Data
111
Single-Precision Floating-Point Format
112
Extended-Precision Floating-Point Format
113
Determining the Decimal Equivalent of a Tms320C3X
114
Conversion between Floating-Point Formats
117
Floating-Point Format
117
Converting from Short Floating-Point Format to Single-Precision Floating-Point Format
117
Converting from Short Floating-Point Format to Extended-Precision
117
Converting from Single-Precision Floating-Point Format to Extended-Precision
118
Converting from Extended-Precision Floating-Point Format to Single-Precision
118
Floating-Point Format
118
Floating-Point Conversion (IEEE Std. 754)
119
IEEE Single-Precision Std. 754 Floating-Point Format
119
Converting IEEE Format to 2S-Complement Tms320C3X
120
Tms320C3X Single-Precision 2S-Complement Floating-Point Format
120
Converting IEEE Format to 2S-Complement Floating-Point Format
120
Floating-Point Format
124
Converting 2S-Complement Floating-Point Format to IEEE Format
126
Converting 2S-Complement Tms320C3X Floating-Point Format to IEEE Format
126
Floating-Point Multiplication
131
Flowchart for Floating-Point Multiplication
133
Floating-Point Addition and Subtraction
137
Flowchart for Floating-Point Addition
138
Normalization Using the NORM Instruction
142
Flowchart for NORM Instruction Operation
143
Rounding (RND Instruction)
144
Flowchart for Floating-Point Rounding by the RND Instruction
145
Floating-Point to Integer Conversion (FIX Instruction)
146
Flowchart for Floating-Point to Integer Conversion by FIX Instruction
147
Integer to Floating-Point Conversion (FLOAT Instruction)
148
Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction
148
Example of Fast Logarithm on a Floating-Point Device
150
Squaring Operation of F0 = 1.5
150
Tabulated Values for Mantissa
151
Points to Consider
152
Fast Logarithm for FFT Displays
153
6 Addressing Modes
154
Addressing Types
155
Register Addressing
156
CPU Register Address/Assembler Syntax and Function
156
Direct Addressing
157
Indirect Addressing
158
Indirect Addressing Operand Encoding
159
Indirect Addressing
160
Indirect Addressing
161
Immediate Addressing
171
PC-Relative Addressing
172
Encoding for 24-Bit PC-Relative Addressing Mode
173
Circular Addressing
174
Logical and Physical Representation of Circular Buffer
174
Logical and Physical Representation of Circular Buffer after Writing Three Values
174
Logical and Physical Representation of Circular Buffer after Writing Eight Values
175
Circular Buffer Implementation
176
Data Structure for FIR Filters
177
Bit-Reversed Addressing
179
Index Steps and Bit-Reversed Addressing
180
Aligning Buffers with the TMS320 Floating-Point DSP Assembly Language Tools
181
System and User Stack Management
182
System-Stack Pointer
182
System Stack Configuration
182
Stacks
183
Implementations of High-To-Low Memory Stacks
183
Queues
184
Implementations of Low-To-High Memory Stacks
184
7 Program Flow Control
185
Repeat Modes
186
Repeat-Mode Registers
186
Repeat-Mode Control Bits
187
Repeat-Mode Operation
187
Rptb Instruction
188
Repeat-Mode Restrictions
190
Rc Register Value after Repeat Mode Completes
191
Nested Block Repeats
192
Delayed Branches
193
Calls, Traps, and Returns
195
CALL Response Timing
196
Interlocked Operations
197
Multiple Tms320C3Xs Sharing Global Memory
201
Zero-Logic Interconnect of Tms320C3X Devices
202
Reset Operation
205
Tms320C3X Pin Operation at Reset
205
Reset, Interrupt, and Trap-Branch Locations for the TMS320C31
212
Microcomputer Boot Mode
212
Effective Base Address of the Interrupt-Trap-Vector Table
213
Interrupt and Trap-Vector Locations for the TMS320C32
214
Interrupt Prioritization
215
Reset and Interrupt Vector Priorities
215
Cpu Interrupt Control Bits
216
Interrupt Flag Register Behavior
216
IF Register Modification
217
CPU Interrupt Processing
218
External Interrupts
220
Interrupt Latency
220
Interrupt Logic Functional Diagram
221
Dma Interrupts
222
DMA Interrupt Processing
223
Parallel CPU and DMA Interrupt Processing
224
Tms320C3X Interrupt Considerations
225
Pipeline Operation with PUSH ST
226
Pipeline Operation with Load Followed by Interrupt
226
Tms320C30 Interrupt Considerations
228
Flow of Traps
231
Power Management Modes
233
IDLE2 Timing
234
Interrupt Response Timing after IDLE2 Operation
235
LOPOWER Timing
236
MAXSPEED Timing
236
8 Pipeline Operation
237
Tms320C3X Pipeline Structure
238
Pipeline Conflicts
240
Register Conflicts
242
Memory Conflicts
244
Resolving Register Conflicts
255
One Program Fetch and One Data Access for Maximum Performance
258
One Program Fetch and Two Data Accesses for Maximum Performance
259
Clocking Memory Accesses
260
Minor Clock Periods
260
Multiply or CPU Operation with a Parallel Store
265
Two Parallel Stores
265
Parallel Multiplies and Adds
266
9 Tms320C30 and Tms320C31 External-Memory Interface
267
Memory Interface Signals
269
Primary Bus Interface Signals
270
Expansion Bus Interface Signals
271
Memory-Mapped External Interface Control Registers
272
Memory Interface Control Registers
273
Primary-Bus Control Register
273
Primary-Bus Control Register Bits
274
Expansion-Bus Control Register
275
Expansion-Bus Control Register Bits
275
Wait-State Generation
277
BNKCMP Example
278
Bank-Switching Example
280
External Memory Interface Timing
281
Read-Read-Write for (M)STRB
283
Write-Write-Read for (M)STRB
284
Use of Wait States for Read for (M)STRB
285
Use of Wait States for Write for (M)STRB
286
Read and Write for IOSTRB
287
Read with One Wait State for IOSTRB
288
Write with One Wait State for IOSTRB
289
Memory Read and I/O Write for Expansion Bus
290
Memory Read and I/O Read for Expansion Bus
291
Memory Write and I/O Write for Expansion Bus
292
Memory Write and I/O Read for Expansion Bus
293
I/O Write and Memory Write for Expansion Bus
294
I/O Write and Memory Read for Expansion Bus
295
I/O Read and Memory Write for Expansion Bus
296
I/O Read and Memory Read for Expansion Bus
297
I/O Write and I/O Read for Expansion Bus
298
I/O Write and I/O Write for Expansion Bus
299
I/O Read and I/O Read for Expansion Bus
300
Inactive Bus States for IOSTRB
301
Inactive Bus States for STRB and MSTRB
302
HOLD and HOLDA Timing
303
Tms320C32 Memory Features
305
Tms320C32 Memory Overview
306
Program Memory Access
307
Memory Address Spaces
307
Data Memory Access
308
Status Register
308
Memory-Mapped External Interface Control Registers
310
STRB0 Control Register
311
STRB0, STRB1, and IOSTRB Control Register Bits
313
Using Physical Memory Width and Data-Type Size Fields
316
Data-Access Sequence for a Memory Configuration with Two Banks
317
Wait-State Generation
319
Strobe Byte-Enable for 32-Bit-Wide Memory with 8-Bit Data-Type Size
324
Example of 8-Bit Data-Type Size
325
Strobe Byte-Enable for 32-Bit-Wide Memory with 16-Bit Data-Type Size
325
Example of 16-Bit Data-Type Size and 32-Bit-Wide External Memory
326
Example of 32-Bit-Wide Memory with 32-Bit Data-Type Size
328
Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size
330
Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory
331
Example of 16-Bit-Wide Memory with 16-Bit Data-Type Size
332
Example of 16-Bit-Wide Memory with 32-Bit Data-Type Size
334
Example of 8-Bit-Wide Memory with 8-Bit Data-Type Size
336
Example of 8-Bit-Wide Memory with 16-Bit Data-Type Size
338
Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory
340
External Ready Timing Improvement
341
Bus Timing
342
Tms320C31 Boot Loader
357
Boot-Loader Mode Selection
358
Tms320C31 Boot Data Stream Structure
362
Source Data Stream Structure
363
TMS320C31 Interrupt and Trap Memory Maps
367
Tms320C32 Boot Loader
369
Tms320C32 Boot-Loading Sequence
370
Boot-Loader Mode Selection
370
Source Data Stream Structure
376
Timer Global-Control Register
383
Timer Global-Control Register Bits Summary
384
Serial Ports
394
Serial-Port Global-Control Register
396
Serial-Port Global-Control Register Bits Summary
397
FSX/DX/CLKX Port-Control Register Bits Summary
401
Fsr/Dr/Clkr Port-Control Register
402
FSR/DR/CLKR Port-Control Register Bits Summary
403
Receive/Transmit Timer-Control Register Register Bits Summary
404
Receive/Transmit Timer-Counter Register
406
Receive/Transmit Timer-Period Register
407
Data-Transmit Register
407
Data-Receive Register
407
Serial-Port Timing
410
Dma Controller
427
Dma Registers
430
DMA Global-Control Register Bits Summary
433
Interrupt-Enable Register
439
CPU/DMA Interrupt-Enable Register Bits
440
Tms320C32 Dma Internal Priority Schemes
441
Dma and Interrupts
443
TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules
443
Assembly Language Instructions
459
Instruction Set
460
Load and Store Instructions
460
2-Operand Instructions
461
3-Operand Instructions
462
Program-Control Instructions
463
Low-Power Control Instructions
463
Interlocked-Operations Instructions
464
Parallel Instructions
464
Parallel-Operations Instructions
464
Instruction Set Summary
468
Parallel Instruction Set Summary
475
Group Addressing Mode Instruction Encoding
478
Parallel Addressing Modes
483
Conditional-Branch Addressing Modes
485
Condition Codes and Flags
486
Condition Codes and Flags
488
Individual Instructions
490
Instruction Symbols
491
CPU Register Syntax
494
Instruction Opcodes
712
Tms320C3X Instruction Opcodes
713
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