Omap5912 Clock Architecture - Texas Instruments OMAP5912 Reference Manual

OMAP5912 Clock Architecture

Figure 9. VDD_IO Ramps First
VDD_CORE
VDD_IO
LDO internal pwrdn
is active high
PWRDN
SLEEP
RESPWRON
STEADY
5 OMAP5912 Clock Architecture
32 Clocks
LDO is OFF
The OMAP5912 clock architecture includes the functional and interface clock
distribution for the OMAP5912 peripherals.
OMAP5912 receives its system clock from an oscillator or an external
squarewave input clock. The system clock first goes through the
ultralow-power device module (ULPD), which is responsible for power-mode
transitions and clock management. System clock frequencies are 12, 13, or
19.2 MHz. OMAP5912 is also clocked by a 32-kHz clock used by the ULPD
finite state machine (FSM) and for specific clocking needs such as the
real−time counter (RTC) or the general-purpose timers.
The ULPD output clocks are connected directly to a few peripherals with
specific clock requirements. The main system clock output of the ULPD is
connected to the MPU subsystem (often referred to as the OMAP 3.2 gigacell).
The 32−kHz clock is also one of the ULPD outputs. OMAP 3.2 gigacell is
responsible for controlling, multiplying, and distributing clocks to the remaining
peripherals.
LDO is ON
SPRU751A