Related Manuals for Texas Instruments TMS320DM643
Summary of Contents for Texas Instruments TMS320DM643
- Page 1 TMS320DM643x DMP DDR2 Memory Controller User's Guide Literature Number: SPRU986B November 2007...
- Page 2 SPRU986B – November 2007 Submit Documentation Feedback...
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Page 3: Table Of Contents
Preface Introduction Purpose of the Peripheral Features Functional Block Diagram Supported Use Case Statement Industry Standard(s) Compliance Statement Peripheral Architecture Clock Control Memory Map Signal Descriptions Protocol Description(s) Memory Width and Byte Alignment Endianness Considerations Address Mapping DDR2 Memory Controller Interface Refresh Scheduling 2.10 Self-Refresh Mode... - Page 4 Data Paths to DDR2 Memory Controller DDR2 Memory Controller Clock Block Diagram DDR2 Memory Controller Signals Refresh Command DCAB Command DEAC Command ACTV Command DDR2 READ Command DDR2 WRT Command DDR2 MRS and EMRS Command Byte Alignment Logical Address-to-DDR2 SDRAM Address Map DDR2 SDRAM Column, Row, and Bank Access DDR2 Memory Controller FIFO Block Diagram DDR2 Memory Controller Reset Block Diagram...
- Page 5 PLLC2 Configuration DDR2 Memory Controller Signal Descriptions DDR2 SDRAM Commands Truth Table for DDR2 SDRAM Commands Addressable Memory Ranges 16-Bit External Memory 32-Bit External Memory Bank Configuration Register Fields for Address Mapping Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM DDR2 Memory Controller FIFO Description Refresh Urgency Levels...
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Page 6: Preface
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. -
Page 7: Introduction
Introduction This document describes the DDR2 memory controller in the TMS320DM643x Digital Media Processor (DMP). Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. -
Page 8: Functional Block Diagram
Introduction Functional Block Diagram The DDR2 memory controller is the main interface to external DDR2 memory. general data paths to on-chip peripherals and external DDR2 SDRAM. Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controller through the switched central resource (SCR). -
Page 9: Peripheral Architecture
www.ti.com Peripheral Architecture This section describes the architecture of the DDR2 memory controller as well as how it is structured and how it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. -
Page 10: Memory Map
Peripheral Architecture 2.1.2 Clock Configuration The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in Table 1 is derived by assuming a 27-MHZ reference clock. -
Page 11: Signal Descriptions
www.ti.com Signal Descriptions The DDR2 memory controller signals are shown in features are included: The maximum data bus is 32-bits wide. The address bus is 13-bits wide with an additional 3 bank address pins. Two differential output clocks driven by internal clock sources. Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask. -
Page 12: Protocol Description(S)
Peripheral Architecture Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in signal truth table for the DDR2 SDRAM commands. Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. -
Page 13: Refresh Command
www.ti.com 2.4.1 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). -
Page 14: Dcab Command
Peripheral Architecture 2.4.2 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). -
Page 15: Deac Command
www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. the timings diagram for a DEAC command. DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[12,11, 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[3:0] SPRU986B – November 2007 Submit Documentation Feedback Figure 6. -
Page 16: Actv Command
Peripheral Architecture 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. -
Page 17: Ddr2 Read Command
www.ti.com 2.4.4 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. -
Page 18: Ddr2 Wrt Command
Peripheral Architecture 2.4.5 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. -
Page 19: Ddr2 Mrs And Emrs Command
www.ti.com 2.4.6 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2 device), single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. -
Page 20: Memory Width And Byte Alignment
Peripheral Architecture Memory Width and Byte Alignment The DDR2 memory controller supports memory widths of 16 bits and 32 bits. addressable memory ranges on the DDR2 memory controller. See the device-specific data manual for the memory widths that are supported. Figure 11 shows the byte lanes used on the DDR2 memory controller. -
Page 21: Endianness Considerations
www.ti.com Endianness Considerations The DDR2 memory controller supports little-endian operating mode. This determines the order in which data on the internal data bus is written to or read from devices that are not as wide as the internal data bus. However, the DDR2 memory controller maintains the natural order of endian operations. That is, a stream of data starting at any address N will always be accessed in the correct or incrementing data order. -
Page 22: Address Mapping
Peripheral Architecture Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of external physical devices mapped to a given chip select space. The DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical address from the rest of the system. -
Page 23: Logical Address-To-Ddr2 Sdram Address Map For 32-Bit Sdram
www.ti.com Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM SDBCR Bit IBANK PAGESIZE Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits. Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM SDBCR Bit IBANK PAGESIZE... -
Page 24: Logical Address-To-Ddr2 Sdram Address Map
Peripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address Map Col. 0 Col. 1 Col. 2 NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. DDR2 Memory Controller Col. -
Page 25: Ddr2 Sdram Column, Row, And Bank Access
www.ti.com Figure 13. DDR2 SDRAM Column, Row, and Bank Access Bank 0 0 1 2 3 Row 0 Row 1 Bank 1 Row 2 Row 0 Row 1 Row 2 Row N Row N NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. -
Page 26: Ddr2 Memory Controller Interface
Peripheral Architecture DDR2 Memory Controller Interface To move data efficiently from on-chip resources to external DDR2 SDRAM memory, the DDR2 memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and command and data schedulers. Table 11 describes the purpose of each FIFO. - Page 27 www.ti.com 2.8.1 Command Ordering and Scheduling, Advanced Concept The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address, and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. Command re-ordering takes place within the command FIFO.
- Page 28 Peripheral Architecture 2.8.2 Command Starvation The reordering and scheduling rules listed above may lead to command starvation, which is the prevention of certain commands from being processed by the DDR2 memory controller. Command starvation results from the following conditions: A continuous stream of high-priority read commands can block a low-priority write command A continuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to the closed row in the same bank.
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Page 29: Refresh Scheduling
www.ti.com Refresh Scheduling The DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDRAM devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR). A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. -
Page 30: 2.11 Reset Considerations
Peripheral Architecture Once in self-refresh mode, the DDR2 memory controller input clocks (VCLK and X2_CLK) may be gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See Section 2.16 for more information describing the proper procedure to follow when shutting down DDR2 memory controller input clocks. -
Page 31: 2.12 Vtp Io Buffer Calibration
www.ti.com 2.12 VTP IO Buffer Calibration The DDR2 memory controller is able to control the impedance of the output IO. This feature allows the DDR2 memory controller to tune the output impedance of the IO to match that of the PCB board. Control of the output impedance of the IO is an important feature because impedance matching reduces reflections, creating a cleaner board design. -
Page 32: Ddr2 Sdram Configuration By Mrs Command
Peripheral Architecture Table 14. DDR2 SDRAM Configuration by MRS Command DDR2 Memory Controller DDR2 SDRAM Address Bus Value Register Bit DDR_A[12] DDR_A[11:9] t_WR 11:9 DDR_A[8] DDR_A[7] DDR_A[6:4] CL bit DDR_A[3] DDR_A[2:0] Table 15. DDR2 SDRAM Configuration by EMRS(1) Command DDR2 Memory Controller DDR2 SDRAM Address Bus... - Page 33 www.ti.com 2.13.2 Initializing Following Device Power Up and Device RESET The following power-up sequence is preliminary and is documented to reflect the intended-use case. This power-up sequence may change at a future date. Following device power up, the DDR2 memory controller is held in reset with the internal clocks to the module gated off.
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Page 34: 2.14 Interrupt Support
Peripheral Architecture 2.14 Interrupt Support The DDR2 memory controller supports two addressing modes, linear incrementing and cache line wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2 memory controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2 memory controller will then treat the request as a linear incrementing request. -
Page 35: 2.17 Emulation Considerations
www.ti.com 2.16.1 DDR2 Memory Controller Clock Stop Procedure The following clock stop procedures are preliminary and are documented to reflect the intended-use cases. These clock stop procedures may change at a future date. Note: If an access occurs to the DDR2 memory controller after completing steps 1-5, the DLL will wake up and lock, then the MCLK will turn on and the access will be performed. -
Page 36: Supported Use Cases
Supported Use Cases Supported Use Cases The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. The programmability inherent to the DDR2 memory controller provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM bank configuration register (SDBCR), SDRAM refresh control register (SDRCR), SDRAM timing register (SDTIMR), and SDRAM timing register 2 (SDTIMR2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2 SDRAM. -
Page 37: Connecting Ddr2 Memory Controller For 32-Bit Connection
www.ti.com Figure 17. Connecting DDR2 Memory Controller for 32-Bit Connection DDR_CLK DDR_CLK DDR_CKE DDR2 DDR_CS memory DDR_WE controller DDR_RAS DDR_CAS DDR_DQM[0] DDR_DQM[1] DDR_DQS[0] DDR_DQS[1] DDR_BA[2:0] DDR_A[12:0] DDR_D[15:0] DDR_DQM[2] DDR_DQM[3] DDR_DQS[2] DDR_DQS[3] DDR_D[31:16] DDR_ZN DDR_ZP Figure 18. Connecting DDR2 Memory Controller for 16-Bit Connection DDR_CLK DDR_CLK DDR_CKE... -
Page 38: Sdram Bank Configuration Register (Sdbcr) Configuration
Supported Use Cases 3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR) The SDRAM bank configuration register (SDBCR) contains register fields that configure the DDR2 memory controller to match the data bus width, CAS latency, number of banks, and page size of the attached DDR2 memory. -
Page 39: Sdram Timing Register (Sdtimr) Configuration
www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2) The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR2 data sheet specification. -
Page 40: Ddr2 Memory Controller Registers
DDR2 Memory Controller Registers 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR) The DDR PHY control register (DDRPHYCR) contains a read latency (READLAT) field that helps the DDR2 memory controller determine when to sample read data. The READLAT field should be programmed to a value equal to CAS latency plus round trip board delay minus 1. -
Page 41: Sdram Status Register (Sdrstat)
www.ti.com Table 22. DDR2 Memory Controller Registers Relative to Base Address 2000 0000h Offset Acronym SDRSTAT SDBCR SDRCR SDTIMR SDTIMR2 PBBPR IMSR IMCR DDRPHYCR VTPIOCR Table 23. DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h Offset Acronym DDRVTPR Table 24. -
Page 42: Sdram Bank Configuration Register (Sdbcr)
DDR2 Memory Controller Registers SDRAM Bank Configuration Register (SDBCR) The SDRAM bank configuration register (SDBCR) contains fields that program the DDR2 memory controller to meet the specification of the attached DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the attached DDR2 memory. - Page 43 www.ti.com Table 26. SDRAM Bank Configuration Register (SDBCR) Field Descriptions (continued) Field Value Description 11-9 0-7h CAS latency. 0-1h Reserved CAS latency of 2 CAS latency of 3 CAS latency of 4 CAS latency of 5 6h-7h Reserved Reserved Reserved IBANK 0-7h Internal DDR2 bank setup.
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Page 44: Sdram Refresh Control Register (Sdrcr)
DDR2 Memory Controller Registers SDRAM Refresh Control Register (SDRCR) The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to: Enter and Exit the self-refresh state. Enable and disable MCLK, stopping when in the self-refresh state. Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands. -
Page 45: Sdram Timing Register (Sdtimr)
www.ti.com SDRAM Timing Register (SDTIMR) The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. The SDTIMR register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK signal. -
Page 46: Sdram Timing Register 2 (Sdtimr2)
DDR2 Memory Controller Registers SDRAM Timing Register 2 (SDTIMR2) Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. -
Page 47: Peripheral Bus Burst Priority Register (Pbbpr)
www.ti.com Peripheral Bus Burst Priority Register (PBBPR) The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command. -
Page 48: Interrupt Raw Register (Irr)
DDR2 Memory Controller Registers Interrupt Raw Register (IRR) The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs, the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is shown in Figure 25 and described in... -
Page 49: Interrupt Masked Register (Imr)
www.ti.com Interrupt Masked Register (IMR) The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR bit is set. -
Page 50: Interrupt Mask Set Register (Imsr)
DDR2 Memory Controller Registers Interrupt Mask Set Register (IMSR) The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shown Figure 27 and described in Note: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask clear register (IMCR), the interrupt is not enabled and neither bit is set to 1. -
Page 51: Interrupt Mask Clear Register (Imcr)
www.ti.com 4.10 Interrupt Mask Clear Register (IMCR) The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in described in Table Note:... -
Page 52: Ddr Phy Control Register (Ddrphycr)
DDR2 Memory Controller Registers 4.11 DDR PHY Control Register (DDRPHYCR) The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operation and determines whether the DLL is in reset, whether it is powered up, and the read latency. The DDRPHYCR is shown in Figure 29 Figure 29. -
Page 53: Vtp Io Control Register (Vtpiocr)
www.ti.com 4.12 VTP IO Control Register (VTPIOCR) The VTP IO control register (VTPIOCR) is used to control the calibration of the DDR2 memory controller IOs with respect to voltage, temperature, and process (VTP). The voltage, temperature, and process information is used to control the IO's output impedance. The VTPIOCR is shown in described in Table RECAL... -
Page 54: Ddr Vtp Register (Ddrvtpr)
DDR2 Memory Controller Registers 4.13 DDR VTP Register (DDRVTPR) The DDR VTP register (DDRVTPR) is used in conjunction with the VTP IO control register (VTPIOCR) to calibrate the output impedance of the DDR2 memory controller IOs with respect to voltage, temperature, and process. -
Page 55: Appendix A Revision History
www.ti.com Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Global Changed DDR_CLKO to DDR_CLK in text, figures, and tables. Global Changed DDR_CLKO to DDR_CLK in text, figures, and tables. Global Changed DDR_BS[2:0] to DDR_BA[2:0] in text, figures, and tables. -
Page 56: Important Notice
TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...