Instruction Cache Configuration; St3 Control Register (St3) - Texas Instruments OMAP5912 Reference Manual

DSP Memory
Table 1. Presence-Check Truth Table
3.3

Instruction Cache Configuration

3.3.1

ST3 Control Register (ST3)

28 DSP Subsystem
cache hit, the word number is used to select which word from the cache line
is returned to the DSP to complete the fetch request.
When ½ ramset memory is enabled, the presence check is performed on both
the cache and ramset blocks simultaneously. Table 1 describes the instruction
presence-check behavior. Ramset presence check is for TVB-LVB.
Cache Ramset Presence
Miss Miss False
Miss Hit-Hit True
Hit Miss True
Hit Hit-Hit True
Miss Hit-Miss False
Hit Hit-Miss True
If there is no match between the TAG number and the stored TAG(s), then a
cache miss has occurred. The I-cache then initiates a burst fetch request to
the EMIF. Four words are fetched in a burst read to fill the least recently used
cache line of the pair located at the index number offset into the data array. At
that point, the requested instruction is returned to the DSP, while the cache line
continues to fill. The LRU, LVB, and TVB are updated when line fill is
completed.
Control of the I-cache is maintained through a set of memory mapped registers
in the DSP I/O space and through three bits located in the CPU register ST3.
Cache-related bits located in ST3 are described in Table 2.
Table 2 describes the cache-related bits located in ST3. Through the ST3
register, the cache can also be frozen to lock a time-critical routine so it cannot
be overwritten.
Behavior
The cache is loaded with the corresponding
line.
The instruction is read from the ramset.
The instruction is read from the cache.
The instruction is read from the ramset.
The ramset is loaded with the corresponding
line.
The ramset is loaded with the corresponding
line.
SPRU750A