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Figure 13.
Power-up Sequence in External Clock Mode
CLK32K_IN
PWRON_RESET
RESET_MODE1
CK_REF
SYS_CLK_IN
1
LOW_PWR
1.16
ULPD Reset Inputs
1.17
OMAP3.2 Reset Generation
SPRU753A
At this step the system
clock must be stable.
The ULPD has five distinct reset inputs that act differently on the ULPD
generated output reset.
-
PWRON_RESET corresponds to the device power reset and as such
must correspond to a device input pin. PWRON_RESET is a cold reset.
-
The MPU_RST is a device global system reset and is intended to
correspond to a device input pin. MPU_RST is a warm reset.
-
Security violation
-
32-kHz watchdog reset
-
Secure watchdog reset
The ULPD propogates the cold and warm resets to OMAP3.2.
OAMP3.2 resets the processors and peripherals. Figure 14 shows the reset
procedures.
Glitch less latency
mechanism
Power Management
Ultralow-Power Device
45
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