Prescaler Value/Timer Reset Frequency - Texas Instruments OMAP5912 Reference Manual

32-Bit Watchdog Timer General Overview
1.5

Prescaler Value/Timer Reset Frequency

Table 4. Reset Period Examples
12 Timers
The 32-bit watchdog is composed of a prescaler stage and a timer counter.
The prescaler stage is clocked with the timer clock and acts as a clock divider
for the timer counter stage. The ratio can be managed by accessing the ratio
definition field of the control register (PTV of the watchdog control register
(WCLR)) and enabled with the PRE field of WCLR. Table 3 provides the divisor
ratios.
Table 3. Prescaler Clock Ratios
PRE Bit
(WCLR)
0
1
1
1
1
1
1
1
1
The reset period can be estimated by using:
Reset Period = (0xFFFF FFFF – WLDR + 1) x Timer Clock Period x Clock
Divider (PS),
where Timer Clock = 1/Timer clock frequency and PS = 2
For example, if we consider a timer clock input of 32 kHz with a prescaler ratio
value of 0x1 (clock divided by 2) and PRE field = 1 (clock divider enabled), the
reset period is as shown in Table 4.
WLDR Value
0x0000 0000
0xFFFF 0000
0xFFFF FFF0
0xFFFF FFFF
PTV Bits
(WCLR)
X
0
1
2
3
4
5
6
7
Reset Period
74 h 56 min
4 s
1 ms
62.5 µs
Divisor (PS)
1
1
2
4
8
16
32
64
128
(PTV)
.
SPRU759B