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OMAP

™

Public Version

OMAP36xx Multimedia Device

Silicon Revision 1.x

Texas Instruments OMAP™ Family of Products

Version N

Technical Reference Manual

Literature Number: SWPU177N

December 2009 – Revised November 2010

Table of Contents

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Summary of Contents for Texas Instruments OMAP36 Series

Page 1 OMAP ™ Public Version OMAP36xx Multimedia Device Silicon Revision 1.x Texas Instruments OMAP™ Family of Products Version N Technical Reference Manual Literature Number: SWPU177N December 2009 – Revised November 2010...
Page 2 WARNING: EXPORT NOTICE Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S.
Page 3 Power, Reset, and Clock Management .................. Introduction to Power Managements ................... 3.1.1 Goal of Power Management ................3.1.2 Power-Management Techniques ............. 3.1.2.1 Dynamic Voltage and Frequency Scaling SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 4 ................3.5.1.5.9 WKUP Power Domain ................. 3.5.1.5.10 PER Power Domain ................ 3.5.1.5.11 SmartReflex Power Domain ................3.5.1.5.12 DPLL Power Domains ................3.5.1.5.13 EFUSE Power Domain Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 5 ............ 3.5.3.5.3 External Output Clock1 (sys_clkout1) Control ............ 3.5.3.5.4 External Output Clock2 (sys_clkout2) Control ....................3.5.3.6 DPLL Control ............... 3.5.3.6.1 DPLL Multiplier and Divider Factors SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 6 Wake-Up and Emulation Voltage Control ................3.5.7 PRCM Off-Mode Management ....................3.5.7.1 Overview ................. 3.5.7.2 Device Off-Mode Configuration ....................3.5.7.2.1 Overview ................3.5.7.2.2 I/O Wake-Up Mechanism Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 7 Domain Wake-Up Control Registers ........3.6.2.5.1 PM_WKEN_ <domain_name> (Wake-Up Enable Register) ........3.6.2.5.2 PM_WKST_ <domain_name> (Wake-Up Status Register) ......3.6.2.5.3 PM_WKDEP_ <domain_name> (Wake-Up Dependency Register) SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 8 DVFS Using Device SmartReflex With TWL5030 Power IC ..............3.7.1.1 Device DVFS Support Architecture ..............3.7.1.2 TWL5030 DVFS Support Architecture ....................3.7.1.2.1 SMPS ................... 3.7.1.2.2 C Interface Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 9 3.8.1.13.1 Global_Reg_CM Register Summary ................. 3.8.1.13.2 Global_Reg_CM Registers ..................3.8.1.14 NEON_CM Registers ..............3.8.1.14.1 NEON_CM Register Summary ................3.8.1.14.2 NEON_CM Registers ................3.8.1.15 USBHOST_CM Registers SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 10 ................... 3.8.3.1 SR Instance Summary ....................3.8.3.2 SR Registers ................3.8.3.2.1 SR Register Summary ..................3.8.3.2.2 SR Registers ......................MPU Subsystem ..................... MPU Subsystem Overview Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 11 5.2.1.1 Clocks ..................5.2.1.1.1 IVA2.2 Clocks ...................... 5.2.1.2 Resets ..................5.2.1.2.1 Hardware Resets ..................5.2.1.2.2 Software Resets .................... 5.2.1.3 Power Domain ..................... 5.2.2 Hardware Requests SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 12 Video Accelerator/Sequencer SYSC ....................5.3.7.5.1 Reset ................. 5.3.7.5.2 Power Management ..................5.3.7.5.3 Interrupt Handler ....................5.3.8 Local Memories .................... 5.3.8.1 ROM Overview .................... 5.3.8.2 RAM Overview Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 13 ................5.4.4.6.7 DMA Completion Mode ..............5.4.4.6.8 Partial Versus Total Completion ................5.4.4.6.9 Tracking DMA Completion ..............5.4.4.6.10 DMA Interrupt Service Routine ..................5.4.4.6.11 Benchmarking SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 14 5.4.11 Error Identification Process ............... 5.4.11.1 Error Reporting for IDMA Module ..............5.4.11.2 Error Reporting for EDMA Module ..............5.4.11.3 Error Reporting for the L3 Interconnect Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 15 5.5.16.1 IA_SEQ Register Mapping Summary 1081 ................ 5.5.16.2 IA_SEQ Register Descriptions 1081 ..................Camera Image Signal Processor 1085 ....................Camera ISP Overview 1086 ..................6.1.1 Camera ISP Features 1088 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 16 Camera ISP CSI2 Checksum 1178 .... 6.4.3.5 Camera ISP CSI2 RAW Image Transcoding with DPCM and A-law Compression 1178 ............... 6.4.3.6 Camera ISP CSI2 Short Packet 1182 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 17 Camera ISP H3A AE/AWB Engine 1225 ................. 6.4.8.2 Camera ISP Histogram 1225 ..............6.4.8.2.1 Camera ISP Histogram Features 1225 ............6.4.8.2.2 Camera ISP Histogram Block Diagram 1226 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 18 6.5.3.20.2 Camera ISP CSI1/CCP2B Read Data from Memory 1255 ................6.5.4 Programming the CSI2 Receiver 1256 ............6.5.4.1 Camera ISP CSI2 Enabling the Interface 1256 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 19 Camera ISP Resizer Multiple Passes for Large Resizing Operations 1287 ..........6.5.8.5.2 Camera ISP Resizer Processing Time Calculation 1288 ............6.5.8.6 Camera ISP Resizer Summary of Constraints 1288 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 20 Camera ISP CCDC Registers 1372 .............. 6.6.4.1 Camera ISP CCDC Register Summary 1372 ............6.6.4.2 Camera ISP CCDC Register Description 1373 ................. 6.6.5 Camera ISP HIST Registers 1404 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 21 Data Type Field DT[5:0] 1599 ............... 7.2.2.4.6 Pixel Data Formats in Video Mode 1599 ................7.2.2.4.7 Synchronization Codes 1600 ....................7.2.2.4.8 Blanking 1600 ................... 7.2.2.4.9 Frame Structures 1604 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 22 Color Phase Rotation 1655 ............7.4.2.5.2 Passive Matrix Display Dithering Logic 1656 ............. 7.4.2.5.3 Passive Matrix Display Output FIFO 1656 ..............7.4.2.5.4 Multiple Cycle Output Format 1656 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 23 RFBI Interconnect FIFO 1688 ..................7.4.6.3 Input Pixel Formats 1688 .................. 7.4.6.4 Output Parallel Modes 1688 ..................7.4.6.5 Unmodified Bits 1689 .................... 7.4.6.6 Bypass Mode 1689 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 24 ..................7.5.3.6.1 Digital Timings 1738 ................7.5.3.6.2 Digital Frame/Field Size 1738 ..................7.5.3.6.3 Digital Overlay 1738 ............7.5.4 DSI Protocol Engine Basic Programming Model 1738 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 25 Programmable Line Number 1766 ..................7.5.7.3 RFBI Configuration 1766 ..................7.5.7.3.1 Parallel Mode 1767 ..................7.5.7.3.2 Trigger Mode 1767 ............7.5.7.3.3 VSYNC Pulse Width (Minimum Value) 1767 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 26 Enable Video Mode Using the DISPC Video Port 1802 ............7.6.5 DSI Command Mode Using the DISPC Video Port 1802 ............7.6.5.1 Display Subsystem Use Cases and Tips 1802 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 27 9.1.2 Architecture Overview 1994 .................... 9.1.3 Module Distribution 1996 ................. 9.1.3.1 L3 Interconnect Agents 1996 ..................9.1.3.2 L4-Core Agents 1997 ................... 9.1.3.3 L4-Per Agents 1998 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 28 2055 ......................9.3.1 Overview 2055 ................... 9.3.1.1 L4-Core Interconnect 2057 ..................9.3.1.2 L4-Per Interconnect 2057 ..................9.3.1.3 L4-Emu Interconnect 2058 ................9.3.1.4 L4-Wakeup Interconnect 2059 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 29 ................10.1.4.2 L3 Interconnect Interface 2122 ..10.1.4.3 Address Decoder, GPMC Configuration, and Chip-Select Configuration Register File 2123 ................. 10.1.4.4 Error Correction Code Engine 2123 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 30 ..................10.1.5.13 Boot Configuration 2156 ............10.1.5.14 NAND Device Basic Programming Model 2156 ........10.1.5.14.1 NAND Memory Device in Byte or Word16 Stream Mode 2156 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 31 10.2.4.4.9 Power-Saving Features 2257 ............... 10.2.4.4.10 SDRC Power-Down Mode 2259 ................10.2.4.4.11 Controlled Delay Line 2260 ..................10.2.4.5 Mode Registers 2263 ................10.2.4.5.1 Mode Register (MR) 2263 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 32 2331 ................. 10.3.1 OCM Subsystem Overview 2331 ................10.3.2 OCM Subsystem Integration 2332 ....................10.3.2.1 Description 2332 ..........10.3.2.2 Clocking, Reset, and Power-Management Scheme 2332 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 33 11.4.19.3 Descriptors 2362 ....................11.4.19.3.1 Type 1 2362 ....................11.4.19.3.2 Type 2 2363 ....................11.4.19.3.3 Type 3 2364 ..............11.4.19.4 Linked-List Control and Monitoring 2364 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 34 12.6.3 MPU INTC Register Descriptions 2423 ............... 12.6.4 Modem INTC Register Descriptions 2433 ....................System Control Module 2435 ......................13.1 SCM Overview 2436 ...................... 13.2 SCM Environment 2436 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 35 13.4.10 Debug and Observability 2485 ....................13.4.10.1 Description 2485 ................... 13.4.10.2 Observability Tables 2488 ..........13.4.11 EMI Reduction for Clocking Generation (Spreading) 2522 ....................13.4.11.1 Overview 2522 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 36 2647 ....................14.2.1.2 Resets 2647 ..................14.2.1.2.1 Hardware Reset 2647 ..................14.2.1.2.2 Software Reset 2647 ..................14.2.1.3 Power Domains 2647 ..................14.2.1.4 Power Management 2648 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 37 15.3.3.3.1 Second-Level Descriptor Format 2676 ..............15.3.3.3.2 Small Page Translation Summary 2676 ............... 15.3.3.3.3 Large Page Translation Summary 2677 ................15.3.4 Translation Lookaside Buffer 2677 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 38 16.4.1 WDTs Overview 2746 ................... 16.4.1.1 WDT Features 2746 ....................16.4.2 WDT Integration 2747 ..........16.4.2.1 Clocking, Reset, and Power-Management Scheme 2747 ................. 16.4.2.1.1 Clock Management 2747 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 39 C SCCB Typical Connection Protocol and Data Format 2777 ........... 17.2.2.3.1 HS I C Serial Transmission Timing Diagram 2777 ............17.2.2.3.2 HS I C SCCB Transmission Data Formats 2777 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 40 17.5.2.1 HS I C Main Program (SCCB Mode) 2810 ..17.5.2.1.1 HS I C Configure the Module Before Enabling the I C Controller (SCCB Mode) 2810 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 41 18.5.1.1 Mode Selection 2854 ..................18.5.1.2 Reset/Initialization 2854 ..............18.5.2 HDQ Protocol Basic Programming Model 2854 ..................18.5.2.1 Write Operation 2854 ..................18.5.2.2 Read Operation 2855 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 42 2887 ..................19.3.1.3 Software Reset 2888 ................... 19.3.1.4 Power Domain 2888 ..................19.3.2 Hardware Requests 2888 ....................19.3.2.1 Interrupts 2888 ..................19.3.2.2 DMA Requests 2888 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 43 19.4.5.3.2 System Power Saving 2919 ................. 19.5 UART/IrDA/CIR Basic Programming Model 2920 ................. 19.5.1 UART Programming Model 2920 ....................19.5.1.1 Quick start 2920 ..................19.5.1.1.1 Software Reset 2920 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 44 ................... 20.5.2.6 Start Bit Mode 2996 ................20.5.2.7 Chip-Select Timing Control 2996 ..............20.5.2.8 Programmable SPI Clock (spim_clk) 2997 ................20.5.2.8.1 Clock Ratio Granularity 2997 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 45 20.6.3.1 Common Transfer Procedure 3025 ........20.6.3.2 Transmit-Receive Procedure With Word Count (WCNT≠0) 3027 ........20.6.3.3 Transmit-Receive Procedure Without Word Count (WCNT=0) 3028 ................20.6.3.4 Transmit-Only Procedure 3029 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 46 21.3.2.4.2 McBSP Acknowledgment Modes 3080 ................21.3.2.4.3 Wake-Up Capability 3082 ..........21.3.2.4.4 Analysis of the Receiver Smart Idle Behavior 3083 ..................21.3.3 Hardware Requests 3086 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 47 21.4.4.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse 3112 ......... 21.4.4.6.3 Preventing Unexpected Transmit Frame-sync Pulses 3112 ................21.4.4.7 Overflow in the Transmitter 3113 ................. 21.4.5 McBSP DMA Configuration 3113 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 48 High-Speed USB OTG Controller 3211 .............. 22.1.1 High-Speed USB OTG Controller Overview 3211 ................... 22.1.1.1 Main Features 3211 ............22.1.2 High-Speed USB OTG Controller Environment 3213 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 49 22.2.2.4 Serial Interfaces 3245 ................22.2.2.4.1 Encoding in Serial Mode 3247 .............. 22.2.2.4.2 Sideband Signals for Serial Modes 3250 ............22.2.2.4.3 Transceiver Interface Configurations 3251 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 50 24.1 MMC/SD/SDIO Overview 3364 ..................24.1.1 MMC/SD/SDIO Features 3365 ..................24.2 MMC/SD/SDIO Environment 3367 ..........24.2.1 MMC/SD/SDIO Connected to MMC, SD, or SDIO Card 3367 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 51 24.5.2 Basic Operations for MMC/SD/SDIO Host Controller 3399 ............24.5.2.1 Card Detection, Identification, and Selection 3400 ........... 24.5.2.2 Read/Write Transfer Flow in DMA Mode With Interrupt 3401 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 52 ............25.5 General-Purpose Interface Basic Programming Model 3480 ........... 25.5.1 Power Saving by Grouping the Edge/Level Detection 3480 ................... 25.5.2 Set and Clear Instructions 3480 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 53 26.4.5.3.2 USB Customized Descriptors 3538 ................26.4.5.3.3 USB Driver Functionality 3539 ..................26.4.6 Fast External Booting 3540 ....................26.4.6.1 Overview 3540 ..................26.4.6.2 External Booting 3540 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 54 27.2.1 ICEPick Overview 3588 ..................27.2.2 ICEPick Environment 3588 ................... 27.2.3 ICEPick Integration 3589 ................27.2.4 ICEPick Functional Description 3589 ................. 27.2.4.1 ICEPick Block Diagram 3589 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 55 27.3.6.1 SDTI Register Summary 3621 ................27.3.6.2 SDTI Register Description 3622 ....................27.4 Emulation Pin Manager 3639 ....................27.4.1 EPM Overview 3639 ....................27.4.2 EPM Integration 3639 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 56 L3 Interconnect Agents 3668 ..................A.7.1.2 L4-Core Agents 3668 ................... A.7.1.3 L4-Per Agents 3669 ....................Memory Subsystem 3670 ......................A.8.1 GPMC 3670 ........................sDMA 3671 Contents SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 57 B.4.6 Multichannel Buffered Serial Port 3708 ................B.4.7 High-Speed USB Host Subsystem 3709 ................... B.4.8 General-Purpose Interface 3709 ..............Control Module Pad Multiplexing Register Fields 3711 ........................Glossary 3725 SWPU177N – December 2009 – Revised November 2010 Contents Copyright © 2009–2010, Texas Instruments Incorporated...
Page 58: Table Of Contents
3-34. Power Control Overview ..................3-35. PRCM Clock Manager Overview ......................3-36. External Clock I/O ....................3-37. Internal Clock Sources ....................3-38. PRM Clock Generator List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 59 3-84. Voltage Processor Functional Overview ........3-85. SmartReflex - SMPS Communication for Automatic Voltage Adjustments ..................3-86. Device Off-Mode Control Overview ................... 3-87. sys_clkout2 Gating Polarity Control SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 60 5-23. SYSC Block Diagram ..................5-24. IVA2.2 Local Memories Hierarchy ..................5-25. IVA2 Boot Mode Configuration ................. 5-26. IVA2 Boot Basic Programming Model List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 61 6-36. Camera ISP CSI2 RGB565 1127 ................... 6-37. Camera ISP CSI2 RGB888 1128 ................... 6-38. Camera ISP CSI2 RGB666 1129 ................... 6-39. Camera ISP CSI2 RGB444 1130 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 62 6-86. Camera ISP VPBE Resizer Process 1214 ............. 6-87. Camera ISP VPBE Resizer Resizer in Memory-Input Mode 1215 ............. 6-88. Camera ISP VPBE Resizer Typical Sample-Rate Converter 1216 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 63 7-11. LCD Pixel Data Color24 Active Matrix 1577 ..................7-12. RFBI Data Stall Signal Diagram 1577 ..............7-13. RFBI Data Stall Signal Diagram With Handcheck 1578 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 64 7-60. TV Display Interface (Composite Mode, AC coupled, Low FS Swing) 1614 ............... 7-61. TV Display Interface (Bypass Mode, Dual Channel) 1614 ..................7-62. Display Subsystem Integration 1618 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 65 7-110. DC-Coupling TV Detect Waveforms for TV Connected and Disconnected 1700 ........7-111. AC-Coupling TV Detect Waveforms for TV Connected and Disconnected 1701 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 66 8-2. SGX Subsystem Integration 1969 ....................8-3. SGX Block Diagram 1971 .................. 9-1. Interconnect Architecture Overview 1995 ..................... 9-2. L3 Interconnect Overview 2001 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 67 2167 ..................10-30. 128 Word16 ECC Computation 2168 ..................10-31. 256 Word16 ECC Computation 2168 ................10-32. Manual Mode Sequence and Mapping 2173 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 68 2331 ................. 10-79. OCM Subsystem Integration to the Device 2332 ......................11-1. SDMA Overview 2337 ..............11-2. External SDMA Requests Typical Application 2339 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 69 14-4. Example of Communication 2656 ....................15-1. Device MMU Instances 2664 ..................15-2. Camera MMU System Integration 2665 ..................15-3. IVA2.2 MMU System Integration 2665 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 70 17-10. HS I C Synchronization of I C Clock Generators 2774 ..........17-11. HS I C Controllers and Typical Connections to SCCB Devices 2775 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 71 19-4. CIR System Overview 2874 .................... 19-5. UART Frame Data Format 2875 ....................19-6. IrDA SIR Frame Format 2876 ..................19-7. IrDA SIR Encoding Mechanism 2877 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 72 20-21. Buffer Use in Transmit Direction Only 3002 ................20-22. Buffer Use in Receive Direction Only 3003 ..............20-23. Buffer Used For Both Transmit/Receive Directions 3003 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 73 21-28. McBSP Operating at Maximum Packet Frequency 3097 ..............21-29. Single-Phase Frame for a McBSP Data Transfer 3099 ..............21-30. Dual-Phase Frame for a McBSP Data Transfer 3100 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 74 3213 ............22-4. High-Speed USB Controller Functional Interface Signals 3214 ................22-5. High-Speed USB Controller Integration 3215 ................... 22-6. High-Speed USB Controller 3221 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 75 3374 ................... 24-17. MMC/SD/SDIO1 Integration 3375 ....................24-18. DMA Receive Mode 3380 ....................24-19. DMA Transmit Mode 3381 ....................24-20. MMC/SD/SDIO Diagram 3384 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 76 ....................26-5. ROM Code Architecture 3522 ....................26-6. 32KB ROM Memory Map 3523 ................26-7. 64KB RAM Memory Map of GP Devices 3525 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 77 OMAP36xx in CYN Package Block Diagram 3652 ....................A-2. External Clock Interface 3658 .................. A-3. Camera Subsystem Block Diagram 3665 ................... A-4. Display Subsystem Block Diagram 3667 SWPU177N – December 2009 – Revised November 2010 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated...
Page 78 Public Version www.ti.com ..................A-5. Clock and Reset Environment 3699 List of Figures SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 79 3-21. EFUSE Power Domain Reset Signal ..................3-22. BANDGAP Logic Reset Signal ....................3-23. Global Reset Summary ....................3-24. Local Reset Summary ....................3-25. Power Domain Modules SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 80 3-71. PER Power Domain Wake-Up Events ................3-72. EMU Power Domain Wake-Up Events ................3-73. WKUP Power Domain Wake-Up Events ..................3-74. Clock Domain Mute Conditions List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 81 3-119. Register Call Summary for Register CM_SYSCONFIG ................... 3-120. MPU_CM Register Summary ....................3-121. CM_CLKEN_PLL_MPU ............3-122. Register Call Summary for Register CM_CLKEN_PLL_MPU ....................... 3-123. CM_IDLEST_MPU SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 82 3-168. Register Call Summary for Register CM_CLKSEL_SGX ....................3-169. CM_SLEEPDEP_SGX ............3-170. Register Call Summary for Register CM_SLEEPDEP_SGX ....................3-171. CM_CLKSTCTRL_SGX ............. 3-172. Register Call Summary for Register CM_CLKSTCTRL_SGX List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 83 3-217. Register Call Summary for Register CM_IDLEST_DSS ....................3-218. CM_AUTOIDLE_DSS ............3-219. Register Call Summary for Register CM_AUTOIDLE_DSS ...................... 3-220. CM_CLKSEL_DSS ............3-221. Register Call Summary for Register CM_CLKSEL_DSS SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 84 3-266. Register Call Summary for Register CM_CLKSTCTRL_EMU ....................3-267. CM_CLKSTST_EMU ............3-268. Register Call Summary for Register CM_CLKSTST_EMU ....................3-269. CM_CLKSEL2_EMU ............3-270. Register Call Summary for Register CM_CLKSEL2_EMU List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 85 3-315. PRM_REVISION .............. 3-316. Register Call Summary for Register PRM_REVISION ...................... 3-317. PRM_SYSCONFIG ............3-318. Register Call Summary for Register PRM_SYSCONFIG ....................3-319. PRM_IRQSTATUS_MPU SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 86 3-364. Register Call Summary for Register PM_MPUGRPSEL3_CORE ..................3-365. SGX_PRM Register Summary ......................3-366. RM_RSTST_SGX ............3-367. Register Call Summary for Register RM_RSTST_SGX ....................... 3-368. PM_WKDEP_SGX List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 87 3-413. Register Call Summary for Register PM_PREPWSTST_CAM ..................3-414. PER_PRM Register Summary ......................3-415. RM_RSTST_PER ............3-416. Register Call Summary for Register RM_RSTST_PER ......................3-417. PM_WKEN_PER SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 88 3-462. Register Call Summary for Register PRM_VOLTCTRL ....................3-463. PRM_SRAM_PCHARGE ............ 3-464. Register Call Summary for Register PRM_SRAM_PCHARGE ....................3-465. PRM_CLKSRC_CTRL ............3-466. Register Call Summary for Register PRM_CLKSRC_CTRL List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 89 3-511. Register Call Summary for Register PM_WKDEP_NEON ....................3-512. PM_PWSTCTRL_NEON ............ 3-513. Register Call Summary for Register PM_PWSTCTRL_NEON ....................3-514. PM_PWSTST_NEON ............3-515. Register Call Summary for Register PM_PWSTST_NEON SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 90 3-560. Register Call Summary for Register IRQENABLE_SET ....................... 3-561. IRQENABLE_CLR ............3-562. Register Call Summary for Register IRQENABLE_CLR ....................... 3-563. SENERROR_REG ............3-564. Register Call Summary for Register SENERROR_REG List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 91 5-28. EVTCLRi ............... 5-29. Register Call Summary for Register EVTCLRi ........................ 5-30. EVTMASKi ..............5-31. Register Call Summary for Register EVTMASKi ......................5-32. MEVTFLAGi SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 92 5-77. Register Call Summary for Register SDMAARBE ......................5-78. MDMAARBE ..............5-79. Register Call Summary for Register MDMAARBE ......................5-80. ICFGMPFAR ..............5-81. Register Call Summary for Register ICFGMPFAR List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 93 5-126. Register Call Summary for Register L2IBAR ........................5-127. L2IWC ................5-128. Register Call Summary for Register L2IWC ........................5-129. L1PIBAR ............... 5-130. Register Call Summary for Register L1PIBAR SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 94 5-175. L1PMPPAk ..............5-176. Register Call Summary for Register L1PMPPAk ....................... 5-177. L1DMPFAR ..............5-178. Register Call Summary for Register L1DMPFAR ....................... 5-179. L1DMPFSR List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 95 5-224. TPCC_QEMR ..............5-225. Register Call Summary for Register TPCC_QEMR ......................5-226. TPCC_QEMCR ............... 5-227. Register Call Summary for Register TPCC_QEMCR ......................5-228. TPCC_CCERR SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 96 5-273. Register Call Summary for Register TPCC_CER ......................5-274. TPCC_CERH ..............5-275. Register Call Summary for Register TPCC_CERH ....................... 5-276. TPCC_EER ..............5-277. Register Call Summary for Register TPCC_EER List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 97 5-322. TPCC_QSECR ..............5-323. Register Call Summary for Register TPCC_QSECR ......................5-324. TPCC_ER_Rn ..............5-325. Register Call Summary for Register TPCC_ER_Rn ......................5-326. TPCC_ECR_Rn SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 98 5-371. Register Call Summary for Register TPCC_ICRH_Rn ......................5-372. TPCC_IEVAL_Rn ............. 5-373. Register Call Summary for Register TPCC_IEVAL_Rn ......................5-374. TPCC_QER_Rn .............. 5-375. Register Call Summary for Register TPCC_QER_Rn List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 99 5-420. Register Call Summary for Register TPTCj_ERREN ......................5-421. TPTCj_ERRCLR .............. 5-422. Register Call Summary for Register TPTCj_ERRCLR ......................5-423. TPTCj_ERRDET .............. 5-424. Register Call Summary for Register TPTCj_ERRDET SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 100 5-469. TPTCj_DFCNTi ............... 5-470. Register Call Summary for Register TPTCj_DFCNTi ......................5-471. TPTCj_DFDSTi ............... 5-472. Register Call Summary for Register TPTCj_DFDSTi ......................5-473. TPTCj_DFBIDXi List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 101 1001 ..........5-520. Register Call Summary for Register WUGEN_PENDEVTCLR0 1002 .................... 5-521. WUGEN_PENDEVTCLR1 1002 ..........5-522. Register Call Summary for Register WUGEN_PENDEVTCLR1 1002 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 102 1017 ............5-569. Register Call Summary for Register VLCD_MPEG_CBP 1018 ....................5-570. VLCD_LUMA_VECTOR 1018 ............ 5-571. Register Call Summary for Register VLCD_LUMA_VECTOR 1018 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 103 5-617. Register Call Summary for Register VLCD_VLD_ERRCTL 1030 ....................5-618. VLCD_VLD_ERRSTAT 1030 ............ 5-619. Register Call Summary for Register VLCD_VLD_ERRSTAT 1030 ....................5-620. VLCD_RING_START 1030 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 104 1042 ............5-667. Register Call Summary for Register CAVLC_NUMTTL 1043 ....................... 5-668. CAVLC_NUMHD 1043 ............5-669. Register Call Summary for Register CAVLC_NUMHD 1043 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 105 1059 ............5-716. Register Call Summary for Register iME_SYSSTATUS 1059 ................5-717. iME_PROGRAMBUFFERLINENLSBi 1059 ........5-718. Register Call Summary for Register iME_PROGRAMBUFFERLINENLSBi 1059 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 106 1071 ..........5-765. Register Call Summary for Register iLF_PARAMETERSTACKLWk 1072 ....................5-766. iLF_EFPTABLEENTRYl 1072 ............ 5-767. Register Call Summary for Register iLF_EFPTABLEENTRYl 1072 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 107 6-13. Camera ISP cam_xclka Configuration 1141 ................6-14. Camera ISP cam_xclkb Configuration 1142 ....................6-15. Camera ISP Interrupts 1145 ................6-16. Camera ISP CBUFF Interrupt Details 1147 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 108 6-63. Camera ISP CCDC Conventional Readout Pattern 1 to 1 1274 ..............6-64. Camera ISP CCDC Dual Readout Pattern 1 to 1 1275 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 109 1327 ............. 6-111. Register Call Summary for Register TCTRL_SHUT_DELAY 1328 .................... 6-112. TCTRL_PSTRB_LENGTH 1328 ..........6-113. Register Call Summary for Register TCTRL_PSTRB_LENGTH 1328 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 110 6-159. Register Call Summary for Register CCP2_LC23_IRQSTATUS 1352 ..................... 6-160. CCP2_LCM_IRQENABLE 1353 ..........6-161. Register Call Summary for Register CCP2_LCM_IRQENABLE 1353 ..................... 6-162. CCP2_LCM_IRQSTATUS 1353 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 111 ....................6-208. CCP2_LCM_DST_OFST 1371 ........... 6-209. Register Call Summary for Register CCP2_LCM_DST_OFST 1372 ..................6-210. ISP_CCDC Register Summary 1372 ......................6-211. CCDC_PID 1373 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 112 1395 ............6-258. Register Call Summary for Register CCDC_FMT_HORZ 1395 ....................6-259. CCDC_FMT_VERT 1396 ............6-260. Register Call Summary for Register CCDC_FMT_VERT 1396 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 113 6-306. Register Call Summary for Register H3A_PID 1412 ........................ 6-307. H3A_PCR 1412 ..............6-308. Register Call Summary for Register H3A_PCR 1413 ......................6-309. H3A_AFPAX1 1413 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 114 6-355. Register Call Summary for Register PRV_PID 1427 ....................... 6-356. PRV_PCR 1427 ..............6-357. Register Call Summary for Register PRV_PCR 1429 ..................... 6-358. PRV_HORZ_INFO 1430 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 115 1445 ..............6-405. Register Call Summary for Register PRV_CSC0 1445 ......................6-406. PRV_CSC1 1445 ..............6-407. Register Call Summary for Register PRV_CSC1 1446 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 116 1461 ............... 6-454. Register Call Summary for Register RSZ_HFILT98 1461 ......................6-455. RSZ_HFILT1110 1461 ............6-456. Register Call Summary for Register RSZ_HFILT1110 1461 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 117 6-502. Register Call Summary for Register RSZ_VFILT2524 1473 ......................6-503. RSZ_VFILT2726 1473 ............6-504. Register Call Summary for Register RSZ_VFILT2726 1473 ......................6-505. RSZ_VFILT2928 1474 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 118 6-551. Register Call Summary for Register SBL_PRV_RD_3 1494 ....................... 6-552. SBL_PRV_WR_0 1494 ............6-553. Register Call Summary for Register SBL_PRV_WR_0 1494 ....................... 6-554. SBL_PRV_WR_1 1495 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 119 1509 ............6-601. Register Call Summary for Register SBL_RSZ4_WR_0 1510 ..................... 6-602. SBL_RSZ4_WR_1 1510 ............6-603. Register Call Summary for Register SBL_RSZ4_WR_1 1510 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 120 1528 ..............6-650. Register Call Summary for Register CSI2_CTRL 1529 ......................6-651. CSI2_DBG_H 1530 ..............6-652. Register Call Summary for Register CSI2_DBG_H 1530 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 121 Number of Displayed Pixels per Pixel Clock Cycle Based on Display Type 1573 ................ 7-6. Programmable Timing Fields in RFBI Mode 1578 ................7-7. Programmable Fields in Bypass Mode 1579 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 122 7-54. VRFB Rotation - DMA Settings 1724 ..............7-55. VRFB Rotation With Mirroring - DMA Settings 1726 ..............7-56. Video Rotation Register Settings (YUV Only) 1727 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 123 7-102. Reset DSI Modules 1804 ..................... 7-103. Configure DSI PLL 1805 ..................7-104. Switch to DSI PLL Clock Source 1806 ....................7-105. DSI Control Registers 1806 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 124 7-151. Register Call Summary for Register DISPC_CONFIG 1835 ..................7-152. DISPC_DEFAULT_COLOR_m 1836 ..........7-153. Register Call Summary for Register DISPC_DEFAULT_COLOR_m 1836 ..................7-154. DISPC_TRANS_COLOR_m 1836 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 125 1852 ..........7-201. Register Call Summary for Register DISPC_VIDn_ATTRIBUTES 1855 .................. 7-202. DISPC_VIDn_FIFO_THRESHOLD 1855 ........7-203. Register Call Summary for Register DISPC_VIDn_FIFO_THRESHOLD 1855 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 126 7-249. Register Call Summary for Register RFBI_SYSSTATUS 1869 ....................... 7-250. RFBI_CONTROL 1869 ............7-251. Register Call Summary for Register RFBI_CONTROL 1870 ...................... 7-252. RFBI_PIXEL_CNT 1871 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 127 1887 .......... 7-299. Register Call Summary for Register VENC_CC_CARR_WSS_CARR 1887 ...................... 7-300. VENC_C_PHASE 1887 ............7-301. Register Call Summary for Register VENC_C_PHASE 1888 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 128 7-347. Register Call Summary for Register VENC_VS_EXT_STOP_Y 1901 ..................7-348. VENC_AVID_START_STOP_X 1902 ........... 7-349. Register Call Summary for Register VENC_AVID_START_STOP_X 1902 ..................7-350. VENC_AVID_START_STOP_Y 1902 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 129 1933 ............7-397. Register Call Summary for Register DSI_VM_TIMING3 1933 ...................... 7-398. DSI_CLK_TIMING 1934 ............7-399. Register Call Summary for Register DSI_CLK_TIMING 1934 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 130 7-445. Register Call Summary for Register DSI_PHY_REGISTER5 1958 ....................7-446. DSI_PLL_CONTROL 1958 ............7-447. Register Call Summary for Register DSI_PLL_CONTROL 1959 ..................... 7-448. DSI_PLL_STATUS 1959 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 131 8-39. Register Call Summary for Register OCP_DEBUG_CONFIG 1986 ....................8-40. OCP_DEBUG_STATUS 1987 ........... 8-41. Register Call Summary for Register OCP_DEBUG_STATUS 1988 ................... 9-1. MCmd Qualifier Description 1993 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 132 9-47. Register Call Summary for Register L3_IA_ERROR_LOG 2034 ..................9-48. L3_IA_ERROR_LOG_ADDR 2035 ..........9-49. Register Call Summary for Register L3_IA_ERROR_LOG_ADDR 2035 ................. 9-50. Target Agent Common Register Summary 2035 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 133 9-95. Register Call Summary for Register L3_PM_ADDR_MATCH_k 2051 ................. 9-96. Reset Value for L3_PM_ADDR_MATCH_k 2052 ....................9-97. SI Register Summary 2052 ...................... 9-98. L3_SI_CONTROL 2053 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 134 9-144. Register Call Summary for Register L4_IA_AGENT_CONTROL_H 2083 ................... 9-145. L4_IA_AGENT_STATUS_L 2084 ..........9-146. Register Call Summary for Register L4_IA_AGENT_STATUS_L 2084 ................... 9-147. L4_IA_AGENT_STATUS_H 2084 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 135 9-193. L4_TA_AGENT_STATUS_H 2096 ..........9-194. Register Call Summary for Register L4_TA_AGENT_STATUS_H 2096 ....................9-195. L4 LA Register Summary 2096 ....................9-196. L4_LA_COMPONENT_L 2097 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 136 2116 ..................10-2. GPMC Pin Multiplexing Options 2117 ..................10-3. Idle Cycle Insertion Configuration 2139 ..............10-4. Chip-Select Configuration for NAND Interfacing 2157 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 137 10-50. Register Call Summary for Register GPMC_CONFIG1_i 2206 ....................10-51. GPMC_CONFIG2_i 2206 ............10-52. Register Call Summary for Register GPMC_CONFIG2_i 2207 ....................10-53. GPMC_CONFIG3_i 2207 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 138 10-100. VRFB Contexts Virtual Address Spaces vs Rotation Angle 2244 ..............10-101. Mobile DDR SDRAM AC Timing Parameters 2252 ................... 10-102. SDRC Data Lane Configurations 2253 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 139 10-148. Register Call Summary for Register SMS_ROT_SIZEn 2313 ..................10-149. SMS_ROT_PHYSICAL_BAn 2313 ..........10-150. Register Call Summary for Register SMS_ROT_PHYSICAL_BAn 2313 .................... 10-151. SDRC Instance Summary 2314 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 140 11-12. Type 3 With Source and Destination Address Updates 2364 .............. 11-13. Type 3 With Source or Destination Address Update 2364 ..................... 11-14. SDMA Instance Summary 2374 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 141 2397 ..............11-61. Register Call Summary for Register DMA4_CDFIi 2397 ......................11-62. DMA4_CSACi 2398 ............... 11-63. Register Call Summary for Register DMA4_CSACi 2398 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 142 2429 ............... 12-33. Register Call Summary for Register INTCPS_MIRn 2429 ....................12-34. INTCPS_MIR_CLEARn 2430 ............ 12-35. Register Call Summary for Register INTCPS_MIR_CLEARn 2430 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 143 13-31. Internal Signals Multiplexed on OBSMUX1 2489 ................. 13-32. Internal Signals Multiplexed on OBSMUX2 2489 ................. 13-33. Internal Signals Multiplexed on OBSMUX3 2490 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 144 2554 ..........13-80. Register Call Summary for Register CONTROL_SYSCONFIG 2554 ..................... 13-81. CONTROL_PADCONF_X 2555 ..........13-82. Register Call Summary for Register CONTROL_PADCONF_X 2556 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 145 2590 ........13-129. Register Call Summary for Register CONTROL_FUSE_OPP1G_VDD1 2590 .................. 13-130. CONTROL_FUSE_OPP50_VDD1 2591 ........13-131. Register Call Summary for Register CONTROL_FUSE_OPP50_VDD1 2591 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 146 13-177. Register Call Summary for Register CONTROL_CORE_DPLL_SPREADING 2610 ................13-178. CONTROL_PER_DPLL_SPREADING 2611 ......... 13-179. Register Call Summary for Register CONTROL_PER_DPLL_SPREADING 2611 ..............13-180. CONTROL_USBHOST_DPLL_SPREADING 2611 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 147 2622 ....13-227. Register Call Summary for Register CONTROL_DPF_REGION4_GPMC_FW_REQINFO 2622 ..............13-228. CONTROL_DPF_REGION4_GPMC_FW_WR 2622 ......13-229. Register Call Summary for Register CONTROL_DPF_REGION4_GPMC_FW_WR 2622 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 148 13-275. Register Call Summary for Register CONTROL_WKUP_DEBOBS_3 2638 ............13-276. Type Value For CONTROL_WKUP_DEBOBS_3 Register 2639 ..................13-277. CONTROL_WKUP_DEBOBS_4 2639 ......... 13-278. Register Call Summary for Register CONTROL_WKUP_DEBOBS_4 2639 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 149 2691 ............15-19. Register Call Summary for Register MMU_IRQENABLE 2691 ....................15-20. MMU_WALKING_ST 2692 ............15-21. Register Call Summary for Register MMU_WALKING_ST 2692 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 150 2730 ................16-23. Register Call Summary for Register TISR 2731 ........................16-24. TIER 2731 ................16-25. Register Call Summary for Register TIER 2732 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 151 2756 ............16-72. Register Call Summary for Register WD_SYSCONFIG 2757 ...................... 16-73. WD_SYSSTATUS 2757 ............16-74. Register Call Summary for Register WD_SYSSTATUS 2758 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 152 2821 ..............17-22. Register Call Summary for Register I2C_STAT 2824 ........................17-23. I2C_WE 2824 ..............17-24. Register Call Summary for Register I2C_WE 2826 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 153 2862 ............. 18-11. Register Call Summary for Register HDQ_TX_DATA 2862 ......................18-12. HDQ_RX_DATA 2863 ............. 18-13. Register Call Summary for Register HDQ_RX_DATA 2863 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 154 19-38. UART/IrDA/CIR Instance Summary 2928 ................19-39. UART/IrDA/CIR Register Summary Part 1 2928 ................19-40. UART/IrDA/CIR Register Summary Part 2 2929 ........................ 19-41. DLL_REG 2931 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 155 2956 .............. 19-88. Register Call Summary for Register RESUME_REG 2957 ......................19-89. TXFLH_REG 2957 ..............19-90. Register Call Summary for Register TXFLH_REG 2957 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 156 20-5. McSPI Clocks 2988 ......................20-6. Power Domain 2988 ....................20-7. McSPI Hardware Reset 2988 ......................20-8. DMA Requests 2989 ...................... 20-9. Interrupt Requests 2990 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 157 21-9. McBSP Transmit Interrupt Requests 3087 ................. 21-10. McBSP Receive Interrupt Requests 3087 ..................21-11. McBSP Transmit Interrupt Events 3087 ..................21-12. McBSP Receive Interrupt Events 3088 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 158 3168 ............ 21-59. Register Call Summary for Register MCBSPLP_XCR1_REG 3169 ..................... 21-60. MCBSPLP_SRGR2_REG 3169 ..........21-61. Register Call Summary for Register MCBSPLP_SRGR2_REG 3170 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 159 21-107. Register Call Summary for Register MCBSPLP_XINTCLR_REG 3188 ..................21-108. MCBSPLP_ROVFLCLR_REG 3189 ........... 21-109. Register Call Summary for Register MCBSPLP_ROVFLCLR_REG 3189 ..................21-110. MCBSPLP_SYSCONFIG_REG 3190 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 160 22-9. High-Speed USB Controller Register Summary 3229 ......................22-10. OTG_REVISION 3229 ............22-11. Register Call Summary for Register OTG_REVISION 3229 ..................... 22-12. OTG_SYSCONFIG 3230 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 161 22-55. High-Speed USB Host Subsystem Instance Summary 3285 ....... 22-56. USBTLL Registers Mapping Summary (L4-Core Interconnect Register Space) 3286 ................22-57. UHH_config Registers Mapping Summary 3287 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 162 22-103. Register Call Summary for Register ULPI_USB_INT_EN_RISE_SET_i 3307 .................. 22-104. ULPI_USB_INT_EN_RISE_CLR_i 3307 ........22-105. Register Call Summary for Register ULPI_USB_INT_EN_RISE_CLR_i 3308 ..................22-106. ULPI_USB_INT_EN_FALL_i 3308 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 163 3322 .......... 22-153. Register Call Summary for Register ULPI_VENDOR_INT_LATCH_i 3322 ...................... 22-154. UHH_REVISION 3322 ............22-155. Register Call Summary for Register UHH_REVISION 3322 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 164 22-201. Register Call Summary for Register HCRHDESCRIPTORA 3338 ....................22-202. HCRHDESCRIPTORB 3338 ............ 22-203. Register Call Summary for Register HCRHDESCRIPTORB 3338 ......................22-204. HCRHSTATUS 3339 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 165 24-2. MMC/SD/SDIO2 I/O Description 3369 ..........24-3. Relation Between Configuration and Name of Response Type 3373 ................ 24-4. Smart Idle Mode and Wake-Up Capabilities 3377 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 166 24-50. Register Call Summary for Register MMCHS_ARG 3436 ......................24-51. MMCHS_CMD 3437 ............... 24-52. Register Call Summary for Register MMCHS_CMD 3439 ......................24-53. MMCHS_RSP10 3439 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 167 3492 ............25-18. Register Call Summary for Register GPIO_SYSSTATUS 3492 ....................25-19. GPIO_IRQSTATUS1 3492 ............25-20. Register Call Summary for Register GPIO_IRQSTATUS1 3493 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 168 26-3. Memory Preferred Booting Configuration Pins After POR 3517 ............26-4. Peripheral Preferred Booting Configuration Pins After POR 3518 ..............26-5. Booting Configuration Pins After a Warm Reset 3519 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 169 26-51. SDRC Register Organization in the SCM Block 3580 ....................26-52. Debug POR Signals 3582 ..................... 26-53. Debugger Address Space 3583 ....................... 27-1. JTAG Pins 3588 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 170 27-47. Register Call Summary for Register SDTI_SYSCONFIG 3623 ....................27-48. SDTI_SYSSTATUS 3623 ............27-49. Register Call Summary for Register SDTI_SYSSTATUS 3623 ......................27-50. SDTI_WINCTRL 3624 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 171 3638 ............27-97. Register Call Summary for Register COMPONENT_ID2 3638 ..................... 27-98. COMPONENT_ID3 3638 ............27-99. Register Call Summary for Register COMPONENT_ID3 3638 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 172 ....................A-27. McSPI I/O Description 3692 ..................... A-28. McSPI Instance Summary 3693 ....................A-29. Input/Output Description 3693 .................... A-30. McBSP Instance Summary 3695 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 173 GPIO Channel Description 3709 ............B-7. Core Control Module Pad Configuration Register Fields 3712 ............B-8. WKUP Control Module Pad Configuration Register Fields 3722 SWPU177N – December 2009 – Revised November 2010 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated...
Page 174 List of Tables SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 175 TI Embedded Processors Wiki — Texas Instruments Embedded Processors Wiki Established to assist developers using the many Embedded Processors from Texas Instruments to get started, help each other innovate, and foster the growth of general knowledge about the hardware and software surrounding these devices.
Page 176 If You Need Assistance. . . www.ti.com If You Need Assistance. . . If you want to . . . Do this . . . Request more information about Texas Instruments Digital Call the CRC hotline: Signal Processing (DSP) products (800) 336−5236...
Page 177 The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. SWPU177N – December 2009 – Revised November 2010 Read This First Copyright © 2009–2010, Texas Instruments Incorporated...
Page 178 After each register description, a table summarizes all hyperlinked register calls. To navigate in the PDF documents, see Acrobat Reader Tips. Read This First SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 179 Starts with the module name and is followed by the #define SMS_ERR_TYPE *((volatileUint32*)0x680080F4) register name #define MCBSP2_RCR1_REG *((volatile Uint32*)0x4807401C) Enumeration Starta with the module name Typedef enum DMA_Mode_Label INPUT_MODE OUTPUT_MODE } DMA_Mode_t; SWPU177N – December 2009 – Revised November 2010 Read This First Copyright © 2009–2010, Texas Instruments Incorporated...
Page 180 Parallel mode (ISO) Beginning or end of two or more simultaneous operations Flow Line Lines indicate the sequence of steps and the direction of flow. Read This First SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 181 Click the Go To Previous View button or the Go To Next View button. NOTE: This navigation tip is useful to return to your previous view after clicking on a register call hyperlink. SWPU177N – December 2009 – Revised November 2010 Read This First Copyright © 2009–2010, Texas Instruments Incorporated...
Page 182 MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary Read This First SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 183 CoreSight, Java and Neon are trademarks of ARM Limited. Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is licensed to Texas Instruments. Memory Stick is a registered trademark of Sony Corporation, and Memory Stick PRO is a trademark of Sony Corporation.
Page 184 Chapter 13: System Control Module • Chapter 22: High-Speed USB Host Subsystem and High-Speed USB OTG Controller • Chapter 26: Initialization • Appendix A: OMAP3621 Multimedia Device Read This First SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 185 K and version L: • Chapter 3: Power, Reset, and Clock Management • Chapter 7: Display Subsystem • Chapter 13: System Control Module SWPU177N – December 2009 – Revised November 2010 Read This First Copyright © 2009–2010, Texas Instruments Incorporated...
Page 186 Chapter 13: System Control Module • Chapter 26: Initialization • Appendix A: OMAP36xx Multimedia Device in CYN Package • Appendix B: OMAP36xx Multimedia Device in CUS Package Read This First SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 187 ........................... Topic Page ......................Overview ....................Environment ..................... Description ....................POP Concept .................... OMAP36xx Family ..................Device Identification SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 188 • Connectivity to various cellular modem chipset • Memory stacking feature using the package-on-package (POP) implementation (see Section 1.4, Package-on-Package Concept) Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 189 (IC). TI provides a global solution with the TWL50xx device. Figure 1-1 is an overview of a nonexhaustive environment for the OMAP36xx device. SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 190: Omap36Xx High-Tier Environment
3D accelerometer McBSP2 FingerPrint I2C2 CVIDEO HSUSB0 I2C4/SR I2C1 Main display TWL50xx WVGA S-VIDEO Y/C Subdisplay TI – TSC200x Touchscreen controller Display subsystem intro_177-001 190 Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 191: Omap36Xx High-Tier Block Diagram
Interrupt controller (MPU INTC) of 96 synchronous interrupt lines • Asynchronous interface with core logic • Debug, trace, and emulation features: ICECrusher™, ETM™, and ETB™ modules SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 192 – Improved loop filtering (iLF) dedicated hardware – Improved variable length coder/decoder (iVLCD) with quantizing capabilities dedicated hardware – Video dedicated sequencer – Video local interconnect Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 193 The device embeds one generic DMA controller, the system DMA (sDMA) controller used for memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers: • One read port, one write port • 32 prioritizable logical channels SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 194 The device uses the following multimedia accelerators for display and gaming effects as well as high-end imaging and video applications. NOTE: The SGX subsystem is an instantiation by Texas Instruments of the POWERVR® SGX530 core from Imagination Technologies Ltd. This document contains materials that are ©2003-2007 Imagination Technologies Ltd.
Page 195 High-speed controller that offers high-speed data transactions (up to 480 Mbps) on a USB port (ULPI 12 bits) with embedded DMA controller • High-speed MMC/SD/SDIO 1/2/3: SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 196 Mailbox: MPU/IVA2.2 interprocessor communications (six in stacked mode, two in stand-alone mode) ICR (only in stacked mode) • Control module: I/O multiplexing and chip-configuration control Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 197: Pop Concept
POP interface. NOTE: For other types of memory, the traditional GPMC interface can be used through the board. SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 198: Stacked Memory Package On The Pop Device
OMAP3630-600 (available in CBP, CBC, and CUS packages) • OMAP3630-800 (available in CBP, CBC, CBK, and CUS packages) • OMAP3630-1000 (available in CBP, CBC, CBK, and CUS packages) Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 199: Omap36Xx Packages
OMAP3621-800 OMAP3615- 1000 OMAP3615-800 OMAP3611-800 Table 1-3. Device Features OMAP3630-600/OMAP3630- 800/ OMAP3615-800/ Feature OMAP3622-1000 OMAP3621-800 OMAP3611-800 OMAP3630-1000/OMAP3630- OMAP3615-1000 1200 2D/3D graphics accelerator (SGX) Full-speed clock SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 200 RESERVED RESERVED 71:64 DEVICE_TYPE 0xF0: GP device Other values: Reserved 63:9 RESERVED RESERVED RESERVED This information is not available in the public domain. RESERVED RESERVED Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 201: Device Identification Registers
The silicon type can be read in the value of the CONTROL.CONTROL_IDCODE[27:12] HAWKEYE bit field. The silicon revision can be read in the value of the CONTROL.CONTROL_IDCODE[31:28] bit field. SWPU177N – December 2009 – Revised November 2010 Introduction Copyright © 2009–2010, Texas Instruments Incorporated...
Page 202: Control_Idcode Register Definition
Table 1-11. CONTROL_PRODUCTION_ID Register Silicon Type Identification Silicon Type Bit Field Value OMAP36xx all revisions CONTROL.CONTROL_PRODUCTION_ID[127:96] 0xCAFEB891 Table 1-12. CONTROL_DIE_ID Field Bits Value Comment DIE_ID[127:0] – Single die identifier Introduction SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 203 ........................... Topic Page ....................Introduction ................. Global Memory Space Mapping ..............L3 and L4 Memory Space Mapping ............IVA2.2 Subsystem Memory Space Mapping SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 204 (L3 and L4 interconnects) and protection mechanisms implemented in the device, see Chapter 9, Interconnect. Figure 2-1 shows the interconnect of the device and the main modules and subsystems in the platform. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 205: Interconnect Overview
ICR, camera ISP, HS USB OTG, MODEM INTC, MPU INTC Stacked memories External and stacked memories L4 interconnect (wake-up) GPTIMER1, WDT2, GPIO1, 32KTIMER External peripherals ports memmap-177-001 SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 206 Table 2-1 describes the global memory space mapping. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 207: Global Memory Space Mapping
SDRC/SMS Boot space location depends on the external sys_boot5 pin configuration. Executable Peripherals connected to the L4-Wakeup interconnect are accessed through the L4-Core interconnect. SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 208 0xFFFF FFFF 512MB SDRC-SMS virtual address virtual space 1 Address space 1 Chip-select 0 and chip-select 1 spaces are configurable in the 1-GB SDRC/SMS space. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 209: L3 Control Register Mapping
OCM ROM TA 0x6800 2C00 0x6800 2FFF OCM ROM target port agent configuration D2D IA 0x6800 3000 0x6800 33FF Die-to-die (D2D) initiator port agent configuration SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 210 NOTE: All memory spaces described as modules provide direct access to module registers outside the L4-Core interconnect. All other accesses are internal to the L4-Core interconnect. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 211: L4-Core Memory Space Mapping
The registers mapped in this range are shadow registers of the first 2-KB region A [0x4800 4000 – 0x4800 47FF]. Region A and region B share the same port. SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 212 32KB Reserved 0x480C 9000 0x480C 9FFF Module 0x480C A000 0x480C AFFF L4 interconnect 0x480C B000 0x480C BFFF Module 0x480C C000 0x480C CFFF L4 interconnect Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 213: L4-Wakeup Memory Space Mapping
The registers mapped in this range are shadow registers of the first 2-KB region A [0x4830 6000 – 0x4830 67FF]. Regions A and B share the same port. SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 214: L4-Peripheral Memory Space Mapping
GPTIMER6 0x4903 A000 0x4903 AFFF Module 0x4903 B000 0x4903 BFFF L4 interconnect GPTIMER7 0x4903 C000 0x4903 CFFF Module 0x4903 D000 0x4903 DFFF L4 interconnect Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 215: L4-Emulation Memory Space Mapping
L4 interconnect TPIU 0x5401 9000 0x5401 9FFF Module 0x5401 A000 0x5401 AFFF L4 interconnect 0x5401 B000 0x5401 BFFF Module 0x5401 C000 0x5401 CFFF L4 interconnect SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 216: Register Access Restrictions
Table 2-7. Register Access Restrictions Module Allowed Access (Bits) MPU subsystem 8/16/32 IVA2.2 subsystem SGX subsystem Camera ISP 8/16/32 Display subsystem Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 217 WDTIMER 16/32 8/16 HDQ/1-Wire McBSP Sidetone 8/16/32 McSPI 8/16/32 UART 8/16/32 MMC/SD/SDIO Mailbox 8/16/32 MPU INTC 16/32 MODEM INTC (chassis mode only) 16/32 8/16/32 SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 218 This section describes the hardware accelerators of IVA2.2. In unavailable modules and features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior. The device includes the high-performance Texas Instruments IVA2.2. For more information, see Chapter 5, IVA2.2 Subsystem.
Page 219: Iva2.2 Subsystem Memory Hierarchy
32, or 64KB to cache. When 64KB are allocated to cache, 32KB are still allocated to memory-mapped L2. Figure 2-3 is an example of the L1D RAM cache allocation, where 16KB are allocated to cache. SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 220: L1D Ram Cache Allocation Example (L3 Interconnect View)
The IVA2.2 memory management unit (IVA2.2 iMMU) handles the virtual-to-physical address translation based on the software configuration (typically under control of the MPU subsystem). Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 221: Iva2.2 Immu Address Translation
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space Table 2-9 lists the IVA2.2 subsystem memory space mapping internally from the perspective of the DSP. SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 222: Dsp View Of The Iva2.2 Subsystem Memory Space
IVA2.2 internal memories are reachable in the [0x007E 0000-0x00F1 7FFF] and [0x107E 0000-0x10F1 7FFF] (aliasing) ranges. For more information, see Chapter 5, IVA2.2 Subsystem. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 223: Edma View Of The Iva2.2 Subsystem Memory Space
0x10E0 8000 0x10F0 3FFF 1008 Reserved L1D RAM 0x10F0 4000 0x10F0 FFFF IVA2.2 internal memories L1D RAM (cache) 0x10F1 0000 0x10F1 7FFF IVA2.2 internal memories SWPU177N – December 2009 – Revised November 2010 Memory Mapping Copyright © 2009–2010, Texas Instruments Incorporated...
Page 224 3,915,776 Controlled by the IVA2.2 MMU to access memories and peripherals external to the IVA2.2 subsystem For more information, see Chapter 5, IVA2.2 Subsystem. Memory Mapping SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 225 PRCM Integration ................PRCM Functional Description ..............PRCM Basic Programming Model ................PRCM Use Cases and Tips ..................PRCM Register Manual SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 226: Comparison Of Energy Consumption With/Without Dvfs
DVFS to the same process executed at optimal frequency and voltage using DVFS, based on the task requirements. If a task that must terminate in 4 seconds is performed at Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 227: Smartreflex Example
OPP. For a given device operating frequency, the device voltage is automatically adapted to maintain performance of the device. This ensures optimal power consumption for a given OPP. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 228: Comparison Of Energy Consumed With/Without Dps
3.1.2.4 Standby Leakage Management Standby leakage management (SLM) is a power-management technique that reduces standby power consumption by reducing power leakage. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 229 This ensures optimal process completion time and application of DPS. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 230: Performance Level And Applied Power-Management Techniques
Thus, a clock domain allows control of dynamic power consumption by the device. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 231: Generic Clock Domain
Voltage domain 2 Power domain Varray Array on power on NON-RTA Memory Memory array array Logic Memory Bank logic Memory prcm-093 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 232 A voltage domain is a group of modules supplied by the same voltage regulator (embedded or external). The power consumption of this group can be controlled by regulating its voltage independently. Figure 3-7 shows the voltage domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 233: Generic Voltage Domain
Each clock in a power domain, with an independent gating control, is a separate clock domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 234: Voltage, Power, And Clock Domain Hierarchical Architecture
The clocks delivered to the modules in the device are divided into two categories: interface clocks and functional clocks (see Figure 3-9). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 235: Functional And Interface Clocks
NOTE: The functional clocks do not have the autoidle clock scheme, and the software must gate the functional clock of each module when it is not needed. Initiator SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 236 Figure 3-10 is a functional overview of the SmartReflex voltage-control architecture of the device connected to an external power integrated circuit (IC). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 237: Smartreflex Voltage-Control Functional Overview
SMPS and acknowledges its reception. In manual control, the voltage processor is bypassed. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 238 SMPS and acknowledges its reception. In automatic mode, the software does not intervene in voltage control; the entire loop is handled by the hardware modules. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 239: Prcm Overview
The PRCM module is fully configurable through its L4 interface port. Figure 3-11 is an overview of the PRCM module and its internal connections with a generic power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 240: Prcm Overview
CORE power domain System control module ctrl vdd_mpu_iva VDD1 vdd_core VDD2 Domain voltage VDD3 vdda_wkup_bg_bb VDD4 vdda_sram VDD5 prcm-010 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 241 • Controlling external supply voltage regulation through dedicated high-speed (HS) I C interface • CM implementation of RFFs to support DPS SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 242: Prcm Functional External Interface (Detailed View)
It receives power control commands (voltage scaling and power switching) from the device and provides the necessary voltages and reset signals. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 243: External Clock Interface
Reset cannot be released without 32K stable and running sys_clkreq depends on sys_boot6 sys_altclk is not enabled by default SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 244: Prcm External Clock Sources
The sys_nrespwron assertion also causes assertion of sys_nreswarm. Figure 3-15 shows the external reset signals. Table 3-3 lists the external reset signals, I/Os, and module reset values. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 245: External Reset Signals
Commands the external power IC for control of VDD1 and VDD2 voltages Shared by the VMODE interface and the SmartReflex dedicated C interface I = Input; O = Output SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 246: Prcm Integration
System clock oscillator control for device-level sleep/wake-up transitions Figure 3-17 shows details of the control interface to a generic power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 247: Prcm Integration
To significantly reduce leakage in sleep modes (SLM strategy) and to optimize active power consumption (DPS strategy), the device is segmented into 18 power domains (see Figure 3-18). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 248: Device Power Domains
(domains) can be switched off or put in retention state while others remain active. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 249: Prcm Power Domains
PRM logic operates on the system clock and is released from reset on release of the reset PRM_RSTPWRON. Figure 3-19 shows the PRCM reset signals. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 250: Prcm Reset Signals
PRCM_MPU_IRQ: Mapped to the MPU INTC module (M_IRQ_11 interrupt line) • PRCM_IVA_IRQ: Mapped to the IVA2.2 WUGEN module (IVA2_IRQ[12] interrupt line) Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 251: Reset Manager Interface With Generic Power Domain
3.5.1.2 General Characteristics of Reset Signals Reset signals can be categorized based on three criteria: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 252 Hardware reset: Triggered by a signal from a hardware module inside or outside the PRCM module 3.5.1.3 Reset Sources Figure 3-21 is an overview of the reset sources. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 253: Reset Sources Overview
Bidirectional pin External hardware warm reset H = Hardware reset, S = Software reset, C = Cold reset, W = Warm reset SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 254: Local Reset Sources
• Because the modem reset signals are not supported in the device stand-alone configuration, they are not discussed in this section. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 255: Reset Destination Overview
EMU_RSTPWRON CORE_RSTPWRON_RET BANDGAP_RSTPWRON Bandgap CM_RSTPWRON_RET USBHOST_RST USBHOST * The green region in the figure represents the boundary of the PRCM prcm-021 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 256: Mpu Power Domain Reset Signal
Resets the clock manager I = Input; O = Output Source for an input signal and destination for an output signal 256 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 257: Dss Power Domain Reset Signal
3.5.1.5.9 WKUP Power Domain The WKUP power domain has three reset input signals and two reset output signals (see Table 3-17). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 258: Wkup Power Domain Reset Signals
They are asserted for any type of global cold reset. 3.5.1.5.13 EFUSE Power Domain The EFUSE power domain has one reset input signal (see Table 3-21). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 259: External Warm Reset Interface
However, a reset status bit is always logged when the reset is released to the domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 260 NOTE: The power domain must be ready (the domain clocks must be active) before its reset is released. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 261: Device Reset Manager Overview
Global warm reset Device reset Global power on reset MPU_WD_RST manager Registers warm reset sys_nrespwron External warm sys_nreswarm_in reset assertion logic sys_nreswarm_out prcm-023 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 262: Power Domain Reset Management: Part
CORE_RST reset manager 1 CORE_DOM_RET_RST CORE_RST_RET CORE domain reset manager 2 CORE_RSTPWRON_RET CORE_DOM_RET_RST CORE domain USBTLL_RST reset manager 4 CORE_DOM_RST prcm-024 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 263: Power Domain Reset Management: Part
1 CORE_DOM_RET_RST PER domain PER_RST_RET PER_DOM_RET _RST reset manager 2 CORE_DOM_RET_RST USBHOST_RST USBHOST domain USB_DOM_RST reset manager CORE_DOM_RET_RST prcm-025 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 264: Power Domain Reset Management: Part
DPLL3_SW_RST DPLL3_DOM_RST DPLL4 domain DPLL4_RSTPWRON reset manager DPLL4_DOM_RST DPLL5 domain DPLL5_RSTPWRON reset manager DPLL5_DOM_RST SMARTREFLEX SR_RST domain reset SR_DOM_RST manager prcm-026 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 265: Global Reset Summary
The shaded blocks identify the power domain reset signals triggered as a result of the reset source signal (at the head of the column). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 266: Local Reset Summary
The shaded blocks identify the power domain reset signals triggered as a result of the reset source signal (at the head of the column). 266 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 267 SW_RST DEVICE_ RST1 RST2 RST3 RESET DPLL3 DPLL3_RSTPWRON DPLL4 DPLL4_RSTPWRON DPLL5 DPLL5_RSTPWRON SR_RST EFUSE EFUSE_RSTPWRON BANDGAP BANDGAP_RSTPWRON Device pad (output) sys_nreswarm_out SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 268: Power-Up Sequence
Global power on reset Global warm reset SYS_CLK EFUSE_RSTPWRON PRM_RSTPWRON CM_SYS_CLK CM_RSTPWRON_RET DPLL[1,2,3,4,5]_ RSTPWRON DPLL3_ALWON_FCLK L3_ICLK CORE_RST DPLL1_ALWON_FCLK MPU_CLK MPU_RST prcm-096 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 269 Power domains such as DSS, CAM, SGX, and NEON are held under reset after power up until the MPU software enables the power domain interface clocks. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 270 The system is running: – Resets are released. – CORE DPLL and processor DPLL are locked. Figure 3-29 shows the global warm reset sequence. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 271: Warm Reset Sequence
The device reset manager resets part of the device by asserting the global warm reset. • The external warm reset (sys_nreswarm_out) is asserted. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 272 All sources of reset to the IVA2.2 subsystem are released except for the software sources of reset. Figure 3-30 shows the IVA2.2 power-up sequence. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 273: Iva2.2 Subsystem Power-Up Reset Sequence
PRCM Functional Description www.ti.com Figure 3-30. IVA2.2 Subsystem Power-Up Reset Sequence prcm-029 The sequence is: 1. Software enables the IVA2.2 subsystem clock. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 274 IVA2 power domain clocks are running. • The software clears the previous reset status. Figure 3-31 shows the IVA2 software reset sequence. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 275: Iva2 Software Reset Sequence
1. DSP software puts the SEQ in idle, and can safely assert the IVA2 power domain software reset. 2. The PRM module asserts the IVA2_RST3 reset asynchronously. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 276 All sources of reset to the IVA2.2 subsystem are released. • Software clears the previous reset status. Figure 3-32 shows the IVA2 global warm reset sequence. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 277: Iva2 Global Warm Reset Sequence
Figure 3-32. IVA2 Global Warm Reset Sequence prcm-031 The sequence is: 1. A global warm reset source is asserted (see sys_nreswarm in Figure 3-32). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 278 IVA2 clocks are running. • The software clears the previous reset status. Figure 3-33 shows the IVA2 power domain wake-up cold reset sequence. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 279: Iva2 Power Domain Power Transition Reset Sequence
Figure 3-33. IVA2 Power Domain Power Transition Reset Sequence prcm-032 The sequence is: 1. DSP software puts the SEQ in inactive state. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 280 The release of the IVA2_RST3 reset is stalled as long as the IVA2_RST2 reset is not released. • The release of the IVA2_RST2 and IVA2_RST1 resets causes IVA2 to deassert the IVA2_RSTDONE signal. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 281 • Level shifter control • External power IC control Figure 3-34 is an overview of PRM power management in the device. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 282: Power Control Overview
EMU: Emulation • SMARTREFLEX: SmartReflex modules • EFUSE: eFuse farm • DPLL1: MPU DPLL • DPLL2: IVA2.2 DPLL • DPLL3: CORE DPLL Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 283: Power Domain Modules
MPU INTC OCM_RAM OCM_ROM SDRC L3 interconnect UART[1, 2] SDMA Temperature sensor (x2)] L4-Core interconnect Display subsystem Video DAC Camera subsystem SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 284 As a consequence, RTA memories do not have any retention mode control signal coming from the PRCM. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 285: Power Domain States
The device supports six transitions: • Active to inactive • Inactive to active • Active to retention • Retention to active • Active to off SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 286: Domain Power Control Summary
L1 flat cache SRAM On-off BB retention L2 cache SRAM On-off BB retention L2 flat cache SRAM On-off BB retention 286 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 287 CSWR SRAM bank 4: Corresponds to memories that are retained only in case of CSWR (all logic is maintained with reduced voltage). These memories are USB and MAILBOXES. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 288 Wake-up dependencies: Used to initiate a wake-up transition on a power domain as a consequence of a linked power domain wake-up transition Two dedicated sets of registers (PRCM.CM_SLEEPDEP_<domain> and PRCM.PM_WKDEP_<domain>) allow the setting of programmable dependencies. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 289 PRCM.PM_PWSTCTRL_<domain_name> registers allow selection of the state to which the logic and memory go when the power domain is put in retention. They also allow selection of the state to which SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 290 For details, see Section 3.6, Basic Programming Model, and Section 3.8,PRCM Registers Manual. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 291 DPLLs; clock division and gating are handled by the PRM and the CM sections of the PRCM module. Figure 3-35 shows the high-level clock-management scheme in the device. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 292: Prcm Clock Manager Overview
For example, the functional clock of a general-purpose timer (GPTIMER) must be active for it to run, but its interface clock can be turned off. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 293: External Clock I/O
Internal oscillator is enabled. Square clock (1.8-V CMOS signal) sys_xtalin (sys_xtalout is not connected) Internal oscillator is bypassed. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 294: External Clock I/Os
The device generates internal clocks from following sources: • • • DPLLs Figure 3-37 shows the internal clock-generation scheme of the device. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 295: Internal Clock Sources
Figure 3-37. Internal Clock Sources MPU_CLK SYS_CLK 32K_FCLK IVA2_CLK L4_ICLK L3_ICLK 96M_FCLK 48M_FCLK 12M_FCLK DSS_TV_CLK CORE_CLK COREX2_CLK CAM_MCLK EMU_PER_ALWON_CLK DSS1_ALWON_FCLK 96M_ALWON_FCLK 120M_FCLK prcm-036 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 296 Figure 3-38 is a functional overview of the PRM. The other clocks in the figure are explained in the following sections. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 297: Prm Clock Generator
Public Version PRCM Functional Description www.ti.com Figure 3-38. PRM Clock Generator PRM control prcm-037 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 298 The 96-MHz clock input from the PRM to the CM (CM_96M_FCLK) is internally gated by the CM. Figure 3-39 is the functional overview of the CM. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 299: Cm Clock Generator Functional Overview
12M_FCLK 48M_FCLK DPLL4_M2_CLK 96M_FCLK COREX2_CLK DPLL3_M2X2_CLK DPLL2_FCLK DPLL1_FCLK CORE_CLK DPLL3_M2_CLK L3_ICLK L4_ICLK CM_96M_FCLK CM_SYS_CLK RM_ICLK (to PRM) sys_clkout2 120M_FCLK DPLL5_M2_CLK prcm-038 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 300 The DPLLs are of two types. Type A DPLLs are DPLL1, DPLL2, DPLL3 and DPLL5. Type B DPLL is DPLL4. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 301: Generic Dpll Functional Diagram
• CLKOUT_M5X2 = CLKOUTX2/M5 • CLKOUT_M6X2 = CLKOUTX2/M6 where M2, M3, M5, and M6 are additional dividers for the DPLL-synthesized clock. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 302 DPLLs during frequency scaling. 3.5.3.3.3.1.2 DPLL3 (CORE) Figure 3-41 is a block diagram of DPLL3. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 303: Dpll3 Clocks
DPLL3 can be used as HS bypass clock input to DPLL1 and DPLL2. 3.5.3.3.3.1.3 DPLL5 (Peripherals) Figure 3-42 is a block diagram of DPLL5. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 304: Dpll5 Clocks
DPLL5 generates clocks for the peripherals, supplying five clock sources: • 120-MHz functional clock to the peripheral domain modules Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 305: Dpll4 Functional Diagram
The user must select which one of the digitally controlled oscillators (DCO) of the DPLL4 is used, depending on the targeted lock frequency. This is done in CM_CLKSEL2_PLL[23:21] DCO_SEL. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 306: Dpll4 Clocks
DPLL4 receives its reference clock (DPLL4_ALWON_FCLK), which is the SYS_CLK from the PRM, and can be divided before feeding the DPLL4. This is done in the PRM through dedicated programmable Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 307 Camera sensor clock • Emulation trace clock The clock outputs to the DSS, PER, and EMU power domains are always on. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 308: Low-Jitter Dpll Output Clocks
L3 interconnect interface clock L4_ICLK DPLL3 L4 interconnect interface clock MPU_CLK DPLL1 MPU subsystem source clock IVA2_ CLK DPLL2 IVA2.2 subsystem source clock Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 309: Mpu Power Domain Clocking Scheme
IVA2_CLK. All clocks are then locally generated by a clock generator in the IVA2.2 subsystem. Figure 3-46 shows the clocking scheme in the IVA2 power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 310: Iva2 Power Domain Clocking Scheme
COREX2_CLK, its frequency can be divided (by 3 or 5). Figure 3-47 shows the clocking scheme in the SGX power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 311: Sgx Power Domain Clocking Scheme
13, System Control Module. Figure 3-48 through Figure 3-50 show the clock signals and their relationships in the CORE power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 312: Core Clock Signals: Part
L4_ICLK L3 interconnect SDMA Async - slave HS USB Async 1 - slave aster Async 2 - m GPMC SDRC prcm-045 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 313: Core Clock Signals: Part
HDQ/1-wire EMU async bridge McSPI[1–4] I2C[1, 2, 3] GPT11_FCLK GPTIMER Temp. sensor (x2) [10, 11] GPT10_FCLK McBSP[1, 5] USB TLL prcm-046 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 314: Core Clock Signals: Part
System control prcm-047 3.5.3.4.1.5 EFUSE Power Domain Figure 3-51 shows the clock signals and their relationships in the EFUSE power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 315: Efuse Clock Signals
Figure 3-52 shows the clock signals and their relationships in the DSS power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 316: Dss Clock Signals
Figure 3-53 shows the clock signals and their relationships in the CAM power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 317: Cam Clock Signals
(CAM_MCLK) is provided by DPLL4 to supply the external sensor. 3.5.3.4.1.8 USBHOST Power Domain Figure 3-54 shows the clock signals and their relationships in the USBHOST power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 318: Usbhost Clock Signals
SAVEANDRESTORE bit) and on the USBHOST power domain state transitions. 3.5.3.4.1.9 WKUP Power Domain Figure 3-55 shows the clock signals and their relationships in the WKUP power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 319: Wkup Clock Signals
CORE L4 interconnects is asynchronous. 3.5.3.4.1.10 PER Power Domain Figure 3-56 shows the clock signals and their relationships in the PER power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 320: Per Clock Signals
The two SmartReflex modules in the device have a common L4 interface clock (SR_L4_ICLK) and a functional clock (SR_ALWON_FCLK) (see Figure 3-57). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 321: Smartreflex Clock Signals
SMARTREFLEX power domain prcm-053 3.5.3.4.1.12 DPLL Domains The PRCM module provides clock sources for the five DPLLs, as shown in Figure 3-58. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 322: Dpll Clock Signals
PRCM Functional Description www.ti.com Figure 3-58. DPLL Clock Signals DPLL5_M2X2_CLK DPLL4_M6X2_CLK DPLL4_M5X2_CLK DPLL4_M4X2_CLK DPLL4_M3X2_CLK DPLL4_M2X2_CLK 96M_ALWON_FCLK DPLL3_M3X2_CLK DPLL3_M2_CLK DPLL3_M2X2_CLK DPLL2_M2_CLK DPLL1_M2_CLK prcm-054 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 323: Clock Distribution
Normal Camera subsystem CSi2_96M_FCLK Normal CSI2 interface 96M_ALWON_FCLK Always-on McBSP[2..4] PER_48M_FCLK Normal UART[3, 4] PER_32K_ALWON_FCLK Always-on WDTIMER3, GPIO[2..6], GPT2_ALWON_FCLK Always-on GPTIMER2 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 324: Mode)
GPTIMER11, McBSP2, McBSP3, McBSP4. UART3, UART4, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, WDT3, GPTIMER2, GPTIMER3, GPTIMER4, GPTIMER5, GPTIMER6, GPTIMER7, GPTIMER8 and GPTIMER9) Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 325: Peripheral Module Functional Clock Frequencies
If the PRM_POLCTRL[1] CLKREQ_POL bit = 1, the software must configure the SCM to select the internal pulldown on the sys_clkreq pad, or an external pulldown is connected to the pad. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 326: Sys_Clkreq Pad Direction Control
Thus, the device oscillator has two possible operating modes: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 327: System Clock Operation Modes
This delay is configured in the PRCM.PRM_CLKSETUP[15:0] SETUP_TIME bit field. Figure 3-59 shows the system clock oscillator controls in the device. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 328: System Clock Oscillator Controls
If the PRCM.PRM_POLCTRL[1] CLKREQ_POL is set to active low (0x0), Asserted = 0, and Not asserted = 1. x indicates that the signal may be asserted or not asserted. 328 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 329: Dpll Multiplier And Divider Factors
3.5.3.6.2 DPLL Modes DPLL supports several power modes (see Table 3-39). Each mode results in a tradeoff between power savings and relock time. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 330: Dpll Power Modes
Global reset Global reset (automatic) (automatic) Device off Device off Device off Device off Device off (automatic) (automatic) (automatic) (automatic) (automatic) Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 331: Mode)
Table 3-42. LP Mode Control Mode Manual Control DPLL1 PRCM.CM_CLKEN_PLL_MPU[10] EN_MPU_DPLL_LPMODE DPLL2 PRCM.CM_CLKEN_PLL_IVA2[10] EN_IVA2_DPLL_LPMODE DPLL3 PRCM.CM_CLKEN_PLL[10] EN_CORE_DPLL_LPMODE DPLL4 PRCM.CM_CLKEN_PLL[26] EN_PERIPH_DPLL_LPMODE DPLL5 PRCM.CM_CLKEN2_PLL[10] EN_PERIPH2_DPLL_LPMODE SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 332: Mode)
Any access during this DLL relock period can be corrupted. It is important; therefore, to stall SDRC access during DPLL recalibration. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 333: Dpll Recalibration Controls
5. Mask/unmask the interrupt to the MPU (and the DPLL2 interrupt to IVA2) (see Section 3.5.3.6.5). 6. Enable the DPLL lock mode (see Section 3.5.3.6.2). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 334 3.5.3.7.1 PRM Source-Clock Controls Figure 3-60 shows the common source-clock controls for the PRM. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 335: Common Prm Source-Clock Controls
48M_FCLK, and 12M_FCLK) are active or 96M_FCLK, 48M_FCLK, and 12M_FCLK when SGX has its functional clock enable and its source is the 96MHz clock SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 336 The sys_clkreq active condition is described in Section 3.5.3.5, External Clock Control. 3.5.3.7.2 CM Source-Clock Controls Figure 3-61 shows the common source-clock controls for the CM. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 337: Common Cm Source-Clock Controls
CLKOUT2_EN PRCM.CM_CLKOUT_CTRL[5:3] sys_clkout2 PRCM.CM_POLCTRL[0] CLKOUT2DIV CLKOUT2_POL Ratios: 1/2/4/8/16 PRCM.CM_CLKSEL4_PLL[18:8] PRCM.CM_CLKEN2_PLL[2:0] DPLL5_ALWON_FCLK PERIPH2_DPLL_MULT EN_PERIPH2_DPLL PRCM.CM_CLKSEL4_PLL[6:0] PRCM.CM_AUTOIDLE2_PLL[2:0] PERIPH2_DPLL_DIV AUTO_PERIPH2_DPLL 120M_FCLK PRCM.CM_CLKSEL5_PLL[4:0] DIV_120M prcm-057 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 338: Common Interface Clock Controls
CORE_L4_ICLK, CAM_L4_ICLK, DSS_L4_ICLK, different modules of the device are gated PER_L4_ICLK, SR_L4_ICLK, and WKUP_L4_ICLK RM_ICLK Running None Gated with source clock (CORE_CLK) 338 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 339: Dpll Power Domain Clock Controls
Also gated if EN_PERIPH2_DPLL, and depends on DPLL is set to low-power stop mode. the clock-gating conditions of DPLL5_M2_CLK SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 340: Sgx Power Domain Clock Controls
Gated when the enable bit is set to 0 SGX_L3_ICLK Stopped PRCM.CM_ICLKEN_SGX[1] EN_SGX Gated when the enable bit is set to 0 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 341: Core Power Domain Clock Controls: Part
PRCM.CM_FCLKEN1_CORE[9] EN_McBSP1 PRCM.CM_FCLKEN1_CORE[21] EN_McSPI4 PRCM.CM_FCLKEN1_CORE[20] EN_McSPI3 48M_FCLK CORE_48M_FCLK PRCM.CM_FCLKEN1_CORE[19] EN_McSPI2 PRCM.CM_FCLKEN1_CORE[18] EN_McSPI1 PRCM.CM_FCLKEN1_CORE[14] EN_UART2 PRCM.CM_FCLKEN1_CORE[13] EN_UART1 12M_FCLK CORE_12M_FCLK PRCM.CM_FCLKEN1_CORE[22] EN_HDQ prcm-061 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 342: Core Power Domain Clock Controls: Part
0 CORE_12M_FCLK Stopped PRCM.CM_FCLKEN1_CORE[22] Gated when the enable bit is set to 0 EN_HDQ 342 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 343: Efuse Power Domain Clock Controls
Figure 3-68 shows the clock controls for the DSS power domain. Table 3-52 lists the clock-gating controls for the DSS power domain. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 344: Dss Power Domain Clock Controls
Figure 3-69 shows the clock controls for the CAM power domain. Table 3-53 lists the clock-gating controls for the CAM power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 345: Cam Power Domain Clock Controls
Table 3-54. USBHOST Power Domain Clock-Gating Controls Clock Name Reset Clock-Gating Control Gating Description USBHOST_48M_FCL Stopped PRCM.CM_FCLKEN_USBHOST[0] EN_USBHOST1 Gated when the enable bit is set to 0 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 346: Wkup Power Domain Clock Controls
• All enable-autoidle bit pairs are set to (WDT2, GPIO1, 32KSYNC, and 1, and the clock is not requested by GPTIMER1) any module. 346 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 347: Per Power Domain Clock Controls: Part
CLKSEL_GPT8 EN_GPT8 GPT9_ALWON_FCLK PRCM.CM_CLKSEL_PER[7] PRCM.CM_FCLKEN_PER[10] CLKSEL_GPT9 EN_GPT9 PRCM.CM_FCLKEN_PER[17] EN_GPIO6 PRCM.CM_FCLKEN_PER[16] EN_GPIO5 PRCM.CM_FCLKEN_PER[15] PER_32K_ALWON_FCLK EN_GPIO4 PRCM.CM_FCLKEN_PER[14] EN_GPIO3 PRCM.CM_FCLKEN_PER[13] EN_GPIO2 PRCM.CM_FCLKEN_PER[12] EN_WDT3 prcm-068 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 348: Per Power Domain Clock Controls: Part
AUTO_GPT3 PRCM.CM_AUTOIDLE_PER[3] AUTO_GPT2 PRCM.CM_AUTOIDLE_PER[2] AUTO_MCBSP4 PRCM.CM_AUTOIDLE_PER[1] AUTO_MCBSP3 PRCM.CM_AUTOIDLE_PER[0] AUTO_MCBSP2 prcm-069 Table 3-56 lists the clock-gating controls for the PER power domain. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 349: Smartreflex Power Domain Clock Controls
PRCM.CM_FCLKEN_WKUP[6] EN_SR1 and Gated when both enable bits are set to 0 PRCM.CM_FCLKEN_WKUP[7] EN_SR2 SR_L4_ICLK Running Depends on L4_ICLK activity (hardware control) SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 350 DPLL • DPLL2 (IVA2 DPLL) output clock frequency (IVA2_CLK) configured by setting the M2 parameter of the DPLL Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 351: Processor Clock Configuration Controls
L4_ICLK Table 3-60 identifies the interface clocks, their reference clocks, and the control bits for configuration of the interface clock frequencies. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 352: Interface Clock Configuration Controls
DPLL2 relock time is only a few µs. Always set the DPLL1 bypass clock to CORE_CLK/1 in the CM_CLKSEL1_PLL_MPU[20:19] MPU_CLK_SRC bit field. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 353: Power Domain Sleep/Wake-Up Transition
All these blocks interact with the global control block that handles reset management, clock generation and distribution, and all PRCM registers. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 354: Device Power Reset And Clock Controllers
The PSCON sequences all sleep and wake-up transitions between on, off, and retention modes for logic and memory. It also ensures that the domain is correctly isolated when it enters off or retention Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 355: Power-State-Related Sleep Transition Actions
Dependency: A power domain can wake up on the wakeup of another power domain. The dependency is software-controllable by configuring the PRCM.PM_WKDEP_<power domain> register. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 356: Mode)
Wake-up transition is complete transition (IVA2, NEON, SGX, USBHOST, DSS, CAM, PER, EMU domains). CM_CLKSTCTRL_NEON CM_CLKSTCTRL_SGX CM_CLKSTCTRL_DSS CM_CLKSTCTRL_CAM CM_CLKSTCTRL_PER CM_CLKSTCTRL_USBHOST CM_CLKSTCTRL_EMU 356 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 357: Neon Power Domain Wake-Up Events
PER domain PRCM PM_WKDEP_IVA2 dependency WKUP domain PRCM PM_WKDEP_IVA2 dependency Peripheral wake-up Peripherals PM_IVA2GRPSEL1_CORE IVA2.2 peripheral group event events occurred . PM_IVA2GRPSEL3_CORE SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 358: Sgx Power Domain Wake-Up Events
McSPI3 wakeup McSP 3 McSPI4 wakeup McSP 4 MMC1 wakeup MMC 1 MMC2 wakeup MMC 2 MMC3 wakeup MMC 3 358 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 359: Dss Power Domain Wake-Up Events
PRCM Software Control Wake-Up Interrupt/Type Interrupt to Wake-Up Module Event Events MPU domain PRCM PM_WKDEP_PER register dependency IVA2 domain PRCM PM_WKDEP_PER register dependency SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 360: Emu Power Domain Wake-Up Events
Internal Source PRCM Software Control Wake-Up Event Interrupt/Type Interrupt to Wake-Up Module Events Device wakeup PRCM PM_WKEN_WKUP SmartReflex1 SmartRefle wakeup 360 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 361: Clock Domain Mute Conditions
N/A (No public Initiator) power domain USBHOST USBHOST power domain USBHOST in stand-by WKUP WKUP power domain N/A (No public Initiator) SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 362 X in the first column, then follow its row to its sleep dependency with another power domain (identified in the top row). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 363: Sleep Dependencies
Abortion of the mute mode (at least one initiator in the domain exits standby mode) of PD2 when both the sleep dependency and wake-up dependency with PD1 are enabled. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 364: Wake-Up Dependencies
Table 3-76. Wake-Up Dependencies Wake-Up Dependency Power Domain Clock NEON IVA2 CORE_ CORE_ CORE_ WKUP Domain HOST RW** RW** NEON IVA2 IVA2 RW** 364 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 365 Software wakeup dependency: dependency by PM_WKDEP_<> and PM_<>GRPSEL_<> registers RW** Software wakeup dependency: dependency by PM_<>GRPSEL_<> registers Hardware wakeup dependency: dependency always enabled No wakeup dependency applicable SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 366 It does not provide the exact timing delays between the switching of the signals and serves only to highlight the sequence of events. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 367: Save-And-Restore Sequence
Public Version PRCM Functional Description www.ti.com Figure 3-77. Save-and-Restore Sequence prcm-092 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 368 4. The PRCM module activates the USBTLL_SAR_FCLK and starts the restore sequence. 5. When the restore sequence completes, USBTLL_SAR_FCLK is gated. 6. The power domain wake-up transition to ON power state completes. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 369: Interrupt Descriptions
PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Voltage processor 1 new MPU[14] VP1_ MPU[14] VP1_ voltage is the same as EQVALUE_ST EQVALUE_EN the current voltage. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 370 PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Voltage controller's MPU[28] VC_BYPASS_ MPU[28] VC_BYPASS_ acknowledge to the ACK_ST ACK_EN bypass interface status 370 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 371: Overview
IC. 3.5.6.1 Overview Figure 3-78 is an overview of the device voltage domains. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 372: Overview Of Device Voltage Domains
The PRM directly manages the following voltage sources: • VDD1: Processor voltage • VDD2: CORE voltage • VDD3: Wake-up voltage Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 373 I C interface independent of the PRM. Figure 3-79 is an overview of PRCM voltage control. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 374: Overview Of Device Voltage Distribution
NOTE: Memory I/Os (1.8 V) are not supplied with the other I/Os. They come directly from the power Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 375: Voltage Domain Controls Summary
OPP1G2 is available only for the OMAP3630-1200 device. Identifies voltage domains that can be switched to 0.0 V when the interface/module is not in use. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 376: Vdd1 Voltage Domain Dependencies
P = 1 Overdriven retention retention power AUTO_RET = domains of VDD1 and AUTO_OFF = VDD2 are in inactive, retention or off state. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 377: Remaining Voltage Domain Dependencies
– Direct software control of VDD1 and VDD2 is also possible by writing to the registers of the voltage controller, which then sends the voltage commands to the power IC through the dedicated I SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 378: Prm Voltage Control Architecture
Level shifters control WAKEUP LDO I/Os control control (VDD3) * The green region in the figure represents the boundary of the PRM. prcm-075 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 379 The power IC must be configured to switch to low voltage when the associated sys_nvmode[1,2] signal is received, and vice versa. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 380 Because the SmartReflex modules and the voltage processors are dedicated to SmartReflex voltage control, they are described together in this section. 3.5.6.5.4.1 SmartReflex in the Device Figure 3-82 shows the SmartReflex integration. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 381: Smartreflex Integration
I master interface to the power IC. 3.5.6.5.4.2 SmartReflex Module Figure 3-83 is a functional overview of the SmartReflex module. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 382: Smartreflex Module Functional Overview
SRn.SRCONFIG[21:12] SRCLKLENGTH is 192 (0x0C0). Sensor Core SR1 and SR2 instances of the SmartReflex module in the device; n varies from 1 to 2. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 383 Table 3-84 Table 3-85 list the interrupt sources in the SmartReflex module and their enable and status bits. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 384: Smartreflex Interrupts
1, the registers contain valid values, although the values are not necessarily fully accumulated. • SRn.SRSTATUS[1] ERRGEN_VALID: Indicates the validity of the value in the Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 385 SRn.ERRCONFIG[18:16] ERRWEIGHT • SRn.ERRCONFIG[15:8] ERRMAXLIMIT • SRn.ERRCONFIG[7:0] ERRMINLIMIT 3.5.6.5.4.6 Voltage Processor Module Figure 3-84 is a functional overview of the voltage processor. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 386: Voltage Processor Functional Overview
VDD. Minimum VDD MPU INTC New voltage requested in the voltage command is equal to or less than minimum VDD. 386 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 387: Voltage Processor Interrupt Enable And Status Bits
Initial voltage set in the voltage processor PRCM.PRM_VPn_CONFIG[2] INITVDD Initialize VDD Set initial voltage given in initial VDD voltage parameter in the voltage processor SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 388 SmartReflex module. The SmartReflex module then clears the VP interrupt. The SmartReflex module is again ready to send a new frequency-error interrupt to the voltage processor. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 389: Smartreflex - Smps Communication For Automatic Voltage Adjustments
OPP_CHANGE - Initiate an OPP based ABB LDO setting change • SR2_STATUS - Current mode of operation of ABB LDO • SR2_IN_TRANSITION - ABB LDO is in transition. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 390 0.82 V is set when the device is in low-power (off) mode, to minimize leakage. These modes are managed automatically by hardware. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 391 For example, the GPIO pads in the WKUP power domain can also wake up the device. NOTE: For the wake-up features of the GPIO pads , see Chapter 25, General-Purpose Interface. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 392: Device Off-Mode Control Overview
The I/O wake-up scheme is enabled by triggering the I/O daisy chain control (Wu clock) by programming a dedicated register (PRCM.PM_WKEN_WKUP[16] EN_IO_CHAIN) in the PRCM module. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 393 NOTE: When the CORE power domain is in RETENTION state, VDD2 voltage must be at retention or on voltage level to maintain stable CORE power domain output values to the I/Os. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 394 The sleep sequences exemplify the two types of device transitions from ON to OFF mode: • Device off-mode transition without using the SYS_OFF_MODE signal Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 395 Depending on the external power IC capability and the user setting, VDD1 and VDD2 voltage control may use the direct sys_off_mode signal and not send the commands through the I C interface. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 396 17. When the PRM receives the acknowledge from the SCM, it releases the MPU and CORE domain output isolations and the I/O isolation. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 397: Cm_Revision
PRM_SYSCONFIG: Holds an AUTOIDLE bit to control the PRM internal clock autogating feature 3.6.1.3 Interrupt Configuration Registers The PRM can interrupt the MPU and the IVA2.2 subsystems as a result of four events: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 398 PRM_IRQENABLE_<processor_name> register is set to 1. The recalibration flag is set by the DPLL and remains active if the DPLL is not reinitialized. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 399: Prm_Irqstatus_Mpu
1. 3.6.1.4 Event Generator Control Registers For details about the event generator module, see the public ARM Cortex-A8 technical reference manual. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 400 Figure 3-87 shows the normal behavior of sys_clkout2 when gated. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 401: Sys_Clkout2 Gating Polarity Control
At device power up, the reset values of polarity settings are OFFMODE_POL = 1 and CLKREQ_POL = 1. For details about using these signals, Section 3.5.3, Clock Manager Functional Description. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 402: Prm_Clksel
3.6.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) The PRM clock out control register provides control to enable and disable the gating of the sys_clkout1 output clock. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 403: Cm_Clksel1_Pll_Iva2
CM_CLKSEL2_PLL: DPLL4 multiplier and divider configuration • CM_CLKSEL3_PLL: Divider configuration for 96-MHz clock (96M_FCLK) • CM_CLKSEL4_PLL: DPLL5 multiplier and divider configuration SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 404: Cm_Clken_Pll_Iva2
It is also restarted automatically. The following are the device DPLL autocontrol registers: • CM_AUTOIDLE_PLL_MPU: DPLL1 autoidle mode control Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 405: Cm_Autoidle_Pll_Iva2
3.6.2.3.10 CM_IDLEST_PLL_ <processor_name> (Processor DPLL Idle-Status Register) The processor DPLL idle-status register indicates the status of the processor DPLL: whether it is in locked or bypass mode. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 406: Gfx Functional Clock Ratio Settings
Table 3-88. GFX Functional Clock Ratio Settings CM_CLKSEL_SGX.CLKSEL_SGX SGX_L3_FCLK CORE_CLK/3 CORE_CLK/4 CORE_CLK/6 CM_96M_FCLK SGX_192M_FCLK CORE_CLK/2 COREX2_CLK/3 COREX2_CLK/5 406 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 407: Cm_Fclken_Iva2
This relation is programmable and is defined in the CLOCKACTIVITY bits of the module SYSCONFIG register; therefore, it requires consistent programming of the CM_FCLKEN and CM_ICLKEN registers. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 408: Interface Clock Autoidle Settings
CM_IDLEST_NEON: NEON subsystem • CM_IDLEST_IVA2: IVA2.2 subsystem • CM_IDLEST_SGX SGX subsystem • CM_IDLEST_WKUP: WKUP domain peripherals set • CM_IDLEST_USBHOST: HS USB Host subsystem Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 409: Clock State Transition Settings
The DSS interface clock is automatically cut when it stops fetching data from the frame buffer (provided the MPU is also in standby mode, if sleep dependency in the MPU power domain is SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 410: Sleep Dependency Settings
CORE-L3 Software controlled Software controlled Software controlled Software controlled Software controlled Always enabled Software controlled USBHOST Software controlled Software controlled 410 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 411: Pm_Wken1_Core
The wake-up status register logs wake-up events from all modules. Each ST_<module> bit of this register logs a given module-generated wake-up event. The device has the following wake-up status registers: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 412: Pm_Wkdep_Iva2
– MPU • PM_WKDEP_IVA2: The IVA2 power domain has programmable wake-up dependency with the following domains: – MPU – PER – WKUP Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 413: Pm_Mpugrpsel1_Core
3.6.3.1 Reset Control 3.6.3.1.1 PRM_RSTTIME (Reset Time Register) The reset time register provides control over reset duration. Two durations are configurable: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 414: Rm_Rstctrl_Iva2
The device includes the following reset status registers: • RM_RSTST_MPU • RM_RSTST_CORE • RM_RSTST_DSS • RM_RSTST_CAM • RM_RSTST_IVA2 • RM_RSTST_PER • RM_RSTST_NEON Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 415: Prm_Rstst
Each bit of these registers is set on the effective release of the respective reset signal. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 416: Pm_Pwstctrl_Iva2
The memory is always in retention state when the power domain is in retention state. • The memory is always in on state when the power domain is in on state. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 417 Thus, the EMU domain is automatically powered down after the power-up sequence if no emulation hardware is connected. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 418: Pm_Pwstst_Iva2
(on or off), L1 cache and flat memory (on, retention, or off), L2 cache and flat memory (on, retention, or off) power state status. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 419: Pm_Prepwstst_Iva2
3.6.5 Voltage Management Registers 3.6.5.1 External Voltage Control Register Descriptions 3.6.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) The device has two voltage setup registers: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 420: Off Mode Wakeup Using I
32-kHz clock cycles, is used to delay the deassertion of sys_off_mode (and as a consequence, the voltage ramping) after the clock has been requested. This is done to avoid waiting for the clock to stabilize Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 421: Prm_Voltctrl
The register set is composed of the following registers: • Registers to store the addresses on the I C bus: – PRM_VC_SMPS_SA SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 422: Prm_Vc_Smps_Sa
Enable and disable the HS mode • Enable and disable the repeated start-operation mode • Enable and disable the HSMASTER mode Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 423: Prm_Vc_Bypass_Val
The slew rate for positive voltage step (in the number of cycles per step) The device has the following voltage processor configuration registers: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 424 CM_CLKSELn_PLL register, where n is from 1 to 3. The DPLL operating mode is set in the CM_CLKEN_PLL register. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 425: Functional Clock Basic Programming Model
NOTE: The activation or deactivation of the clock is implementation-dependent, not one cycle of the source clock, as shown in Figure 3-91. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 426: Functional Clock Switching
A module is inaccessible if its idle status bit is set. Accessing an idle module generates an error (if the interface clock is still running) or a time-out (if the interface clock is cut). Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 427: Interface Clock Basic Programming Model
The domain transition from active state to inactive state is effective only if the CM_CLKSTCTRL_<domain> register is programmed for hardware-supervised state transition. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 428: Domain Inactive State Basic Programming Model
The value of this second divider is written in the CM_CLKSEL2_PLL_<processor> register. This divider can be configured dynamically (while the processor executes instructions), and the DPLL output clock is scaled without any glitches. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 429 DPLL is in lock mode (DPLL output is a high-frequency synthesized clock) or bypass mode (DPLL output is not the synthesized clock; the DPLL output is the bypass clock, or the DPLL is in transitioning state). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 430: Processor Clock Basic Programming Model
DPLL is in low-power BYPASS mode and bypass clock is running DPLL in LOCK mode and clock is running prcm-088 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 431 The peripheral functional clock must be reenabled by programming the CM_FCLKEN_<domain > register, and then the wake-up event can be acknowledged by clearing the PM_WKST_<domain > register. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 432: Wake-Up Basic Programming Model
CORE power domain, but is programmable for the other power domains through the PM_WKDEP_<domain> register. 3.6.6.4 SmartReflex Module Initialization Basic Programming Model Figure 3-96 is a flow chart of the SmartReflex initialization. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 433: Smartreflex Initialization Flow Chart
2. For example, if SR_ALWON_FCLK has a frequency of 38.4 MHz, and the target SR_CLK frequency is 100 kHz, SRCLKLENGTH is set to 192 (0x0C0). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 434 SRn.ERRCONFIG[22] VPBOUNDSINTENABLE Enable the VP bounds interrupt. SRn.IRQENABLE_SET[3] MCUACCUMINTENASET Enable the MCU accumulator interrupt. SRn.IRQENABLE_SET[2] MCUVALIDINTENASET Enable the MCU valid interrupt. 434 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 435 3.6.6.5 Voltage Processor Initialization Basic Programming Model Figure 3-97 is a flow chart of the voltage processor initialization. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 436: Voltage Processor Initialization Flow Chart
1. Error-to-voltage converter setting The error-to-voltage converter setting consists of configuring the error offset, error gain, minimum and Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 437 0x0: Mask the VP1 equal-value interrupt. (Default) 0x1: Unmask the VP1 equal-value interrupt. PRCM.PRM_IRQENABLE_MPU[19] VP2_NOSMPSACK_EN 0x0: Mask the VP2 no-SMPS acknowledge. (Default) SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 438 SMPS. It then waits for a command acknowledge from the SMPS before clearing the SmartReflex interrupt. PRCM.PRM_VPn_CONFIG[0] Enable the voltage processor module. VPENABLE Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 439: Voltage Controller Initialization Flow Chart
Set master code in PRM_VC_I2C_CFG MCODE I C in repeated start operation? Clear PRM_VC_I2C_CFG SREN to 0 prcm-UC-008 1. Assign power IC slave addresses. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 440 (F/S) mode. By default, a repeated-start operation for communication is enabled. If necessary, it can be disabled. For more information, see Chapter 17, I Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 441 PRCM.PRM_VC_I2C_CFG[2:0] MCODE Master code for I C HS preamble PRCM.PRM_VC_I2C_CFG[3] HSEN Switch to F/S mode. PRCM.PRM_VC_I2C_CFG[4] SREN Disable repeated start operation. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 442: Smartreflex - Opp Change Flow Chart
(a) Switching from VDDx(Vx,Fx) to (b) Switching from VDDx(Vx,Fx) to VDDy(Vy,Fy) where Fy > Fx VDDy(Vy,Fy) where Fx > Fy prcm-uc-009 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 443 SMPS. The voltage is thus adjusted according to OPPy. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 444 In this case, the SmartReflex module is disabled and the voltage processor is configured to initiate the OPP transition. Figure 3-100 is the flow chart of the OPP change. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 445: Voltage Processor - Opp Change Flow Chart
NOTE: In the following steps, VPn refers to VP1 if VDD1 OPP is changed, and to VP2 if VDD2 OPP is changed. 1. Disable the modules. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 446 Similarly, the wake-up event at the end of the off time restarts the processor clock and interrupts the processor. To enable the corresponding interrupts, the MPU interrupts mask must be set in PRCM.PRM_IRQENABLE_MPU register. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 447: Overview Of Device/Twl5030 Dvfs Management Architecture
DMA, and the camera, display, graphics, and peripheral power domain subsystems. DPLL3 and DPLL4 provide the clocks to the subsystems of VDD2 voltage domains (see Figure 3-102). SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 448: Vdd1 And Vdd2 Voltage Domain Modules And Clock Sources
SMPS Voltage Output Voltage Step VDD1 0.6 V to 1.45 V 12.5 mV VDD2 0.6 V to 1.45 V 12.5 mV Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 449: Smartreflex Voltage Control Registers In Id5 Register Group
Table 3-93. Data Composition for SmartReflex Voltage Control Registers Function Description Reset Value MODE 0x0: VDDx is in active mode. 0x1: VDDx is in sleep mode. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 450: Device/Twl5030 Smartreflex Dvfs Overview Flow Chart
Switch from VDD2 OPP100 to VDD1 OPP100 to VDD1 OPP50 to VDD2 OPP100 to VDD2 OPP50 Continue the voltage scaling? prcm-094 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 451 The error offset and gain values for the voltage converter are provided after system characterization. PRCM.PRM_VPn_CONFIG[31:24] Depends on the characteristics of the SMPS ERROROFFSET PRCM.PRM_VPn_CONFIG[13:16] ERRORGAIN SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 452 SRn.SRCONFIG[11] SR_EN Enable the SmartReflex module. The valid interrupt of the MPU signals that the voltage has stabilized to within the limits. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 453 2 > f 1, f 2 > f To switch from OPP100 to OPPTM, the domain voltage must be switched before the frequency SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 454 To switch from OPP100 to OPP50, the DPLL3 output divider must be configured to divide the output by 2. Frequency switching must be done before voltage switching. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 455 Configured according to the settings in eFuse. SR2.NVALUERECIPROCAL[19:16] SENNGAIN Section 3.5.6.5.4.5, Parameter Configuration. SR2.NVALUERECIPROCAL[15:8] RNSENP SR2.NVALUERECIPROCAL[7:0] RNSENN SR2.SRCONFIG[9] ERRORGENERATORENABLE Enable the error generator. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 456: Vdd1 And Vdd2 Voltage Control Through Vmode
(ON to OFF, or ON to retention), it deasserts sys_nvmode1 and sys_nvmode2. When the PRCM module detects a device wake-up transition (retention to on, or off to on), it asserts sys_nvmode1 and sys_nvmode2. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 457 VMODE signal state changes. This ensures that the voltages provided by the power IC are stable before switching the device to the desired power state. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 458: Voltage Control Through Vmode Flow Chart
Sys_nvmode1 and sys_nvmode2 automatically toggle Wait for stabilization time VDD1 and VDD2 are set to the desired values prcm-UC-014 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 459: Cm Instance Summary
0x4800 4034 CM_CLKSEL1_PLL_IVA2 0x0000 0040 0x4800 4040 CM_CLKSEL2_PLL_IVA2 0x0000 0044 0x4800 4044 CM_CLKSTCTRL_IVA2 0x0000 0048 0x4800 4048 CM_CLKSTST_IVA2 0x0000 004C 0x4800 404C SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 460 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 461 RESERVED Read returns 0. 0x00000000 ST_IVA2 IVA2 standby status. 0x0: IVA2 sub-system is active. 0x1: IVA2 sub-system is in standby mode. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 462 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 463 PRCM Use Cases and Tips • Switch VDD1 OPPs: [5] [6] [7] [8] PRCM Register Manual • IVA2_CM Register Summary: • IVA2_CM Registers: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 464 Processor Clock Configurations: PRCM Basic Programming Model • CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register): PRCM Register Manual • IVA2_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 465 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 466: Ocp_System_Reg_Cm Register Summary
Table 3-117. Register Call Summary for Register CM_REVISION PRCM Basic Programming Model • Revision Information Registers: PRCM Register Manual • OCP_System_Reg_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 467: Mpu_Cm Register Summary
0x0000 0040 0x4800 4940 CM_CLKSEL2_PLL_MPU 0x0000 0044 0x4800 4944 CM_CLKSTCTRL_MPU 0x0000 0048 0x4800 4948 CM_CLKSTST_MPU 0x0000 004C 0x4800 494C 3.8.1.4.2 MPU_CM Registers SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 468 PRCM Basic Programming Model • CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register): [4] [5] PRCM Register Manual • MPU_CM Register Summary: 468 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 469 Table 3-126. Register Call Summary for Register CM_IDLEST_PLL_MPU PRCM Basic Programming Model • CM_IDLEST_PLL_ <processor_name> (Processor DPLL Idle-Status Register): PRCM Register Manual • MPU_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 470 0x1: DPLL1_FCLK is CORE_CLK divided by 1 0x2: DPLL1_FCLK is CORE_CLK divided by 2 0x4: DPLL1_FCLK is CORE_CLK divided by 4 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 471 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 472 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 473: Core_Cm Register Summary
Table 3-137. CORE_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type (Bits) CM_FCLKEN1_CORE 0x0000 0000 0x4800 4A00 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 474 Write 0s for future compatibility. Read returns 0. EN_HDQ HDQ-1 wire functional clock control. 0x0: HDQ functional clock is disabled 0x1: HDQ functional clock is enabled Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 475 [0] [1] [2] [3] [4] [5] [6] [7] PRCM Basic Programming Model • CM_FCLKEN_ <domain_name> (Functional Clock Enable Register): PRCM Register Manual • CORE_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 476 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 477 0x1: UART 1 interface clock is enabled EN_GPT11 GPTIMER 11 interface clock control. 0x0: GPTIMER 11 interface clock is disabled 0x1: GPTIMER 11 interface clock is enabled SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 478 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 479 0x0: MMC 1 can be accessed. 0x1: MMC 1 cannot be accessed. Any access may return an error. RESERVED Read returns 1. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 480 McBSP 5 idle status. 0x0: McBSP 5 can be accessed. 0x1: McBSP 5 cannot be accessed. Any access may return an error. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 481 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 482 0x0: MMC 2 interface clock is unrelated to the domain state transition. 0x1: MMC 2 interface clock is automatically enabled or disabled along with the domain state transition. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 483 0x0: UART 1 interface clock is unrelated to the domain state transition. 0x1: UART 1 interface clock is automatically enabled or disabled along with the domain state transition. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 484 CORE Power Domain Clock Controls: [0] [1] PRCM Basic Programming Model • CM_AUTOIDLE_ <domain_name> (Autoidle Register): PRCM Register Manual • CORE_CM Register Summary: 484 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 485 0x1: The clock 96 MHz is the DPLL4_M2_CLK divided by 0x2: The clock 96 MHz is the DPLL4_M2_CLK divided by 11:8 RESERVED Write the reset value, read returns reset value. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 486 Controls the clock state transition of the L4 clock domain. 0x0: Automatic transition is disabled 0x1: Reserved 0x2: Reserved 0x3: Automatic transition is enabled. Transition is supervised by the HardWare. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 487 • CM_CLKSTST_ <domain_name> (Clock State Status Register): PRCM Register Manual • CORE_CM Register Summary: 3.8.1.6 SGX_CM Registers 3.8.1.6.1 SGX_CM Register Summary SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 488: Sgx_Cm Register Summary
SGX Power Domain Clock Controls: PRCM Basic Programming Model • CM_FCLKEN_ <domain_name> (Functional Clock Enable Register): PRCM Register Manual • SGX_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 489 Table 3-166. Register Call Summary for Register CM_IDLEST_SGX PRCM Basic Programming Model • CM_IDLEST_ <domain_name> (Idle-Status Register): PRCM Register Manual • SGX_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 490 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 491 [0] [1] [2] PRCM Basic Programming Model • CM_CLKSTCTRL_ <domain_name> (Clock State Control Register): PRCM Register Manual • SGX_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 492: Wkup_Cm Register Summary
0x0000 0010 0x4800 4C10 CM_IDLEST_WKUP 0x0000 0020 0x4800 4C20 CM_AUTOIDLE_WKUP 0x0000 0030 0x4800 4C30 CM_CLKSEL_WKUP 0x0000 0040 0x4800 4C40 3.8.1.7.2 WKUP_CM Registers Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 493 [6] [7] PRCM Use Cases and Tips • Device SmartReflex Initialization: [8] [9] PRCM Register Manual • WKUP_CM Register Summary: [10] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 494 0x0000 0020 Physical Address 0x4800 4C20 Instance WKUP_CM Description WAKEUP domain modules access monitoring.This register is read only and automatically updated. Type Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 495 Table 3-181. Register Call Summary for Register CM_IDLEST_WKUP PRCM Basic Programming Model • CM_IDLEST_ <domain_name> (Idle-Status Register): PRCM Register Manual • WKUP_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 496 WKUP Power Domain Clock Controls: PRCM Basic Programming Model • CM_AUTOIDLE_ <domain_name> (Autoidle Register): PRCM Register Manual • WKUP_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 497: Clock_Control_Reg_Cm Register Summary
0x4800 4D40 CM_CLKSEL2_PLL 0x0000 0044 0x4800 4D44 CM_CLKSEL3_PLL 0x0000 0048 0x4800 4D48 CM_CLKSEL4_PLL 0x0000 004C 0x4800 4D4C CM_CLKSEL5_PLL 0x0000 0050 0x4800 4D50 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 498 This bit allows to power-down or not the DPLL4_M2_CLK path. 0x0: Power-up the DPLL4_M2_CLK path. 0x1: Power-down the DPLL4_M2_CLK path. Writting this bit to 1 will take effect immediatly. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 499 DPLL Clock Path Power Down: [5] [6] [7] [8] [9] [10] • Recalibration: [11] [12] • DPLL Source-Clock Controls: [13] [14] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 500: Register Call Summary For Register Cm_Clken_Pll
DPLL5 control; Other enums: Reserved 0x1: Put the second DPLL5 in low power stop mode 0x7: Enables the DPLL5 in lock mode Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 501 RESERVED Read returns 0. ST_54M_CLK Functional clock 54 MHz activity 0x0: 54MHz clock is not active 0x1: 54MHz clock is active SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 502 0x0: USB HOST 120M_FCLK is not active. 0x1: USB HOST 120M_FCLK is active. ST_PERIPH2_CLK DPLL5 clock activity 0x0: DPLL5 is bypassed. 0x1: DPLL5 is locked. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 503 DPLL Source-Clock Controls: [4] [5] PRCM Basic Programming Model • DPLL Clock Control Registers: PRCM Register Manual • Clock_Control_Reg_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 504 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CORE_DPLL_MULT CORE_DPLL_DIV Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 505 Selection of Func_12M_clk and Func_48M_clk source 0x0: source is the CM_96M_FCLK 0x1: source is sys_altclk RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 506 • DPLLs: [0] [1] PRCM Basic Programming Model • CM_CLKSELn_PLL (DPLL Clock Selection Register): PRCM Register Manual • Clock_Control_Reg_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 507 Table 3-204. Register Call Summary for Register CM_CLKSEL3_PLL PRCM Basic Programming Model • CM_CLKSELn_PLL (DPLL Clock Selection Register): PRCM Register Manual • Clock_Control_Reg_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED DIV_120M Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 509 This bit controls the external output clock activity 0x0: sys_clkout2 is disabled 0x1: sys_clkout2 is enabled RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 510: Dss_Cm Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 511 DSS Power Domain Clock Controls: PRCM Basic Programming Model • CM_ICLKEN_ <domain_name> (Interface Clock Enable Register): PRCM Register Manual • DSS_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 512 0x0: Display Sub-System interface clock is unrelated to the domain state transition. 0x1: Display Sub-System interface clock is automatically enabled or disabled along with the domain state transition. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 513 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CLKSEL_TV CLKSEL_DSS1 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 514 0x1F: TV functional clock is DPLL4 clock divided by 31 0x20: TV functional clock is DPLL4 clock divided by 32 RESERVED Write 0s for future compatibility. Read returns 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 515 Table 3-221. Register Call Summary for Register CM_CLKSEL_DSS PRCM Basic Programming Model • CM_CLKSEL_ <domain_name> (Clock Select Register): PRCM Register Manual • DSS_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 516 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 517 • CM_CLKSTST_ <domain_name> (Clock State Status Register): PRCM Register Manual • DSS_CM Register Summary: 3.8.1.10 CAM_CM Registers 3.8.1.10.1 CAM_CM Register Summary SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 518: Cam_Cm Register Summary
CAM Power Domain Clock Controls: PRCM Basic Programming Model • CM_FCLKEN_ <domain_name> (Functional Clock Enable Register): PRCM Register Manual • CAM_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 519 Table 3-234. Register Call Summary for Register CM_IDLEST_CAM PRCM Basic Programming Model • CM_IDLEST_ <domain_name> (Idle-Status Register): PRCM Register Manual • CAM_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 520 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CLKSEL_CAM Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 521 Table 3-238. Register Call Summary for Register CM_CLKSEL_CAM PRCM Basic Programming Model • CM_CLKSEL_ <domain_name> (Clock Select Register): PRCM Register Manual • CAM_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 522 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 523 • CM_CLKSTST_ <domain_name> (Clock State Status Register): PRCM Register Manual • CAM_CM Register Summary: 3.8.1.11 PER_CM Registers 3.8.1.11.1 PER_CM Register Summary SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 524: Per_Cm Register Summary
0x1: GPIO 2 functional clock is enabled EN_WDT3 WDTIMER 3 functional clock control. 0x0: WDTIMER 3 functional clock is disabled 0x1: WDTIMER 3 functional clock is enabled Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 525 [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] PRCM Basic Programming Model • CM_FCLKEN_ <domain_name> (Functional Clock Enable Register): [15] PRCM Register Manual • PER_CM Register Summary: [16] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 526 0x1: GPTIMER 8 interface clock is enabled EN_GPT7 GPTIMER 7 interface clock control. 0x0: GPTIMER 7 interface clock is disabled 0x1: GPTIMER 7 interface clock is enabled Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 527 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 528 GPTIMER 5 idle status. 0x0: GPTIMER 5 can be accessed. 0x1: GPTIMER 5 cannot be accessed. Any access may return an error. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 529 0x0: UART 4 interface clock is unrelated to the domain state transition. 0x1: UART 4 interface clock is automatically enabled or disabled along with the domain state transition. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 530 0x0: GPTIMER 6 interface clock is unrelated to the domain state transition. 0x1: GPTIMER 6 interface clock is automatically enabled or disabled along with the domain state transition. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 531 PER Power Domain Clock Controls: PRCM Basic Programming Model • CM_AUTOIDLE_ <domain_name> (Autoidle Register): PRCM Register Manual • PER_CM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 532 Table 3-255. Register Call Summary for Register CM_CLKSEL_PER PRCM Basic Programming Model • CM_CLKSEL_ <domain_name> (Clock Select Register): PRCM Register Manual • PER_CM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 533 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 534 • CM_CLKSTST_ <domain_name> (Clock State Status Register): PRCM Register Manual • PER_CM Register Summary: 3.8.1.12 EMU_CM Registers 3.8.1.12.1 EMU_CM Register Summary Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 535: Emu_Cm Register Summary
0x12: EMU_PER_ALWON_CLK is DPLL4 clock divided by 18 0x13: EMU_PER_ALWON_CLK is DPLL4 clock divided by 19 0x14: EMU_PER_ALWON_CLK is DPLL4 clock divided by 20 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 536 0x14: EMU_CORE_ALWON_CLK is DPLL3 clock divided by 0x15: EMU_CORE_ALWON_CLK is DPLL3 clock divided by 0x16: EMU_CORE_ALWON_CLK is DPLL3 clock divided by Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 537 0x0: TRACE source clock is SYS_CLK 0x1: TRACE source clock is EMU_CORE_ALWON_CLK 0x2: TRACE source clock is EMU_PER_ALWON clock 0x3: TRACE source clock is EMU_MPU_ALWON clock SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 538 [0] [1] [2] PRCM Basic Programming Model • CM_CLKSTCTRL_ <domain_name> (Clock State Control Register): PRCM Register Manual • EMU_CM Register Summary: 538 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 539 0x1: The emulation override controls are enabled 18:8 CORE_DPLL_EMU_MULT DPLL3 override multiplier factor (0 to 2047) 0x000 RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 540: Global_Reg_Cm Register Summary
Table 3-273. Global_Reg_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type (Bits) CM_POLCTRL 0x0000 009C 0x4800 529C 3.8.1.13.2 Global_Reg_CM Registers Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 541: Neon_Cm Register Summary
Register Width Address Offset Physical Address Reset Type (Bits) CM_IDLEST_NEON 0x0000 0020 0x4800 5320 CM_CLKSTCTRL_NEON 0x0000 0048 0x4800 5348 3.8.1.14.2 NEON_CM Registers SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 542 0x2: Start a software supervised wake-up transition on the domain 0x3: Automatic transition is enabled. Transition is supervised by the HardWare. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 543: Usbhost_Cm Register Summary
0x0: USBHOST_120M_FCLK is disabled 0x1: USBHOST_120M_FCLK is enabled EN_USBHOST1 USB HOST 48-MHz functional clock control 0x0: USBHOST_48M_FCLK is disabled 0x1: USBHOST_48M_FCLK is enabled SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 544 0x0000 0020 Physical Address 0x4800 5420 Instance USBHOST_CM Description Modules access availability monitoring. This register is read only and automatically updated. Type Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 545 Table 3-289. Register Call Summary for Register CM_AUTOIDLE_USBHOST PRCM Functional Description • USBHOST Power Domain Clock Controls: PRCM Basic Programming Model • CM_AUTOIDLE_ <domain_name> (Autoidle Register): SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 546: Register Call Summary For Register Cm_Autoidle_Usbhost
This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states. Type Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 547 Write 0s for future compatibility. Read returns 0. 0x00000000 CLKACTIVITY_USBHOST Interface clock activity status 0x0: No domain interface clock activity 0x1: Domain interface clock is active SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 548: Prm Instance Summary
PM_PWSTST_IVA2 0x0000 00E4 0x4830 60E4 PM_PREPWSTST_IVA2 0x0000 00E8 0x4830 60E8 PRM_IRQSTATUS_IVA2 0x0000 00F8 0x4830 60F8 PRM_IRQENABLE_IVA2 0x0000 00FC 0x4830 60FC 548 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 549 [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] PRCM Basic Programming Model • RM_RSTCTRL_ <domain_name> (Reset Control Register): [20] PRCM Register Manual • IVA2_PRM Register Summary: [21] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 550 Write 0x0: Status bit unchanged Read 0x1: IVA2 domain has been reset upon IVA2-MMU software reset. Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 551 [7] [8] PRCM Basic Programming Model • RM_RSTST_ <domain_name> (Reset Status Register): [9] [10] PRCM Register Manual • IVA2_PRM Register Summary: [11] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 552 [0] [1] [2] [3] [4] PRCM Basic Programming Model • PM_WKDEP_ <domain_name> (Wake-Up Dependency Register): PRCM Register Manual • IVA2_PRM Register Summary: 552 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 553 0x3: Shared L1 Cache and Flat memory is always ON when domain is ON. 15:12 RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 554 PRCM Basic Programming Model • PM_PWSTCTRL_ <domain_name> (Power State Control Register): [0] [1] [2] [3] [4] PRCM Register Manual • IVA2_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 555 0x3: Shared L1 Cache and Flat memory is ON RESERVED Read returns 0. LOGICSTATEST Logic state status 0x0: IVA2 domain logic is OFF 0x1: IVA2 domain logic is ON SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 556 0x1: Shared L2 Cache and Flat memory was previously in RETENTION 0x2: Reserved 0x3: Shared L2 Cache and Flat memory was previously Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 557 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 558 Write 0s for future compatibility. Read returns 0. 0x00000000 IVA2_DPLL_RECAL_EN DPLL2 recalibration mask 0x0: DPLL2 recalibration event is masked 0x1: DPLL2 recalibration event generates an interrupt Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 559: Ocp_System_Reg_Prm Register Summary
RESERVED Reads returns 0. 0x000000 IP revision 0x10 [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 560 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 561 Write 0x0: Status bit unchanged Read 0x1: Voltage Controller slave address acknowledge error event is true (pending) Write 0x1: Status bit is cleared to 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 562 Write 0x0: Status bit unchanged Read 0x1: Voltage Processor 2 OPP change done event is true (pending) Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 563 Write 0x0: Status bit unchanged Read 0x1: Voltage Processor 1 OPP change done event is true (pending) Write 0x1: Status bit is cleared to 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 564 Read 0x0: Wake-up event is false Write 0x0: Status bit unchanged Read 0x1: Wake-up event is true (pending) Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 565 ABB LDO transaction done mask. dual 0x0: ABB LDO transaction done event is masked. 0x1: ABB LDO transaction done event generates an interrupt. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 566 Voltage Processor 1 transaction done mask. 0x0: Voltage Processor 1 transaction done event is masked 0x1: Voltage Processor 1 transaction done event generates an interrupt Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 567 0x0: End of ON time event is masked 0x1: End of ON time event generates an interrupt RESERVED Write 0s for future compatibility. Reads returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 568: Mpu_Prm Register Summary
0x0000 00DC 0x4830 69DC PM_PWSTCTRL_MPU 0x0000 00E0 0x4830 69E0 PM_PWSTST_MPU 0x0000 00E4 0x4830 69E4 PM_PREPWSTST_MPU 0x0000 00E8 0x4830 69E8 3.8.2.4.2 MPU_PRM Registers Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 569 Write 0x0: Status bit unchanged Read 0x1: MPU domain has been reset upon a global cold reset Write 0x1: Status bit is cleared to 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 570 • Wake-Up Dependencies: PRCM Basic Programming Model • CM_CLKSTCTRL_ <domain_name> (Clock State Control Register): • PM_WKDEP_ <domain_name> (Wake-Up Dependency Register): 570 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 571: Register Call Summary For Register Pm_Wkdep_Mpu
PRCM Basic Programming Model • Event Generator Control Registers: • Event Generator Programming Examples: PRCM Register Manual • MPU_PRM Registers Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 572 Event Generator Control Registers: • Event Generator Programming Examples: [3] [4] PRCM Register Manual • MPU_PRM Registers Register Summary: • MPU_PRM Registers: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 573 0x1: Logic and L1 Cache are retained when domain is in RETENTION state. POWERSTATE Power state control 0x0: OFF state 0x1: RETENTION state 0x2: Reserved 0x3: ON state SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 574 Table 3-337. Register Call Summary for Register PM_PWSTST_MPU PRCM Basic Programming Model • PM_PWSTST_ <domain_name> (Power State Status Register): PRCM Register Manual • MPU_PRM Registers Register Summary: 574 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 575 PM_PREPWSTST_ <domain_name> (Previous Power State Status Register): PRCM Register Manual • MPU_PRM Registers Register Summary: 3.8.2.5 CORE_PRM Registers 3.8.2.5.1 CORE_PRM Register Summary SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 576: Core_Prm Register Summary
Write 0x0: Status bit unchanged Read 0x1: CORE domain has been reset upon a global warm reset Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 577 0x1: McSPI 3 wake-up event is enabled EN_MCSPI2 McSPI 2 wake-up control 0x0: McSPI 2 wake-up is disabled 0x1: McSPI 2 wake-up event is enabled SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 578 • Device Wake-Up Events: PRCM Basic Programming Model • PM_WKEN_ <domain_name> (Wake-Up Enable Register): PRCM Register Manual • CORE_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 579 0x0: McSPI 1 is not attached to the MPU wake-up events group. 0x1: McSPI 1 is attached to the MPU wake-up events group. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 580 0x1: HS OTG USB is attached to the MPU wake-up events group. RESERVED Write 0x8 for future compatibility. Read returns 0x8. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 581 0x0: McSPI 3 is not attached to the IVA2 wake-up events group. 0x1: McSPI 3 is attached to the IVA2 wake-up events group. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 582 0x1: McBSP 1 is attached to the IVA2 wake-up events group. RESERVED Write 0s for future compatibility. Read returns 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 583 Read 0x1: MMC 1 wake-up occurred. Write 0x1: Status bit is cleared to 0. 23:22 RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 584 Read 0x0: UART 1 wake-up did not occur or was masked. Write 0x0: Status bit unchanged Read 0x1: UART 1 wake-up occurred. Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 585 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 586 0x0: Memory block 2 is OFF when domain is in RETENTION state. 0x1: Memory block 2 is retained when domain is in RETENTION state. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 587 This is done by setting the PM_PWSTCTRL_CORE [19:18] MEM2ONSTATE bit field to 0x3 and the PM_PWSTCTRL_CORE [17:16] MEM1ONSTATE bit field to 0x3." SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 588 Table 3-356. Register Call Summary for Register PM_PWSTST_CORE PRCM Basic Programming Model • PM_PWSTST_ <domain_name> (Power State Status Register): PRCM Register Manual • CORE_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 589 Table 3-358. Register Call Summary for Register PM_PREPWSTST_CORE PRCM Basic Programming Model • PM_PREPWSTST_ <domain_name> (Previous Power State Status Register): PRCM Register Manual • CORE_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 590 0x1: USB TLL is attached to the IVA2 wake-up events group. RESERVED Write 0s for future compatibility. Read returns 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 591: Sgx_Prm Register Summary
0x4830 6B58 PM_WKDEP_SGX 0x0000 00C8 0x4830 6BC8 PM_PWSTCTRL_SGX 0x0000 00E0 0x4830 6BE0 PM_PWSTST_SGX 0x0000 00E4 0x4830 6BE4 PM_PREPWSTST_SGX 0x0000 00E8 0x4830 6BE8 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 592 Table 3-367. Register Call Summary for Register RM_RSTST_SGX PRCM Basic Programming Model • RM_RSTST_ <domain_name> (Reset Status Register): PRCM Register Manual • SGX_PRM Register Summary: 592 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 593 Address Offset 0x0000 00E0 Physical Address 0x4830 6BE0 Instance SGX_PRM Description This register controls the SGX domain power state transition. Type SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 594 31:21 RESERVED Read returns 0. 0x000 INTRANSITION Domain transition status 0x0: No transition 0x1: SGX power domain transition is in progress. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 595 PM_PREPWSTST_ <domain_name> (Previous Power State Status Register): PRCM Register Manual • SGX_PRM Register Summary: 3.8.2.7 WKUP_PRM Registers 3.8.2.7.1 WKUP_PRM Register Summary SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 596: Wkup_Prm Register Summary
Reserved for non-GP devices EN_GPT1 GPTIMER 1 wake-up control 0x0: GPTIMER 1 wakeup is disabled 0x1: GPTIMER 1 wake-up event is enabled Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 597 0x0: Smart Reflex 1 is not attached to the MPU wake-up events group. 0x1: Smart Reflex 1 is attached to the MPU wake-up events group. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 598 0x0: Smart Reflex 2 is not attached to the IVA2 wake-up events group. 0x1: Smart Reflex 2 is attached to the IVA2 wake-up events group. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 599 Write 0x1:The status bit is cleared to 0. 15:10 RESERVED Write 0s for future compatibility. Read returns 0. 0x000000 RESERVED Reserved for non-GP devices SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 600: Clock_Control_Reg_Prm Register Summary
Type Register Width Address Offset Physical Address Reset Type (Bits) PRM_CLKSEL 0x0000 0040 0x4830 6D40 PRM_CLKOUT_CTRL 0x0000 0070 0x4830 6D70 600 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 601 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 602: Dss_Prm Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 603 Write 0s for future compatibility. Read returns 0. 0x00000000 EN_DSS DSS Wake-up enable 0x0: DSS wake-up is disabled 0x1: DSS wake-up event is enabled SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 604 Events: [0] [1] [2] PRCM Basic Programming Model • PM_WKDEP_ <domain_name> (Wake-Up Dependency Register): PRCM Register Manual • DSS_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 605 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 606 Table 3-402. Register Call Summary for Register PM_PREPWSTST_DSS PRCM Basic Programming Model • PM_PREPWSTST_ <domain_name> (Previous Power State Status Register): PRCM Register Manual • DSS_PRM Register Summary: 606 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 607: Cam_Prm Register Summary
Read 0x1: CAM domain has been reset following a CAMERA power domain wake-up. Write 0x1: Status bit is cleared to 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 608 0x0: CAM domain is independent of MPU domain wake-up. 0x1: CAM domain is woken-up upon MPU domain wake-up. RESERVED Write 0s for future compatibility. Read returns 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 609 Table 3-409. Register Call Summary for Register PM_PWSTCTRL_CAM PRCM Basic Programming Model • PM_PWSTCTRL_ <domain_name> (Power State Control Register): PRCM Register Manual • CAM_PRM Registers: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 610 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 611: Per_Prm Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 612 Write 0s for future compatibility. Read returns 0. 0x0000 EN_UART4 UART 4 wake-up control 0x0: UART 4 wake-up is disabled 0x1: UART 4 wake-up event is enabled Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 613 0x1: McBSP 4 wake-up event is enabled EN_MCBSP3 McBSP3 wake-up control 0x0: McBSP 3 wake-up is disabled 0x1: McBSP 3 wake-up event is enabled SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 614 0x0: GPIO 4 is not attached to the MPU wake-up events group. 0x1: GPIO 4 is attached to the MPU wake-up events group. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 615 0x0: GPTIMER 2 is not attached to the MPU wake-up events group. 0x1: GPTIMER 2 is attached to the MPU wake-up events group. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 616 0x0: GPIO 6 is not attached to the IVA2 wake-up events group. 0x1: GPIO 6 is attached to the IVA2 wake-up events group. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 617 0x0: GPTIMER 4 is not attached to the IVA2 wake-up events group. 0x1: GPTIMER 4 is attached to the IVA2 wake-up events group. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 618 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 619 Read 0x0: GPTIMER 9 wake-up did not occur or was masked. Write 0x0: Status bit unchanged Read 0x1: GPTIMER 9 wake-up occurred. Write 0x1: Status bit is cleared to 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 620 Read 0x0: McBSP 4 wake-up did not occur or was masked. Write 0x0: Status bit unchanged Read 0x1: McBSP 4 wake-up occurred. Write 0x1: Status bit is cleared to 0. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 621 0x0: PER domain is independent of MPU domain wake-up event. 0x1: PER domain is is woken-up upon MPU domain wake-up event. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 622 0x1: Logic is retained when domain is in RETENTION state. POWERSTATE Power state control 0x0: OFF state 0x1: RETENTION state 0x2: Reserved 0x3: ON state Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 623 Table 3-430. Register Call Summary for Register PM_PWSTST_PER PRCM Basic Programming Model • PM_PWSTST_ <domain_name> (Power State Status Register): PRCM Register Manual • PER_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 624: Emu_Prm Register Summary
Register Width Address Offset Physical Address Reset Type (Bits) RM_RSTST_EMU 0x0000 0058 0x4830 7158 PM_PWSTST_EMU 0x0000 00E4 0x4830 71E4 3.8.2.12.2 EMU_PRM Registers Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 625 Table 3-435. Register Call Summary for Register RM_RSTST_EMU PRCM Basic Programming Model • RM_RSTST_ <domain_name> (Reset Status Register): PRCM Register Manual • EMU_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 626: Global_Reg_Prm Register Summary
PRM_VC_I2C_CFG 0x0000 0038 0x4830 7238 PRM_VC_BYPASS_VAL 0x0000 003C 0x4830 723C PRM_RSTCTRL 0x0000 0050 0x4830 7250 PRM_RSTTIME 0x0000 0054 0x4830 7254 626 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 627 Write 0s for future compatibility. Read is undefined. 0x000 Set the I C slave address value for the first Power IC 0x00 device. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 628 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CMDRA1 RESERVED CMDRA0 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 629: Prm_Vc_Cmd_Val_0
• Sleep Sequences: • Wake-Up Sequences: PRCM Basic Programming Model • Voltage Controller Registers: PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 630: Prm_Vc_Cmd_Val_1
Set the slave address pointer for the second VDD channel (VDD2). 15:5 RESERVED Write 0s for future compatibility. Read is undefined. 0x000 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 631: Prm_Vc_I2C_Cfg
• Voltage Controller Initialization Basic Programming Model: [1] [2] [3] PRCM Use Cases and Tips • Device SmartReflex Initialization: [4] [5] SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 632 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 633 Power-Up Sequence: • Global Warm Reset Sequence: PRCM Basic Programming Model • Reset Management: PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 634 Write 0x0: Status bit unchanged Read 0x1: Global external warm reset occurred. Write 0x1: Status bit is cleared to 0. RESERVED Reserved for non-GP devices. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 635 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 636 PRM_VOLTSETUP (Voltage Setup Time Register): [8] [9] PRCM Use Cases and Tips • Initialization Procedure: [10] PRCM Register Manual • Global_Reg_PRM Register Summary: [11] Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 637 0x1: Syst_clk is external clock / 1 0x2: Syst_clk is external clock / 2 0x3: Reserved RESERVED Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 638 Field Name Description Type Reset 31:18 RESERVED Read is undefined. 0x0000 17:0 OBS_BUS Indicates the current value on the observable bus. 0x00000 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 639 Write 0s for future compatibility. Read returns 0. 0x0000 15:0 OFFSET_TIME Number of 32kHz clock cycles for the OFF mode offset 0x0000 time SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 640 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 641 • PRM_VOLTSETUP (Voltage Setup Time Register): [0] [1] [2] • PRM_VOLTOFFSET (Voltage Offset Register): PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 642 PRCM Use Cases and Tips • Device SmartReflex Initialization: • Switch VDD1 OPPs: [3] [4] [5] [6] PRCM Register Manual • Global_Reg_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 643 PRCM Basic Programming Model • Voltage Processor Registers: • PRM_VP_VSTEPMAX (Voltage Processor Maximum Voltage Step): [1] [2] PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 644 PRCM Basic Programming Model • Voltage Processor Registers: • PRM_VP_VOLTAGE (Voltage Processor Voltage Register): PRCM Register Manual • Global_Reg_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 645 Set the initial voltage level of the SMPS. It must be 0x00 reconfigured before SmartReflex is enabled around a new OPP. RESERVED Write 0s for future compatibility. Read is undefined. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 646 PRCM Basic Programming Model • Voltage Processor Registers: • PRM_VP_VSTEPMIN (Voltage Processor Minimum Voltage Step): PRCM Register Manual • Global_Reg_PRM Register Summary: 646 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 647 PRCM Basic Programming Model • Voltage Processor Registers: • PRM_VP_VLIMITTO (Voltage Processor Voltage Limit and Time-Out): PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 648 PRCM Basic Programming Model • Voltage Processor Registers: • PRM_VP_STATUS (Voltage Processor Status Register): PRCM Register Manual • Global_Reg_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 649 Table 3-504. Register Call Summary for Register PRM_LDO_ABB_SETUP PRCM Functional Description • ABB LDOs Control: PRCM Register Manual • Global_Reg_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 650 PM_WKDEP_NEON 0x0000 00C8 0x4830 73C8 PM_PWSTCTRL_NEON 0x0000 00E0 0x4830 73E0 PM_PWSTST_NEON 0x0000 00E4 0x4830 73E4 PM_PREPWSTST_NEON 0x0000 00E8 0x4830 73E8 650 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 651 Table 3-509. Register Call Summary for Register RM_RSTST_NEON PRCM Basic Programming Model • RM_RSTST_ <domain_name> (Reset Status Register): PRCM Register Manual • NEON_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 652 Write 0s for future compatibility. Read returns 0. 0x00000000 LOGICRETSTATE Logic state when RETENTION 0x1: Logic is always retained when domain is in RETENTION state. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 653 Table 3-515. Register Call Summary for Register PM_PWSTST_NEON PRCM Basic Programming Model • PM_PWSTST_ <domain_name> (Power State Status Register): PRCM Register Manual • NEON_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 654: Usbhost_Prm Register Summary
PM_WKDEP_USBHOST 0x0000 00C8 0x4830 74C8 PM_PWSTCTRL_USBHOST 0x0000 00E0 0x4830 74E0 PM_PWSTST_USBHOST 0x0000 00E4 0x4830 74E4 PM_PREPWSTST_USBHOST 0x0000 00E8 0x4830 74E8 654 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 655 Table 3-520. Register Call Summary for Register RM_RSTST_USBHOST PRCM Basic Programming Model • RM_RSTST_ <domain_name> (Reset Status Register): PRCM Register Manual • USBHOST_PRM Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 656 0x0: USBHOST is not attached to the MPU wake-up events group. 0x1: USBHOST is attached to the MPU wake-up events group. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 657 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 658 CORE domain dependency 0x0: USB HOST domain is independent of CORE domain wake-up. 0x1: USB HOST domain is woken-up upon CORE domain wake-up. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 659 0x1: Logic is always retained when domain is in RETENTION state. POWERSTATE Power state control 0x0: OFF state 0x1: RETENTION state 0x2: Reserved 0x3: ON state SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 660 Table 3-534. Register Call Summary for Register PM_PWSTST_USBHOST PRCM Basic Programming Model • PM_PWSTST_ <domain_name> (Power State Status Register): PRCM Register Manual • USBHOST_PRM Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 661: Sr Instance Summary
SRCONFIG 0x0000 0000 0x480C 9000 0x480C B000 SRSTATUS 0x0000 0004 0x480C 9004 0x480C B004 SENVAL 0x0000 0008 0x480C 9008 0x480C B008 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 662 0x1: Enables the module SENENABLE Sensor module enable 0x0: Disable all sensors 0x1: Enable sensors Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 663: Register Call Summary For Register Srconfig
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 664: Register Call Summary For Register Srstatus
Table 3-544. Register Call Summary for Register SENVAL PRCM Functional Description • SmartReflex Voltage Control: [0] [1] [2] [3] PRCM Register Manual • SR Register Summary: Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 665: Register Call Summary For Register Senmin
Table 3-548. Register Call Summary for Register SENMAX PRCM Functional Description • SmartReflex Voltage Control: [0] [1] [2] [3] PRCM Register Manual • SR Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 666: Register Call Summary For Register Senavg
PRCM Use Cases and Tips • Device SmartReflex Initialization: [8] [9] [10] [11] PRCM Register Manual • SR Register Summary: [12] 666 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 667: Register Call Summary For Register Nvaluereciprocal
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 668 Write 0: Bounds interrupt status is unchanged. Write 1: Bounds interrupt status is cleared. MCUDISABLEACKINTSTATENA Read 0: MCUDisable acknowledge status is unchanged. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 669: Register Call Summary For Register Irqstatus
0: Bounds interrupt generation is disabled/masked. 1: Bounds interrupt generation is enabled. Write mode: 0: No change to bounds interrupt enable. 1: Enable bounds interrupt generation. SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 670 0: Valid interrupt generation is disabled/masked. 1: Valid interrupt generation is enabled. Write mode: 0: No change to valid interrupt enable. Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 671 Table 3-564. Register Call Summary for Register SENERROR_REG PRCM Functional Description • SmartReflex Voltage Control: [0] [1] [2] [3] [4] [5] PRCM Register Manual • SR Register Summary: SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 672: Register Call Summary For Register Errconfig
[17] [18] [19] [20] • Switch VDD2 OPPs: [21] [22] [23] [24] PRCM Register Manual • SR Register Summary: [25] 672 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 673 Public Version PRCM Register Manual www.ti.com SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management Copyright © 2009–2010, Texas Instruments Incorporated...
Page 674 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 675 This chapter describes the microprocessor unit (MPU) subsystem..........................Topic Page ................MPU Subsystem Overview ................MPU Subsystem Integration ............. MPU Subsystem Functional Description ............MPU Subsystem Basic Programming Model SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 676: Mpu Subsystem Overview
® and media extensions – ARM NEON™ core - single instruction, multiple data (SIMD) coprocessor (VFP light + media streaming instructions) – Cache memories MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 677 Emulation features: ICECrusher™, Embedded Trace Macrocell™ ( ETM™). The Cortex-A8 MPU implements an APB (Advanced Peripheral Bus) slave interface that allows access to ETM, ICECrusherCS and debug registers. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 678: Mpu Subsystem Integration Overview
NOTE: Some debug, trace, and emulation features are implemented in the MPU subsystem. Only the clock/reset inputs and power management aspects of these features are listed in this chapter. For details, see the Emulation TRM. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 679: Mpu Subsystem Clocking Scheme
Chapter 3, Power, Reset, and Clock Managment. Table 4-1 summarizes the clocks generated in the MPU subsystem by the MPU DPLL and clock generator. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 680: Mpu Dpll Clock Signals
There are as many reset signals as power domains. For details about power domains, see Section 4.3.2.1. Figure 4-4 shows the reset scheme of the MPU subsystem. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 681: Mpu Subsystem Reset Scheme
CORE power domain reset MPU_PWRON_RST PRCM ICECrusher reset. It is active upon a Cold reset only. EMU_RST PRCM Emulation interconnect reset EMU_RSTPWRON PRCM Emulation modules reset SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 682: Arm Core Key Features
JTAG based debug Supported through DAP Trace support Supported through TPIU External coprocessor Not supported For more information, see the ARM Cortex-A8 Technical Reference Manual. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 683: Mpu Subsystem Clock Signal
It is a power domain reset that also resets the ARM. Table 4-7. MPU Subsystem Reset Signal Signal Name Interface Comments MPU_RST PRCM MPU power domain reset SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 684: Bridge Clock Signals
Signal Name Interface Comments CORE_RST PRCM CORE power domain reset 4.2.4.3 Power Management Chapter 12, Interrupt Controller, and Chapter 3, Power, Reset, and Clock Management. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 685: Mpu Subsystem Power Domain Overview
NEON domain DPLL1_RST MPU DPLL domain INTC CORE_RST Core domain mpu-010 Power management requirements at the device level govern power domains for the MPU subsystem. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 686: Overview Of The Mpu Subsystem Power Domain
Low power bypass Software request (manual) or upon global reset release (auto) Stop low power MPU is RET or OFF (auto) Device is OFF (auto) 686 MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 687: Mpu Retention Modes
(modes 3 and 4) is legal, but would result in improper execution of instructions with referencing data from L2. This combination must not be used. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 688 4-14. For example, a transition from mode 13 to mode 4 is allowed, but the reverse is not true because the L2 RET to OFF is illegal. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 689: Power Mode Allowable Transitions
From For more information about clocks, reset, power management, and wake-up events for the MPU subsystem, see Chapter 3, Power, Reset, and Clock Management. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 690 NOTE: In debug mode, the ICECrusher can prevent the MPU subsystem from entering into IDLE mode. See IceCrusher programming details in the emulation TRM. MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 691 2. Next, follow the reset sequence as described in Section 4.4.3.1, Basic Power-On Reset. 4.4.4 ARM Programming Model For the complete programming model, see the ARM Cortex-A8 Technical Reference Manual. SWPU177N – December 2009 – Revised November 2010 MPU Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 692 MPU Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 693 ................IVA2.2 Subsystem Overview ................IVA2.2 Subsystem Integration ............IVA2.2 Subsystem Functional Description ............. IVA2.2 Subsystem Basic Programming Model ..............IVA2.2 Subsystem Register Manual SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 694: Iva2.2 Subsystem Highlight
IVA2.2 Subsystem Overview www.ti.com IVA2.2 Subsystem Overview The device includes the high-performance Texas Instruments image video and audio accelerator (IVA2.2), based on the TMS320DMC64X+ VLIW digital signal processor (DSP) core. The internal architecture is an assembly of the following components: •...
Page 695 – Host port interface (HPI) for MMU programming and access to IVA2.2 internal memories. Can be synchronous or asynchronous. – System interfaces: clocking, power management SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 696: Iva2.2 Subsystem Integration
Public Version IVA2.2 Subsystem Integration www.ti.com • C-friendly environment (state-of-the-art C-compiler for VLIW architecture) • Texas Instruments low-overhead DSP-BIOS operating system IVA2.2 Subsystem Integration Figure 5-2 shows IVA2.2 subsystem integration in the device. Figure 5-2. IVA2.2 Subsystem Integration Device IVA2.2 subsystem...
Page 697: Iva2.2 Internal Clock
CORE_RST, connected to the IVA2.2 subsystem wake-up generator (WUGEN) module • RET_RST, connected to the subsystem WUGEN retention logic to reset registers that keep their value SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 698: Iva2.2 Subsystem Resets
IVA2.2 to go to IDLE state. In that case, only IVA2_RST1 and/or IVA2_RST2 and/or IVA2_RST3 are applied, depending on which bits are set, and CORE_RST and IVA2_RSTPWRON are never applied. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 699 (see Figure 5-4): • DSP power domain: Everything specified in the IVA2.2 subsystem, except the wake-up generator • CORE power domain: Includes the WUGEN SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 700: Iva2.2 Power Domain
MEMONSTATE and/or MEMRETSTATE bit fields. For a detailed description of power domains and controls in the device, see Chapter 3, Power, Reset, and Clock Management. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 701: Iva2.2 Edma Requests
D_DMA_4 MCBSP3_DMA_TX MCBSP module 3 - transmit request D_DMA_5 MCBSP3_DMA_RX MCBSP module 3 - receive request D_DMA_6 MCBSP4_DMA_TX MCBSP module 4 - transmit request SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 702 DMA requests, and slave port access) when the IVA2.2 is powered down. The WUGEN also handles formatting interrupts from device peripherals to the DSP megamodule INTC. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 703: Iva2.2 Interrupt Management
IDMA channel 1 interrupt 15-27 Reserved N/A (internal) CCMPINT N/A (internal) EDMA TPCC TPCC memory protection interrupt CCINTG N/A (internal) EDMA TPCC TPCC global interrupt SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 704: Tpcc_Er
MCBSP2_IRQ IVA2_IRQ[34] MCBSP2 MCBSP module 2 MCBSP3_IRQ IVA2_IRQ[35] MCBSP3 MCBSP module 3 MCBSP4_IRQ IVA2_IRQ[36] MCBSP4 MCBSP module 4 MCBSP5_IRQ IVA2_IRQ[37] MCBSP5 MCBSP module 5 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 705 All other interrupts are directly managed by the IVA2.2 DSP INTC, and the DSP registers are set. For information about the DSP INTC, see the documents listed in Section 5.3.1.8, Other DSP Reference Documents. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 706: Iva2.2 Subsystem Block Diagram
(UMC), an extended memory controller (EMC), an INTC, and a power-down controller (PDC). Figure 5-8 is a block diagram of the DSP megamodule. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 707: Dsp Megamodule Block Diagram
The C64x+ is an extension of the first C64x DSP section (also named Kelvin). The C64x features the following: • 32-bit fixed-point media processor • VLIW architecture • 8 instructions/cycle, 8 execution units SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 708 Software-programmable allocation of SRAM to cache or memory-mapped SRAM • DMA transfer from/to SRAM • Fair priority-based arbitration between DSP, DMA, and cache controller for access to the SRAM IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 709 The UMC operates to up to 182.5 MHz in the context of the IVA2.2. The UMC always operates at half the frequency of the DSP. CAUTION Clock configurations depend on core voltage, and maximum clock frequencies might not apply to production. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 710 The exception combiner allows the combination of any of the 128 system events to the single exception input of the DSP CPU (see Figure 5-9). IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 711: Dsp Megamodule Intc Block Diagram
IVA2.2 boundary are reserved for future use or are not used by the IVA2.2 subsystem. For information about the DSP core INTC, see the C64x+ DSP documents listed in Section 5.3.1.8, Other DSP Reference Documents. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 712 Where EF[i * 32 + j] = EVTFLAGi[j] and XM[i * 32 + j] = EXPMASKi[j] (i = 0, 1, 2, 3 and j = 0 to 31). The logic is similar to that of the event combiners, except that only one combined event is routed to EXCEP. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 713: Interrupt Selector Block Diagram
This event -> interrupt mapping allows software to define the priority of the event. For more information, see Section 5.4, IVA2.2 Subsystem Basic Programming Model. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 714 TMS320C64x VelociT. • TMS320C64x+ DSP Megamodule Reference Guide (TI literature number SPRU871) describes the C64x+ megamodule peripherals. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 715 TMS320C6000 DSPs, and includes application program examples. • TMS320C64x to TMS320C64x+ CPU Migration Guide application note (TI literature number SPRAA84A) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 716 • Interrupts generated by the EDMA are routed to the DSP INTC. • Power-management handshakes are exchanged between EDMA components and the SYSC module. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 717: Iva2.2 Edma Overview
Parameter RAM (PaRAM entires) holding up to 128 transfer contexts, with the following capabilities: – Ping-pong and circular buffering – Channel chaining – Auto-reloading SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 718: Tpcc Block Diagram
Although it is depicted twice in Figure 5-12, there is only one physical register set for the QDMA to PaRAM set mapping block. For more information, see Table 5-3. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 719: Tpcc_Qer
TPCC_QER[n] En bit is set, it is always treated as a TR synchronization. For more information, see Section 5.4, IVA2.2 Subsystem Basic Programming Model. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 720: Dma/Qdma Channel Mapping And Param Entry
16-bit and 32-bit parameters that correspond to the transfer geometry. For more information about the parameters, see Section 5.3.2.1.1.2, DMA Versus QDMA. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 721 The specific TCC value (6-bit binary value) programmed by the user dictates which bit of the 64-bit CER and/or interrupt pending register (IPR) is used. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 722 5.5, IVA2.2 Subsystem Register Manual. Table 5-4 lists the hardware settings. Figure 5-14 shows the internal structure of the TPTC and its connection to the TPCC. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 723: Tptc Block Diagram
– SBIDX = Source B-dimension index, defines the address offset between starting addresses of each source array – DBIDX = Distant B-dimension index, defines the address offset between starting addresses of each destination array SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 724: Transfer Geometry
Array BCNT iva2-015 NOTE: Many Texas Instruments DMA controllers employ a concept of element size and element indexing. To maintain orthogonality, the concept of element size has been dropped. An element-indexed transfer is logically achieved by programming ACNT to the size of the element and BCNT to the number of elements that must be transferred.
Page 725: Iva2.2 Edma Hardware Parameters
IVA2.2 subsystem. Table 5-4. IVA2.2 EDMA Hardware Parameters Module Parameter IVA2.2 EDMA FIFO size for TC0 256 bytes FIFO size for TC1 128 bytes SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 726: Edma Memory Mapping For The Video Accelerator/Sequencer
0x0008 6BFF Reserved 0x0008 6C00 0x0008 7FFF iVLCD QMEM 0x0008 8000 0x0008 83FF Reserved 0x0008 8400 0x0008 BFFF iVLCD HMEM 0x0008 C000 0x0008 DBFF IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 727 DSP CPU, because it performs its own internal memory-mapping function. For more information, see Chapter 2, Memory Mapping. The IVA2.2 MMU main features are: • 32 entries/fully associative translation lookaside buffer (TLB) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 728: Iva2.2 Mmu Block Diagram
TLB miss. On a TLB miss, the translation table-walking logic automatically retrieves the information from the translation table stored in physical memory and updates the TLB cache. Figure 5-17 shows the TTB structure in detail. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 729: Iva2.2 Mmu Translation Table Hierarchy
For more information about the functionality of the IVA2.2 subsystem MMU module, including interrupts, register descriptions, and programming model, see Chapter 15, Memory Management Units. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 730: Video Accelerator/Sequencer Memory Mapping
Reserved iME registers 0xA 0000 0xA 0FFF Configuration registers iLF registers 0xA 1000 0xA 1FFF Configuration registers Reserved 0xA 2000 0xF 7FFF 344KB Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 731 The SL2 memory interface is composed of two modules: • Bandwidth optimizer (BWO) for video accelerator/sequencer local interface interconnect • Arbiter Figure 5-18 is a block diagram of the SL2 memory interface. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 732: Sl2 Memory Interface Block Diagram
L2 memory. It has two components: • 256b write buffer to gather bursted write data before sending them to the shared L2 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 733 PRCM • Formatting interrupts to DSP megamodule interrupt format Figure 5-19 shows the WUGEN in the IVA2.2 subsystem and its interactions with other submodules. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 734: Iva2.2 Wugen Description
WUGEN module. 5.3.6.1.1 Event Generation Figure 5-20 shows event-generation steps in the WUGEN. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 735: Wugen Event Generation
WUGEN module. These registers are used to mask interrupts and DMA requests. Figure 5-21 shows the mechanism of event masking in the WUGEN module. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 736: Wugen Event Masking
To unmask individual events, write 1 in the WUGEN_MEVTCLR0, WUGEN_MEVTCLR1, or WUGEN_MEVTCLR2 register of the WUGEN module. Figure 5-22 shows the event-mask-clear mechanism in the WUGEN module. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 737: Wugen Event Mask Clear
Generation of the divided clocks to all components of the IVA2.2 subsystem • Synchronization of the IVA2.2 divided clocks and the DSP megamodule internal-divided clocks • PRCM power handshaking SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 738: Sysc Block Diagram
EDMA, video accelerator, sequencer, and DSP megamodule if the user wants to lead some dynamic power aspects. The SYSC module controls the transition to IVA2.2 subsystem standby state and standby signal IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 739 5.3.7.5.2 Power Management The video accelerator/sequencer SYSC controls clock gating for the iLF, iME, iVLCD, and sequencer modules and controls clock division for the sequencer module. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 740: Lsys Input Interrupts
When the user writes 0, there is no effect. 5.3.8 Local Memories The IVA2.2 subsystem integrates three memory controllers under the control of the DSP megamodule: • • • IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 741: Iva2.2 Local Memories Hierarchy
True LRU (pseudo-LRU) CACHEABILITY Always cached Programmable Programmable BUFFERABILITY Always buffered Always buffered WRITE POLICY Always write-back Always write-back ALLOCATION POLICY Read-allocate Read-allocate Read-write-allocate SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 742 For information about global memory mapping of the IVA2.2 subsystem (DSP CPU view or MPU view through the L3 interconnect), see Chapter 2, Memory Mapping. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 743 IVA2.2 internal operation (data error, bus activity error, etc.). For information about error management and the register set that allows error tracing, see Section 5.4.11, Error Identification Process. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 744: Iva2 Boot Mode Configuration
5.4.1.1.3. 0x04 User defined bootstrap mode: Boot loader copies the boot strap into L2 memory and branches to it. See Section 5.4.1.1.4. 0x05 Reserved. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 745: Pdccmd Programmed Value In Idle Boot Mode
0 -> No action will be taken as by default PC bit of all MARi registers is set to 0 0x10 Address of external memory to which boot loader should branch to. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 746: Header Format Used In User Defined Bootstrap Mode
2. The MPU writes a bootstrap sequence in SDRAM at address <BootLoader Physical Address>. This sequence is executable by the DSP CPU and contains only relative address references, so that it is IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 747 (a) The MPU releases the IVA2.2 from the OFF state by programming the PRCM. (b) The MPU sets the clocks back to the IVA2.2. (c) The MPU releases the IVA2.2 from reset. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 748: Iva2 Boot Basic Programming Model
MMU is restored to its exact context before the IVA2.2 is shut off, if this context was saved correctly. Only from this point can the IVA2.2 subsystem work with virtual addresses. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 749: Cache Size Specified By L1Pmode
L1PMODE. Table 5-13. Cache Size Specified by L1PMODE L1PCFG[2:0] L1PMODE Amount of L1P Setting Cache 000b 0 KB (default) 001b SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 750: Cache Size Specified By L1Dmode
2: Write the desired cache mode to the bit field in the configuration cache register (L1DCFG, L1PCFG, and L2CFG). 3: Read back the register to stall the DSP CPU until the mode change completes. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 751: Default Cache Configuration
The L1D cache responds normally to program-initiated cache commands (invalidate, write-back-invalidate mode change). SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 752 If the producer has a cache-based architecture, the producer must initiate a write-back and track IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 753 L2WB = 1; /* ---------------------------------------------------- */ /* Now, spin waiting for operation to complete. */ /* ---------------------------------------------------- */ while ((L2WB & 1) != 0) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 754 /* Write base address of array to Base Address Register.*/ /* Then write length of array, in words, to the Word */ /* Count register. */ /* ---------------------------------------------------- */ L2WBAR = &array[0]; IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 755: Sysc_Licfg0
DDR memory, the read access can be on an SDRC register). The C64x + is uninstalled only after the read following the write-back is complete. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 756 (d) DSP waits for end of DMA transferred: • IPR/IPRH bit update (for polling-scheme) • Interrupt generation (for interrupt-scheme) • CER/CERH bit update (for chaining) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 757 The solid-color copy (SSC) programming example follows: • IDMA1_SOURCE = my32bPattern; // 32b pattern to be replicated • IDMA1_DEST = &myDstTable[0]; // myDstTable aligned on word boundary SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 758: Idma1_Count
– PARAM[LCH#].DSTBIDX: Index between A arrays at destination (from -32,768 to 32,767) – PARAM[LCH#].DSTCIDX: Index between B arrays at destination (from -32,768 to 32,767) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 759 Restarting a logical channel that just received its new context occurs only after a trigger event associated with that logical channel is detected. See Section 5.4.4.6.1, Assigning a Logical Channel to a Trigger Event. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 760 Event queue 0 is used for background, potentially long, not very latency-sensitive, not very critical DMA transfers. • Event queue 1 is used for short, latency-sensitive, or critical (for example, hardware synchronized) DMA transfers. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 761: Sysc_Licfg1
Before starting the transfer, a trigger event must be associated with the logical channel. Three modes trigger a DMA transfer: • Manual trigger (software-synchronized transfers) • Hardware trigger (hardware-synchronized transfers) • Automatic trigger (automatic on-submission transfer start) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 762 Example: /* ---------------------------------------------------- */ /* Associate defined logical channel #0x5 to QDMA #1 */ /* ---------------------------------------------------- */ IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 763: Idma0_Mask
The registers of the physical channels are memory-mapped, primarily to enable, clear, and read status for error interrupts generated by the physical channel. For more information, see Section 5.4.11, Error Identification Process. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 764 For example, to allow IPR to be updated (and possibly an interrupt to be generated) after all LCHi submissions to a physical channel are complete: • PARAM[LCHi].OPT.TCC = intEvtx; // intEvtx: IPR bit to be updated • PARAM[LCHi].OPT.TCINTEN = 1 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 765 (b) Clear bit for serviced INT. 4. Read IPR. (a) If TPCC_IPR = 0, exit ISR. (b) If TPCC_IPR = 1, go to Step 3. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 766 EFSDW: Send double word EFCMD Send Command to EFI EFCMD (.unit) ucst10 Syntax: .unit = .S1, .S2, .M1, .M2 C64x+ CPU only Compatibility: .S Unit Opcode: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 767 Single-cycle Instruction type: Delay slots: EFRDW Receive Double Word From EFI EFRDW (.unit) dst_o:dst_e Syntax: .unit = .S1, .S2 C64x+ CPU only Compatibility: Opcode: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 768 CPU to stall before the EFRDW instruction reaches E1 if the data to be read has not yet been registered in the CPU. Execution: if(.S1) A_EFI_Din[31:0] → dst (A0 – A31) else // .2 B_EFI_Din[31:0] → dst (B0 – B31) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 769 Delay slots: EFSW See also: EFSW Send Word to EFI EFSW (.unit) src1, dst Syntax: .unit = .L1, .L2 C64x+ CPU only Compatibility: Opcode: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 770 NOTE: To avoid handling specific cases of successive read requests, interrupts are disabled between the time the EFSW is issued and the data is retrieved in the DSP register. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 771 NOTE: The address is stored in the even 32-bit register of the 64-bit register pair, while value_32b is stored in the odd register (that is, the MSB part). SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 772: Ilf_Commandreg
In the flow chart, the four units (DSP, EDMA, sequencer, and coprocessor) work in parallel. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 773: Ime/Ilf Typical Use Flow Chart
L2 memory, so all data must be transferred to its memory through external means. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 774: Ivlcd Typical Use Flow Hart
Set VLCD_START[0] GO bit to 0x1 to start the iVLCD computation iVLCD Interrupt received DMAed processed data End iVLCD processing into DSP memory iva2-039 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 775 64 elements are encoded. N must be specified to the encoder by setting the corresponding bits in the iVLCD control registers. Programming the VLC involves two steps: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 776 For a complete description of this register, see Section 5.5, IVA2.2 Subsystem Register Manual. • IVA.VLCD_MPEG_CBP MPEG coded block pattern register: Specifies which 8x8 blocks of each IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 777: Vlcd_Mpeg_Cbp
Because the iVLCD reads a codeword from the MSB to the LSB, this register is generally set to 15 at the beginning. After each run, the iVLCD updates the SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 778 CBP value, which is stored along the bitstream in a header section. In JPEG mode, this register is ignored and every block is decoded. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 779: Ivlcd List Of Register Values For Standard Algorithms
IVA.CAVLC_BITPTR: This register resets the first call of the CAVLC function. Set the number of MSB bits to be included in the valid bitstream in the stream word register. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 780: Cavlc_Bitptr
Figure 5-29 shows the IVA2.2 subsystem interrupt flow with the main WUGEN and IC registers used for event generation. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 781: Iva2.2 Interrupt Flow
NOTE: The CSR/TCR, IER, IFR, and ICR registers belong to the DSP CPU block (C64x+). For more information, see the C64x+ documentation (Section 5.3.1.8). SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 782 ID of the CPU interrupt and the system event number of the dropped event. By setting the IVA_IC.INTXCLR[0] CLEAR bit to 1, the software user resets the IVA_IC.INTXSTAT register to 0. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 783: Wugen_Mevt0
Noncombined events can be lost after power on wakeup of the DSP megamodule module. To avoid this, one solution is to replay the DSP CPU interrupt after restoring the interrupt selector and event combiner context. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 784 – In case of warm power-on reset (the CORE power domain was in ACTIVE state), the WUGEN_MEVT0 WUGEN_MEVT1 registers value is the previous programmed one, enabling only wake-up interrupts. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 785 5. Restore the IVA2.2 context (except saved return-PC). 6. Globally enable the interrupts by setting the DSP CPU TSR[0] or CSR[0] GIE bit to 1. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 786 (c) Clear the interrupt at the DSP interrupt controller (if combined interrupt is used, see Section 5.4.8.2, Event Combined Programming Sequence, for details) (d) Service the interrupt event 3. Acknowledge the interrupt to the processor IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 787: Process Of Identifying Source Event Of An Interrupt
If set? GENEITEVENTLOG SEQ _IRQSTATE iME_IRQSTATUS ENDPGMEVENTLOG iLF _IRQSTATUS iVLCD iVLCD _IRQSTATUS SEQ _ERR SEQ _IA_AGENT_STATUS DMA_ERR DMA_IA_AGENT_STATUS HOST_MBX GEM_IC_EVTFLAG 3 TPCC_IPR* TCERRINT* TPTC_IPR* iva2-041 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 788: L1P Memory Protection Registers
L1PMPPA 16 0x00E0 0000 – 0x00E0 07FF Region 1 32KB (flat/cache RAM) Page size = 2KB L1PMPPA 31 0x00E0 7800 – 0x00E0 7FFF iva2-042 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 789: L1D Memory Protection Registers
L2MPPA 63 0x107F F000 – 0x107F FFFF iva2-044 NOTE: When memory is used as cache, all its corresponding MPPA registers should be set to 0x0000. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 790: Iva2.2 Megamodule Memory Protection
0x007F C000 - 0x007F CFFF 0x007F D000 - 0x007F DFFF 0x007F E000 - 0x007F EFFF N/A = nonmapped memory. All corresponding registers should be considered reserved. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 791 The DSP megamodule memory protection model allows control of read, write, and execute permissions independently for both user and supervisor mode. This results in the 6-bit permission field shown in Table 5-21. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 792: Request-Type Access Controls
– PMC_CMPA (EVT120) and PMC_DMPA (EVT121) are generated in case of CPU and DMA memory protection faults, respectively, on PMC. – DMC_CMPA (EVT122) and DMC_DMPA (EVT123) are generated in case of CPU and DMA IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 793 McBSP-type peripheral (typically programmed as the highest priority transfer for sDMA requests) can interrupt the DSP CPU transfers on a nearly immediate basis. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 794 IVA_TPCC.QUEPRI register. The SDMAARB[5:0] MAXWAIT field does not affect only the EMC (IVA_IDMA.SDMAARBE register), but also the UMC (IVA_UMC.SDMAARBU register) and the DMC (IVA_DMC.SDMAARBD register). IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 795 ARM968 program must be DMAed in from memory (possibly SL2, as DMA accesses are bursted). 5.4.9.3.3 SL2 Illegal Accesses It is illegal for the user to generate unaligned bursts that span SL2 address range boundaries. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 796 These software resets map to the PRCM.RM_RSTCTL_IVA2[0] RST1_IVA2 bit, the RM_RSTCTRL_IVA2[1] RST2_IVA2 bit, and the PRCM.RM_RSTCTL_IVA2[2] RST3_IVA2 bit, respectively, in the PRCM register RM_RSTCTRL_IVA2. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 797 5.4.8, Interrupt Management. • Programming sequence for transition to power-off state: Before executing the IDLE instruction, the user must perform the sequence shown in Figure 5-34. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 798: Iva2 Power Off
The user must also ensure that no other instruction is executed parallel to the IDLE instruction. When IVA2 is ready to go to off mode, there are two ways to completely shut down IVA2 subsystem (see Figure 5-35): IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 799: Iva2 Power Down
When the IVA2 is shut down, it can be waked up by an external event. The boot code executed after wakeup must include at least the following steps (see Figure 5-36): SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 800: Iva2 Wake Up
After this sequence, the user must not access the L2 memory. If this happens (typically in code under debug), a memory-protection interrupt and/or exception is taken. The sequence to exit L2$ off mode (while DSP is active) follows: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 801 Check whether the module has dependencies with other modules. • Poll the status register in the module to determine whether the module is active. CAUTION Invalid configuration of VIDEOSYSC_CLKCTL causes unpredictable results. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 802 Queue threshold error events (stored in the TPCC_CCERR[n] QTHRXCDn bit, n = {0,1}] When an error is detected, the CCERRINT event is asserted, because error events do not have enables. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 803: Tpcc_Eeval
– // DMA 2D burst optimization – SYSC.SYSC_LICFG0.DMA2DOPTEN = 1 NOTE: If the preceding condition is not set accurately, setting the DMA2DOPTEN optimization can degrade performance. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 804: Instance Summary
5.5.1 IC Registers This section provides information about the IC Module. Each register in the module is described in Table 5-24 through Table 5-46. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 805: Ic Register Summary
Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem: [12] [13] [14] IVA2.2 Subsystem Register Manual • IC Register Mapping Summary: [15] SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 806: Register Call Summary For Register Evtseti
IVA2.2 Subsystem Functional Description • INTC: [0] [1] IVA2.2 Subsystem Basic Programming Model • Event Combined Programming Sequence: IVA2.2 Subsystem Register Manual • IC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 807: Register Call Summary For Register Evtmaski
Table 5-33. Register Call Summary for Register MEVTFLAGi IVA2.2 Subsystem Basic Programming Model • Event Combined Programming Sequence: [0] [1] [2] [3] IVA2.2 Subsystem Register Manual • IC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 808: Register Call Summary For Register Expmaski
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INTSEL(j*4+3) INTSEL(j*4+2) INTSEL(j*4+1) INTSEL(j*4) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 809: Register Call Summary For Register Intmuxj
Write 0s for future compatibility. 0x0000 Read returns 0. DROP Dropped event flag 0: No events dropped 1: Event was dropped by the CPU SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 810: Register Call Summary For Register Intxstat
IDM10 Dropped event mask for CPU interrupt #10 IDM9 Dropped event mask for CPU interrupt #9 IDM8 Dropped event mask for CPU interrupt #8 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 811: Register Call Summary For Register Intdmask
EA1 = 1: EVTOUT1 pulsed high for 4 clk1 cycles, then low. MXF0 Event Assert output #0 EA0 = 0: No effect EA0 = 1: EVTOUT0 pulsed high for 4 clk1 cycles, then low. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 812: Register Call Summary For Register Evtasrt
Public Version IVA2.2 Subsystem Register Manual www.ti.com Table 5-47. Register Call Summary for Register EVTASRT IVA2.2 Subsystem Register Manual • IC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 813: Sys Register Summary
Determines the RAM sleep modes used by the UMC for powering-down L2 pages. 0x0: No sleep mode supported 0x1: Sleep mode 1 Write 0x2: Sleep mode 2 - equivalent to sleep mode 1 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 814: Register Call Summary For Register Pdccmd
• Power-Down and Wake-Up Management: [4] [5] [6] [7] [8] [9] [10] [11] [12] IVA2.2 Subsystem Register Manual • SYS Register Mapping Summary: [13] IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 815: Register Call Summary For Register Revid
Physical implementation of DSP megamodule version 0x0000 Table 5-52. Register Call Summary for Register REVID IVA2.2 Subsystem Register Manual • SYS Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 816: Idma Register Summary
CPU and there is already an active transfer in progress (ACTV = 1) and cleared when the transfer becomes active. PEND = 1: Transfer is pending PEND = 0: No pending transfer IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 817 M21 = 0: Register access permitted (not masked) Register Mask bit: M20 = 1: Register access blocked (masked) M20 = 0: Register access permitted (not masked) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 818 M1 = 0: Register access permitted (not masked) Register Mask bit: M0 = 1: Register access blocked (masked) M0 = 0: Register access permitted (not masked) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 819 Table 5-61. Register Call Summary for Register IDMA0_DEST IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: IVA2.2 Subsystem Register Manual • IDMA Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 820 ACTV = 0: No active transfer Table 5-65. Register Call Summary for Register IDMA1_STAT IVA2.2 Subsystem Register Manual • IDMA Register Mapping Summary: 820 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 821 Table 5-69. Register Call Summary for Register IDMA1_DEST IVA2.2 Subsystem Basic Programming Model • Internal Memory-to-Memory Transfer (IDMA): [0] [1] [2] [3] IVA2.2 Subsystem Register Manual • IDMA Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 822 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Reserved MAXWAIT IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 823: Register Call Summary For Register Cpuarbe
Maximum wait of 8 cycles (1/9 = 11% access) 0x10: Maximum wait of 16 cycles (1/17 = 6% access) 0x20: Maximum wait of 32 cycles (1/33 = 3% access) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 824: Register Call Summary For Register Idmaarbe
Write 0s for future compatibility. 0x0000 Read returns 0. 18:16 Priority 0x0: Highest priority 0x1: 2nd highest priority 0x2: 3rd highest priority 0x3: 4th highest priority IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 825: Register Call Summary For Register Mdmaarbe
Write 0s for future compatibility. 0x0000 Read returns 0. 15:8 FLTID Faulted ID: 0x00 VBUS PrivID of faulting requestor. This field is valid only if LE is zero. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 826: Register Call Summary For Register Icfgmpfsr
0x1: MDMA Read Status Error detected 0x2: MDMA Write Status Error detected 0x3: CFG Read Status Error detected 0x4: CFG Write Status Error detected IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 827: Register Call Summary For Register Ibuserr
Table 5-89. Register Call Summary for Register IBUSERRCLR IVA2.2 Subsystem Basic Programming Model • Error Reporting for IDMA Module: IVA2.2 Subsystem Register Manual • IDMA Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 828: Xmc Register Summary
0x0184 8000 + (0x4*i) L2MPFAR 0x0000 A000 0x0184 A000 L2MPFSR 0x0000 A004 0x0184 A004 L2MPFCR 0x0000 A008 0x0184 A008 i = 0 to 255 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 829 0x2: L2 cache is bypassed L2MODE L2 Configuration Register 0x0: 0KB of L2 Cache 0x1: 32KB of L2 Cache 0x2: 64KB of L2 Cache SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 830: Register Call Summary For Register L2Cfg
Previous value of the OPER field Read 0x0: L1P cache operates normally Read 0x1: L1P Cache is frozen 15:3 Reserved Write 0s for future compatibility. Read returns 0. 0x0000 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 831: Register Call Summary For Register L1Pcc
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved POPER Reserved OPER SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 832: Register Call Summary For Register L1Dcc
Maximum wait of 8 cycles (1/9 = 11% access) 0x10: Maximum wait of 16 cycles (1/17 = 6% access) 0x20: Maximum wait of 32 cycles (1/33 = 3% access) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 833: Register Call Summary For Register Cpuarbu
Maximum wait of 2 cycles (1/3 = 33% access) 0x4: Maximum wait of 4 cycles (1/5 = 20% access) 0x8: Maximum wait of 8 cycles (1/9 = 11% access) SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 834: Register Call Summary For Register Sdmaarbu
Reserved MAXWAIT Bits Field Name Description Type Reset 31:19 Reserved Write 0s for future compatibility. Read returns 0. 0x0000 18:16 Priority 0x0: Highest priority IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 835: Register Call Summary For Register Cpuarbd
Table 5-112. Register Call Summary for Register IDMAARBD IVA2.2 Subsystem Basic Programming Model • Internal Memory: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 836: Register Call Summary For Register Sdmaarbd
Maximum wait of 8 cycles (1/9 = 11% access) 0x10: Maximum wait of 16 cycles (1/17 = 6% access) 0x20: Maximum wait of 32 cycles (1/33 = 3% access) IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 837: Register Call Summary For Register Ucarbd
Table 5-120. Register Call Summary for Register L2WWC IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 838: Register Call Summary For Register L2Wibar
Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 839: Register Call Summary For Register L2Ibar
Table 5-130. Register Call Summary for Register L1PIBAR IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 840: Register Call Summary For Register L1Piwc
Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 841: Register Call Summary For Register L1Dwiwc
Table 5-140. Register Call Summary for Register L1DWWC IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 842: Register Call Summary For Register L1Dibar
Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 843: Register Call Summary For Register L2Wb
Table 5-148. Register Call Summary for Register L2WBINV IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 844: Register Call Summary For Register L2Inv
Table 5-152. Register Call Summary for Register L1PINV IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: 844 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 845: Register Call Summary For Register L1Dwb
Table 5-156. Register Call Summary for Register L1DWBINV IVA2.2 Subsystem Basic Programming Model • Coherence Maintenance: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 846: Register Call Summary For Register L1Dinv
IVA2.2 Subsystem Basic Programming Model • IVA2.2 Boot Configuration: [0] [1] • External Memory: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: 846 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 847: Register Call Summary For Register L2Mpfar
Table 5-164. Register Call Summary for Register L2MPFSR IVA2.2 Subsystem Basic Programming Model • Internal Memory: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 848: Register Call Summary For Register L2Mpfcr
1: External access is permitted LOCAL 0: DSP megamodule access is not permitted 1: DSP megamodule access is permitted Reserved Write 0s for future compatibility. Read returns 0. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 849: Register Call Summary For Register L2Mppaj
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved FLTID ATYP SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 850: Register Call Summary For Register L1Pmpfsr
Table 5-174. Register Call Summary for Register L1PMPFCR IVA2.2 Subsystem Basic Programming Model • Internal Memory: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 851: Register Call Summary For Register L1Pmppak
Table 5-176. Register Call Summary for Register L1PMPPAk IVA2.2 Subsystem Basic Programming Model • Internal Memory: [0] [1] [2] [3] [4] IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 852: Register Call Summary For Register L1Dmpfar
Table 5-180. Register Call Summary for Register L1DMPFSR IVA2.2 Subsystem Basic Programming Model • Internal Memory: IVA2.2 Subsystem Register Manual • XMC Register Mapping Summary: 852 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 853 0: External access is not permitted 1: External access is permitted LOCAL 0: DSP megamodule access is not permitted 1: DSP megamodule access is permitted SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 854 0x01C0 0308 TPCC_EMCRH 0x030C 0x01C0 030C TPCC_QEMR 0x0310 0x01C0 0310 TPCC_QEMCR 0x0314 0x01C0 0314 i = 0 to 63 j = 0 to 7 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 855: Tpcc_Qwmthra
0x01C0 1078 TPCC_QER 0x1080 0x01C0 1080 TPCC_QEER 0x1084 0x01C0 1084 k = 0 to 15 l = 0 to 1 j = 0 to 7 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 856: Tpcc_Qeecr
0x01C0 4018 + (0x20*m) TPCC_CCNTm 0x401C + (0x20*m) 0x01C0 401C + (0x20*m) n = 0 to 7 n = 0 to 7 m = 0 to 127 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 857 MPEXIST = 1: Memory Protection logic included. CHMAPEXIST Channel Mapping Existence CHMAPEXIST = 0: No Channel mapping. CHMAPEXIST = 1: Channel mapping logic included. 23:22 Reserved Read returns 0. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 858 32 DMA Channels Read 0x5: 64 DMA Channels Table 5-189. Register Call Summary for Register TPCC_CCCFG IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 859 Table 5-193. Register Call Summary for Register TPCC_QCHMAPj IVA2.2 Subsystem Functional Description • EDMA: [0] [1] [2] [3] [4] IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: [5] [6] SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 860 Not applicable for IVA2.2 Reserved Write 0s for future compatibility. Read returns 0. 10:8 DMA Queue Number for event #2 0x0: Event En is queued on Q0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 861 Not applicable for IVA2.2 Reserved Write 0s for future compatibility. Read returns 0. 22:20 DMA Queue Number for event #13 0x0: Event En is queued on Q0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 862 Contains the Event queue number to be used for the corresponding DMA Channel. Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 863 DMA Queue Number for event #16 0x0: Event En is queued on Q0 0x1: Event En is queued on Q1 Others: Not applicable for IVA2.2 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 864 Read returns 0. 10:8 DMA Queue Number for event #26 0x0: Event En is queued on Q0 0x1: Event En is queued on Q1 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 865 Event En is queued on Q0 0x1: Event En is queued on Q1 Others: Not applicable for IVA2.2 Reserved Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 866 Reset Reserved Write 0s for future compatibility. Read returns 0. 30:28 DMA Queue Number for event #47 0x0: Event En is queued on Q0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 867 Event En is queued on Q1 Others: Not applicable for IVA2.2 Table 5-205. Register Call Summary for Register TPCC_DMAQNUM5 IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 868 Event En is queued on Q1 Others: Not applicable for IVA2.2 Reserved Write 0s for future compatibility. Read returns 0. DMA Queue Number for event #49 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 869 Read returns 0. 18:16 DMA Queue Number for event #60 0x0: Event En is queued on Q0 0x1: Event En is queued on Q1 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 870 Event En is queued on Q0 0x1: Event En is queued on Q1 Others: Not applicable for IVA2.2 Reserved Write 0s for future compatibility. Read returns 0. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 871 Event En is queued on Q1 Others: Not applicable for IVA2.2 Table 5-211. Register Call Summary for Register TPCC_QDMAQNUM IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 872 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands. 0x0: Priority 0 - Highest priority IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 873 Event Missed #29 Event Missed #28 Event Missed #27 Event Missed #26 Event Missed #25 Event Missed #24 Event Missed #23 Event Missed #22 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 874 Bits Field Name Description Type Reset Event Missed #63 Event Missed #62 Event Missed #61 Event Missed #60 Event Missed #59 Event Missed #58 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 875 Field Name Description Type Reset Event Missed Clear #31 Event Missed Clear #30 Event Missed Clear #29 Event Missed Clear #28 Event Missed Clear #27 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 876 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bits Field Name Description Type Reset Event Missed Clear #63 Event Missed Clear #62 Event Missed Clear #61 Event Missed Clear #60 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 877 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Bits Field Name Description Type Reset 31:8 Reserved Read returns 0. 0x000000 Event Missed #7 Event Missed #6 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 878 Event Missed Clear #1 Event Missed Clear #0 Table 5-227. Register Call Summary for Register TPCC_QEMCR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 879 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Reserved SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 880 Table 5-233. Register Call Summary for Register TPCC_EEVAL IVA2.2 Subsystem Basic Programming Model • Error Reporting for EDMA Module: IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 881 DMA Region Access enable for Region i, bit #2 DMA Region Access enable for Region i, bit #1 DMA Region Access enable for Region i, bit #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 882 DMA Region Access enable for Region i, bit #35 DMA Region Access enable for Region i, bit #34 DMA Region Access enable for Region i, bit #33 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 883 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved ENUM SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 884 (QER), ENUM will range between 0 and NUM_QDMACH (up to 7). Table 5-243. Register Call Summary for Register TPCC_Q1Ek IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 885 Table 5-245. Register Call Summary for Register TPCC_QSTATl IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 886 Table 5-249. Register Call Summary for Register TPCC_QWMTHRB IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 886 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 887 The ACTV bit must remain high through the life of a TR. ACTV = 0: Channel is idle. ACTV = 1: Channel is busy. Reserved Read returns 0. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 888 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 889 CPU write of 1 to the MPFCLR bit causes any error conditions stored in MPFAR and MPFSR registers to be cleared. CPU write of 0 has no effect. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 890 AIDm = 1: VBus requests with PrivID >= 6 are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR). IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 891 AID3 = 1: VBus requests with PrivID == 3 are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR). SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 892 Table 5-261. Register Call Summary for Register TPCC_MPPAj IVA2.2 Subsystem Basic Programming Model • Internal Memory: [0] [1] [2] [3] [4] IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 893 Table 5-263. Register Call Summary for Register TPCC_ER IVA2.2 Subsystem Functional Description • EDMA: [0] [1] IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 894 Event #2 Event #1 Event #0 Table 5-265. Register Call Summary for Register TPCC_ECR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 894 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 895 Event #35 Event #34 Event #33 Event #32 Table 5-267. Register Call Summary for Register TPCC_ECRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 896 Table 5-269. Register Call Summary for Register TPCC_ESR IVA2.2 Subsystem Functional Description • EDMA: [0] [1] [2] IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: 896 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 897: Register Call Summary For Register Tpcc_Esr
Event #43 Event #42 Event #41 Event #40 Event #39 Event #38 Event #37 Event #36 Event #35 Event #34 Event #33 Event #32 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 898 Event #16 Event #15 Event #14 Event #13 Event #12 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 899 Event #53 Event #52 Event #51 Event #50 Event #49 Event #48 Event #47 Event #46 Event #45 Event #44 Event #43 Event #42 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 900 Event #16 Event #15 Event #14 Event #13 Event #12 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 901 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 902 Event #3 Event #2 Event #1 Event #0 Table 5-281. Register Call Summary for Register TPCC_EESR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 903 Event #3 Event #2 Event #1 Event #0 Table 5-283. Register Call Summary for Register TPCC_SER IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 904 Event #34 Event #33 Event #32 Table 5-285. Register Call Summary for Register TPCC_SERH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 904 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 905 Event #3 Event #2 Event #1 Event #0 Table 5-287. Register Call Summary for Register TPCC_SECR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 906 Event #34 Event #33 Event #32 Table 5-289. Register Call Summary for Register TPCC_SECRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 906 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 907 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-291. Register Call Summary for Register TPCC_IER IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 908 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-293. Register Call Summary for Register TPCC_IERH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 908 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 909 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-295. Register Call Summary for Register TPCC_IECR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 910 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-297. Register Call Summary for Register TPCC_IECRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 910 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 911 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-299. Register Call Summary for Register TPCC_IESR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 912 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-301. Register Call Summary for Register TPCC_IESRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 912 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 913 IVA2.2 Subsystem Basic Programming Model • Starting the Transfer: [0] [1] [2] [3] [4] [5] [6] [7] IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 914 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-305. Register Call Summary for Register TPCC_IPRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 914 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 915 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-307. Register Call Summary for Register TPCC_ICR IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 916 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-309. Register Call Summary for Register TPCC_ICRH IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 916 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 917 Field Name Description Type Reset 31:8 Reserved Read returns 0. 0x000000 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 918 Table 5-315. Register Call Summary for Register TPCC_QEER IVA2.2 Subsystem Functional Description • EDMA: [0] [1] [2] IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 919 31:8 Reserved Write 0s for future compatibility. 0x000000 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 920 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Bits Field Name Description Type Reset 31:8 Reserved Write 0s for future compatibility. 0x000000 Event #7 Event #6 Event #5 Event #4 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 921 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 922 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 923 Event #43 Event #42 Event #41 Event #40 Event #39 Event #38 Event #37 Event #36 Event #35 Event #34 Event #33 Event #32 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 924 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 925 Event #43 Event #42 Event #41 Event #40 Event #39 Event #38 Event #37 Event #36 Event #35 Event #34 Event #33 Event #32 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 926 Event #13 Event #12 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 927 Event #49 Event #48 Event #47 Event #46 Event #45 Event #44 Event #43 Event #42 Event #41 Event #40 Event #39 Event #38 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 928 Event #11 Event #10 Event #9 Event #8 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 929 Event #3 Event #2 Event #1 Event #0 Table 5-341. Register Call Summary for Register TPCC_EECR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 930 Event #3 Event #2 Event #1 Event #0 Table 5-343. Register Call Summary for Register TPCC_EESR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 931 Event #3 Event #2 Event #1 Event #0 Table 5-345. Register Call Summary for Register TPCC_SER_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 932 Event #34 Event #33 Event #32 Table 5-347. Register Call Summary for Register TPCC_SERH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 932 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 933 Event #3 Event #2 Event #1 Event #0 Table 5-349. Register Call Summary for Register TPCC_SECR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 934 Event #34 Event #33 Event #32 Table 5-351. Register Call Summary for Register TPCC_SECRH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 934 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 935 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-353. Register Call Summary for Register TPCC_IER_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 936 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-355. Register Call Summary for Register TPCC_IERH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 936 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 937 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-357. Register Call Summary for Register TPCC_IECR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 938 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-359. Register Call Summary for Register TPCC_IECRH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 938 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 939 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-361. Register Call Summary for Register TPCC_IESR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 940 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-363. Register Call Summary for Register TPCC_IESRH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 940 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 941 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-365. Register Call Summary for Register TPCC_IPR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 942 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-367. Register Call Summary for Register TPCC_IPRH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 942 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 943 Interrupt associated with TCC #1 Interrupt associated with TCC #0 Table 5-369. Register Call Summary for Register TPCC_ICR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 944 Interrupt associated with TCC #33 Interrupt associated with TCC #32 Table 5-371. Register Call Summary for Register TPCC_ICRH_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: 944 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 945 Type Reset 31:8 Reserved Read returns 0. 0x000000 Event #7 Event #6 Event #5 Event #4 Event #3 Event #2 Event #1 Event #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 946 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Bits Field Name Description Type Reset 31:8 Reserved Write 0s for future compatibility. 0x000000 Event #7 Event #6 Event #5 Event #4 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 947 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 948 Event #3 Event #2 Event #1 Event #0 Table 5-385. Register Call Summary for Register TPCC_QSECR_Rn IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 949 Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC. 0x0: FIFO width is 8-bit 0x1: FIFO width is 16-bit 0x2: FIFO width is 32-bit 0x3: FIFO width is 64-bit SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 950 TC will assert error if this is not true. Table 5-389. Register Call Summary for Register TPCC_SRCm IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 951 TC will assert error if this is not true. Table 5-393. Register Call Summary for Register TPCC_DSTm IVA2.2 Subsystem Register Manual • TPCC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 952 AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not CC-thus BCNTRLD is a dont care field. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 953 DCIDX is applied, the current array in anA-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 954 TPTCj_PID 0x000 0x01C1 0000 0x01C1 0400 TPTCj_TCCFG 0x004 0x01C1 0004 0x01C1 0404 TPTCj_TCSTAT 0x100 0x01C1 0100 0x01C1 0500 TPTCj_INTSTAT 0x104 0x01C1 0104 0x01C1 0504 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 955: Tptcj_Errcmd
0x314 + (0x40*i) 0x01C1 0314 + (0x40*i) 0x01C1 0714 + (0x40*i) i = 0 to 3 for TPTC0 i = 0 to 1 for TPTC1 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 956 0x000000 DREGDEPTH Dst Register FIFO Depth Parameterization Read 0x0: 1 entry Read 0x1: 2 entries Depends on the hardware parameters of TPTC0 and TPTC1. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 957 FIFO set is empty. Read 0x1: Dst FIFO contains 1 TR Read 0x2: Dst FIFO contains 2 TR Read 0x3: Dst FIFO contains 3 TR SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 958 PROGEMPTY = 0: Condition not detected. PROGEMPTY = 1: Set when Program Register set transitions to empty state. Cleared when user writes 1 to INTCLR.PROGEMPTY register bit. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 959 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 960 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 961 BUSERR Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0: BUSERR is disabled. ERREN.BUSERR = 1: BUSERR is enabled, andcontributes to the TPTC error interrupt generation. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 962 Table 5-422. Register Call Summary for Register TPTCj_ERRCLR IVA2.2 Subsystem Basic Programming Model • Error Reporting for EDMA Module: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 963 IVA2.2 Subsystem Basic Programming Model • Error Reporting for EDMA Module: [0] [1] [2] [3] [4] IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 964 32 cycles between reads Table 5-428. Register Call Summary for Register TPTCj_RDRATE IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: 964 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 965 0x4: Priority 4 0x5: Priority 5 0x6: Priority 6 0x7: Priority 7 - Lowest Priority Reserved Write 0s for future compatibility. Read returns 0. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 966 B-Dimension count. Number of arrays to be transferred, where each 0x0000 array is ACNT in length. 15:0 ACNT A-Dimension count. Number of bytes to be transferred in first 0x0000 dimension. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 967 (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 968 Table 5-440. Register Call Summary for Register TPTCj_PMPPRXY IVA2.2 Subsystem Functional Description • EDMA: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 969 Destination Address Mode within an array: 0: INCR, Dst addressing within an array increments. 1: FIFO, Dst addressing within an array wraps around upon reaching FIFO width. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 970 Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command isissued. Final value should be 0 when TR is complete. IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 971 (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode. SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 972 Table 5-452. Register Call Summary for Register TPTCj_SAMPPRXY IVA2.2 Subsystem Functional Description • EDMA: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: 972 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 973 Table 5-456. Register Call Summary for Register TPTCj_SASRCBREF IVA2.2 Subsystem Functional Description • EDMA: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 974 (recall that there are BCNT arrays of ACNT bytes) Table 5-460. Register Call Summary for Register TPTCj_DFCNTRLD IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 975 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved FWID SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 976 Table 5-466. Register Call Summary for Register TPTCj_DFOPTi IVA2.2 Subsystem Functional Description • EDMA: [0] [1] [2] [3] IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 977 Table 5-470. Register Call Summary for Register TPTCj_DFCNTi IVA2.2 Subsystem Functional Description • EDMA: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 978 Table 5-474. Register Call Summary for Register TPTCj_DFBIDXi IVA2.2 Subsystem Functional Description • EDMA: IVA2.2 Subsystem Register Manual • TPTC0 and TPTC1 Register Mapping Summary: 978 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 979: Sysc Register Summary
Address Offset Physical Address (Bits) SYSC_REVISION 0x000 0x01C2 0000 SYSC_SYSCONFIG 0x008 0x01C2 0008 SYSC_LICFG0 0x040 0x01C2 0040 SYSC_LICFG1 0x048 0x01C2 0048 SYSC_BOOTADDR 0x100 0x01C2 0100 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 980 IVA2.2 Subsystem Register Manual www.ti.com Table 5-477. SYSC Register Summary (continued) Register Name Type Register Width Address Offset Physical Address (Bits) SYSC_BOOTMOD 0x104 0x01C2 0104 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 981 Table 5-481. Register Call Summary for Register SYSC_SYSCONFIG IVA2.2 Subsystem Basic Programming Model • Clock Management: [0] [1] IVA2.2 Subsystem Register Manual • SYSC Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 982 Transfer: [14] • Recommendations for Static Settings: [15] [16] [17] [18] [19] [20] IVA2.2 Subsystem Register Manual • SYSC Register Mapping Summary: [21] 982 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 983 This is the read-only copy of the CONTROL_IVA2_BOOTADDR when the IVA2 is released fromreset This is an index to a 4K-byte page 11:0 Reserved Read returns 0. 0x000 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 984 IVA2.2 Subsystem Functional Description • Boot Configuration: [0] [1] IVA2.2 Subsystem Basic Programming Model • IVA2.2 Boot: IVA2.2 Subsystem Register Manual • SYSC Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 985: Wugen Register Summary
WUGEN_PENDEVT0 0x090 0x01C2 1090 WUGEN_PENDEVT1 0x094 0x01C2 1094 WUGEN_PENDEVT2 0x098 0x01C2 1098 WUGEN_PENDEVTCLR0 0x100 0x01C2 1100 WUGEN_PENDEVTCLR1 0x104 0x01C2 1104 WUGEN_PENDEVTCLR2 0x108 0x01C2 1108 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 986 Table 5-494. Register Call Summary for Register WUGEN_SYSCONFIG IVA2.2 Subsystem Basic Programming Model • Clock Management: [0] [1] IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 987 Interrupt Mask bit #4 MIRQ3 Interrupt Mask bit #3 MIRQ2 Interrupt Mask bit #2 MIRQ1 Interrupt Mask bit #1 MIRQ0 Interrupt Mask bit #0 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 988 Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem: [3] [4] [5] IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: • WUGEN Register Descriptions: [7] [8] 988 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 989 • Interrupts, DMA Requests, and Event Management: [0] [1] IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: • WUGEN Register Descriptions: [3] [4] SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 990: Wugen_Mevtclr0
MIRQ clear #16 1toSet MIRQCLR15 MIRQ clear #15 1toSet MIRQCLR14 MIRQ clear #14 1toSet MIRQCLR13 MIRQ clear #13 1toSet MIRQCLR12 MIRQ clear #12 1toSet IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 991: Register Call Summary For Register Wugen_Mevtclr0
Bits Field Name Description Type Reset 31:16 Reserved Write 0s for future compatibility. 0x0000 MIRQCLR47 MIRQ clear #47 1toSet MIRQCLR46 MIRQ clear #46 1toSet SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 992: Wugen_Mevt2
1toSet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 993: Register Call Summary For Register Wugen_Mevtclr2
Table 5-506. Register Call Summary for Register WUGEN_MEVTCLR2 IVA2.2 Subsystem Functional Description • Interrupts, DMA Requests, and Event Management: [0] [1] IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 994: Wugen_Mevtset0
MIRQ set #16 1toSet MIRQSET15 MIRQ set #15 1toSet MIRQSET14 MIRQ set #14 1toSet MIRQSET13 MIRQ set #13 1toSet MIRQSET12 MIRQ set #12 1toSet IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 995: Register Call Summary For Register Wugen_Mevtset0
Bits Field Name Description Type Reset 31:16 Reserved Write 0s for future compatibility. 0x0000 MIRQSET47 MIRQ set #47 1toSet MIRQSET46 MIRQ set #46 1toSet SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 996: Register Call Summary For Register Wugen_Mevtset1
1toSet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 997: Register Call Summary For Register Wugen_Mevtset2
Table 5-512. Register Call Summary for Register WUGEN_MEVTSET2 IVA2.2 Subsystem Functional Description • Interrupts, DMA Requests, and Event Management: [0] [1] IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 998 PENDIRQ3 Masked pending interrupt number 3 PENDIRQ2 Masked pending interrupt number 2 PENDIRQ1 Masked pending interrupt number 1 PENDIRQ0 Masked pending interrupt number 0 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...
Page 999 IVA2.2 Subsystem Functional Description • Interrupts, DMA Requests, and Event Management: IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: • WUGEN Register Descriptions: SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem Copyright © 2009–2010, Texas Instruments Incorporated...
Page 1000 IVA2.2 Subsystem Functional Description • Interrupts, DMA Requests, and Event Management: IVA2.2 Subsystem Register Manual • WUGEN Register Mapping Summary: • WUGEN Register Descriptions: 1000 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010 Copyright © 2009–2010, Texas Instruments Incorporated...