Logical Channel Interleaving For Synchronized Transfers; Logical Channel Interleaving On Channel Boundary With The Same Priority - Texas Instruments OMAP5912 Reference Manual

System DMA
3.1.7

Logical Channel Interleaving For Synchronized Transfers

Figure 5.

Logical Channel Interleaving on Channel Boundary With the Same Priority

40 Direct Memory Access (DMA) Support
LCh Types Supporting this Feature LCh Types Supporting this Feature
Logical channel interleaving is a term used when more than one synchronized
channel shares the same physical channel. A synchronized channel is only
active and requesting access to a physical channel when a DMA request is
received.
When a DMA request is served but more data remains to be transmitted, the
logical channel stays enabled waiting for next DMA request. During this time,
the physical channel is released if the LCh-type currently running supports
logical channel interleaving.
A nonsynchronized LCh can use the physical channel as well (i.e., interleave),
but it runs to finish before it releases the channel again. This means it is the
responsibility of the software to configure nonsynchronized transfers in small
enough blocks so that synchronized LChs are served in time. This is true only
if all PCh are occupied.
Figure 5 shows an example of a logical channel interleaving scheme for three
synchronized LChs where the DMA requests are received in order: LCh 0
request, LCh 1 request, and LCh 2 request.
L Ch 0
Logical
channels
L Ch 1
waiting for
service
L Ch 2
It is possible to disable the interleaving on a logical channel basis. If this is done
for a specific logical channel, that logical channel does not release the physical
channel between the DMA requests until all the transfers are done or until the
LCh is disabled by software. This is a way of dedicating a physical channel to
a logical channel of type LCh-P or LCh-PD.
To disable LCh interleave
LCH_INTERLEAVE_DISABLE bit in the logical channel control register,
DMA_LCH_CTRL.
A nonsynchronized transfer is not affected by the LCH_INTERLEAVE_DISABLE
bit in any circumstances. A nonsynchronized transfer always releases the
physical channel between transfers even if it is linked to another LCh using the
logical channel linking feature.
2D P
√
Logical channels serviced
P Ch
L Ch 0, L Ch 1, L Ch 2
for synchronized
PD G D
√
transfers, set the
SPRU755B