Overview - Texas Instruments OMAP5912 Reference Manual

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Overview

SPRU751A
This document describes the clocking mechanisms of the OMAP5912
multimedia processor.
In OMAP5912, various clocks are created from special components such as
the digital phase locked loop (DPLL) and the analog phase-locked loop
(APLL).
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The DPLL converts the input clock (12 MHz–20 MHz) to a high-frequency
clock (200 MHz), which is then distributed within OMAP 3.2 gigacell and
to the various on-chip peripherals.
At power-up reset, the DPLL is in bypass mode and acts as a clock divider.
The desired frequency for the DPLL output clock is achieved by enabling
the DPLL and setting the multiplication and divider ratios.
Note:
At power-up reset, the DPLL, by default, is in divide-by-one mode.
The input clock is provided by an external device or is derived from the on-
chip 12-MHz oscillator. For more details, see Chapter 5, Initialization.
An embedded LDO provides a dedicated power supply to the analog por-
tion of the DPLL to ensure low jitter on the DPLL output clock. The regular
core voltage supplies the wrapper of the DPLL. The OMAP5912 configu-
ration modules control the LDO and observe its state.
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The APLL is a clock multiplier that provides a fixed 96-MHz clock from the
same input clock used to feed the DPLL. The input clock frequency is 12
MHz, 13 MHz, or 19.2 MHz. The APLL is enabled whenever the ULPD
requests a 48-MHz clock. The ULPD_PLL_CTRL_STATUS register is set
to ensure the multiplication factor. The 48-MHz frequency is then achieved
by a divide-by-2 cell in the ULPD.
Figure 1 shows the OMAP5912 global-clocking environment.
Clocks
Clocks 13