Cache Memory Organization - Texas Instruments OMAP5912 Reference Manual

DSP Memory
3.2.1

Cache Memory Organization

24 DSP Subsystem
significantly improve the CPU performance by buffering the instructions most
recently fetched from external memory. The entire external program memory
space is cacheable.
The I-cache total size is 24K bytes divided into three memory banks. Two
8K-byte banks are traditional cache modules. The third module is a special
type of cache called ramset, which is divided into two 4K-byte blocks. Each
block is called ½ ramset. Details of the organization and usage are explained
below. The I-cache can be configured in any the following organizations:
1) Two-way set-associative (two cache modules)
2) Direct-mapped (one cache module)
3) Two-way set-associative and one or two ½ ramset
4) Direct-mapped and one or two ½ ramset
The I-cache can be enabled, disabled, or modified at any time by the
programmer using software control. The TIPB bridge allows access to the
cache configuration registers in the DSP I/O space. At reset the I-cache is
disabled. The user must configure the I-cache to be able to use the ramset.
The initial normal cache hit is a one-wait-state operation. Thereafter, the
I-cache performs a simple branch prediction for cache access (that is, a
branch not taken is always assumed). With this feature, no-branch continuous
fetches are no-wait-state operations. The I-cache returns one 32-bit word for
each fetch. Fetches are always aligned on a 32-bit boundary.
When a cache miss occurs, wait states are inserted that are dependent upon
the external memory access time. The I-cache retrieves instructions from
external memory in a burst of four 32-bit words (to fill cache line). To reduce
the penalty of misses, a streaming feature is implemented where the
instruction word requested by the DSP is sent back as soon as it is retrieved
from external memory, so all four 32-bit words do not have to be loaded into
the cache line first. Additionally, program fetch requests that fall in a cache line
already being retrieved because of a previous miss are serviced as soon as
the word becomes available. This streaming feature can increase the
performance of even non-looping code executing from external memory.
The I-cache supports emulation debug read and breakpoint/watchpoint
insertion by invalidating cache lines with the corresponding data changed in
the external memory space.
The two-way set-associative cache configurations are organized as one or two
8K-byte parallel blocks of memory. The size of the I-cache RAM block and
cache line determines the number of lines in the cache. Each 8K-byte memory
SPRU750A