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Texas Instruments TMS320VC5509 DSP Manuals
Manuals and User Guides for Texas Instruments TMS320VC5509 DSP. We have
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Texas Instruments TMS320VC5509 DSP manuals available for free PDF download: Reference Manual, Data Manual
Texas Instruments TMS320VC5509 Reference Manual (285 pages)
DSP, Multichannel Buffered Serial Port (McBSP)
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.35 MB
Table of Contents
Table of Contents
6
Figures
12
Introduction to the Mcbsp
19
Introduction
19
Key Features of the Mcbsp
19
Block Diagram of the Mcbsp
21
Conceptual Block Diagram of the Mcbsp
21
CLKR Pin
21
Mcbsp Pins
23
Mcbsp Operation
25
Data Transfer Process of a Mcbsp
25
Data Transfer Process for Word Length of 8, 12, or 16 Bits
25
Mcbsp Data Transfer Paths
25
Data Transfer Process for Word Length of 20, 24, or 32 Bits
26
Companding (Compressing and Expanding) Data
27
Companding Formats
27
Companding Processes
27
Capability to Compand Internal Data
28
Μ-Law Transmit Data Companding Format
28
A-Law Transmit Data Companding Format
28
Reversing Bit Order: Option to Transfer LSB First
29
Two Methods by Which the Mcbsp Can Compand Internal Data
29
Clocking and Framing Data
30
Clocking
30
Serial Words
30
Frames and Frame Synchronization
31
Detecting Frame-Sync Pulses, Even in the Reset State
32
Ignoring Unexpected Frame-Sync Pulses
32
Frame Frequency
32
Maximum Frame Frequency
32
Mcbsp Operating at Maximum Packet Frequency
33
Frame Phases
34
Number of Phases, Words, and Bits Per Frame
34
Single-Phase Frame Example
34
Mcbsp Register Bits that Determine the Number of Phases, Words, and Bits Per Frame
34
Dual-Phase Frame Example
35
Single-Phase Frame for a Mcbsp Data Transfer
35
Dual-Phase Frame for a Mcbsp Data Transfer
35
Implementing the AC97 Standard with a Dual-Phase Frame
36
Timing of an AC97-Standard Data Transfer Near Frame Synchronization
37
Mcbsp Reception
38
Mcbsp Reception Physical Data Path
38
Mcbsp Reception Signal Activity
38
Mcbsp Transmission Physical Data Path
40
Mcbsp Transmission Signal Activity
40
Interrupts and DMA Events Generated by a Mcbsp
42
Chapter 3 Sample Rate Generator of the Mcbsp
44
Conceptual Block Diagram of the Sample Rate Generator
45
Sample Rate Generator
45
Clock Generation in the Sample Rate Generator
47
Effects of DLB and CLKSTP on Clock Modes
47
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and
48
Possible Inputs to the Sample Rate Generator and the Polarity Bits
49
Falling Edge
50
Polarity Options for the Input to the Sample Rate Generator
50
Frame Sync Generation in the Sample Rate Generator
52
Synchronizing Sample Rate Generator Outputs to an External Clock
53
CLKG Synchronization and FSG Generation When GSYNC = 1, CLKGDV = 1, and CLKS Provides the Sample Rate Generator Input Clock
54
CLKG Synchronization and FSG Generation When GSYNC = 1, CLKGDV = 3, and CLKS Provides the Sample Rate Generator Input Clock
54
Reset and Initialization Procedure for the Sample Rate Generator
55
Sample Rate Generator Clocking Examples
57
ST-BUS and MVIP Clocking Example
57
Single-Rate Clock Example
58
Double-Rate Clock Example
59
Chapter 4 Mcbsp Exception/Error Conditions
60
Mcbsp Exception/Error Conditions
61
Overrun in the Receiver
62
Overrun in the Mcbsp Receiver
63
Overrun Prevented in the Mcbsp Receiver
63
Unexpected Receive Frame-Sync Pulse
64
An Unexpected Frame-Sync Pulse During a Mcbsp Reception
66
Proper Positioning of Frame-Sync Pulses
66
Data in the Mcbsp Transmitter Overwritten And, Therefore, Not Transmitted
67
Overwrite in the Transmitter
67
Underflow in the Transmitter
68
Underflow During Mcbsp Transmission
69
Underflow Prevented in the Mcbsp Transmitter
69
Possible Responses to Transmit Frame-Sync Pulses
70
Unexpected Transmit Frame-Sync Pulse
70
An Unexpected Frame-Sync Pulse During a Mcbsp Transmission
72
Proper Positioning of Frame-Sync Pulses
72
Chapter 5 Multichannel Selection Modes
74
Configuring a Frame for Multichannel Selection
77
Selection Mode
78
Using Two Partitions
78
Alternating between the Channels of Partition a and the Channels of Partition B
79
Reassigning Channel Blocks Throughout a Mcbsp Data Transfer
80
Receive Channel Assignment and Control When Eight Receive Partitions Are Used
81
Mcbsp Data Transfer in the 8-Partition Mode
82
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used
82
Multichannel Selection
77
Receive Multichannel Selection Mode
83
Selecting a Transmit Multichannel Selection Mode with the XMCM Bits
84
Transmit Multichannel Selection Mode
84
Activity on Mcbsp Pins for the Possible Values of XMCM
86
Using Interrupts between Block Transfers
88
Typical SPI Interface
91
Bits Used to Enable and Configure the Clock Stop Mode
93
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
94
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 0, CLKRP
95
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 0, CLKRP
95
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 1, CLKRP
96
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 1, CLKRP
96
Mcbsp as the SPI Master
99
Bit Values Required to Configure the Mcbsp as an SPI Master
100
Mcbsp as an SPI Slave
102
Bit Values Required to Configure the Mcbsp as an SPI Slave
103
Register Bits Used to Reset or Enable the Mcbsp Receiver
109
Reset State of each Mcbsp Pin
110
Register Bit Used to Set Receiver Pins to Operate as Mcbsp Pins
111
Register Bit Used to Enable/Disable the Digital Loopback Mode
112
Receive Signals Connected to Transmit Signals in Digital Loopback Mode
112
Register Bits Used to Enable/Disable the Clock Stop Mode
113
Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode
114
Register Bit Used to Choose One or Two Phases for the Receive Frame
115
Register Bits Used to Set the Receive Word Length(S)
116
Register Bits Used to Set the Receive Frame Length
118
How to Calculate the Length of the Receive Frame
119
Register Bit Used to Enable/Disable the Receive Frame-Sync Ignore Function
120
Register Bits Used to Set the Receive Companding Mode
121
Register Bits Used to Set the Receive Data Delay
122
Range of Programmable Data Delay
123
Register Bits Used to Set the Receive Sign-Extension and Justification Mode
125
Example: Use of RJUST Field with 12-Bit Data Value 0Xabc
125
Example: Use of RJUST Field with 20-Bit Data Value 0Xabcde
126
Register Bits Used to Set the Receive Interrupt Mode
127
Register Bits Used to Set the Receive Frame Sync Mode
128
The Effect on the FSR Pin
130
Register Bit Used to Set Receive Frame-Sync Polarity
131
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
133
Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
134
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
135
Register Bits Used to Set the Receive Clock Mode
136
Register Bit Used to Set Receive Clock Polarity
139
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
141
Register Bits Used to Set the Sample Rate Generator (SRG) Clock
142
Register Bit Used to Set the SRG Clock Synchronization Mode
144
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
145
Falling Edge
146
Register Bits Used to Set the SRG Input Clock Polarity
146
Register Bits Used to Place Transmitter in Reset
151
Reset State of each Mcbsp Pin
152
Register Bit Used to Set Transmitter Pins to Operate as Mcbsp Pins
153
Register Bits Used to Enable/Disable the Clock Stop Mode
155
Register Bits Used to Enable/Disable Transmit Multichannel Selection
156
Register Bit Used to Choose One or Two Phases for the Transmit Frame
157
Register Bits Used to Set the Transmit Word Length(S)
158
Register Bits Used to Set the Transmit Frame Length
160
How to Calculate Frame Length
161
Register Bit Used to Enable/Disable the Transmit Frame-Sync Ignore Function
162
Register Bits Used to Set the Transmit Companding Mode
163
Register Bits Used to Set the Transmit Data Delay
164
Range of Programmable Data Delay
165
Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
167
DX Delay When DXENA
167
Register Bits Used to Set the Transmit Interrupt Mode
168
Register Bits Used to Set the Transmit Frame-Sync Mode
169
How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses
170
Register Bit Used to Set Transmit Frame-Sync Polarity
171
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
173
Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
174
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
175
Register Bit Used to Set the Transmit Clock Mode
176
How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status
176
Register Bit Used to Set Transmit Clock Polarity
178
Register Bits Used to Set the Sample Rate Generator (SRG) Clock
181
Register Bit Used to Set the SRG Clock Synchronization Mode
183
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
184
Register Bits Used to Set the SRG Input Clock Polarity
185
Register Bits Used to Set the SRG Input Clock Polarity
186
How to Use Mcbsp Pins for General-Purpose I/O
190
Mcbsp Emulation Modes Selectable with the FREE and SOFT Bits of SPCR2
193
Reset State of each Mcbsp Pin
196
Four 8-Bit Data Words Transferred To/From the Mcbsp
203
One 32-Bit Data Word Transferred To/From the Mcbsp
204
Data Receive Registers (DRR1 and DRR2)
209
Data Transmit Registers (DXR1 and DXR2)
210
SPCR1 Bit Descriptions
212
SPCR2 Bit Descriptions
216
Receive Control Registers (RCR1 and RCR2)
220
RCR1 Bit Descriptions
221
RCR2 Bit Descriptions
223
Transmit Control Registers (XCR1 and XCR2)
226
XCR1 Bit Descriptions
227
XCR2 Bit Descriptions
229
Sample Rate Generator Registers (SRGR1 and SRGR2)
232
SRGR1 Bit Descriptions
233
Divide-Down Value
234
SRGR2 Bit Descriptions
235
Multichannel Control Registers (MCR1 and MCR2)
238
MCR1 Bit Descriptions
239
Pin Control Register (PCR)
245
Format of the Receive Channel Enable Registers (RCERA-RCERH)
253
Document Revision History
274
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Texas Instruments TMS320VC5509 Data Manual (124 pages)
Fixed-Point Digital Signal Processor
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1.74 MB
Table of Contents
Table of Contents
5
Section Page
6
TMS320VC5509 Features
11
Introduction
12
Description
12
Pin Assignments
13
2.2.1 Terminal Assignments for the GHH Package
13
Pin Assignments for the GHH Package
14
2.2.2 Pin Assignments for the PGE Package
15
Pin Assignments for the PGE Package
16
Signal Descriptions
17
Functional Overview
30
Block Diagram of the TMS320VC5509
30
Memory
31
On-Chip Dual-Access RAM (DARAM)
31
On-Chip Single-Access RAM (SARAM)
31
DARAM Blocks
31
SARAM Blocks
31
On-Chip Read-Only Memory (ROM)
32
3.1.4 Secure ROM
32
3.1.5 Memory Map
33
TMS320VC5509 Memory Map (PGE Package)
34
TMS320VC5509 Memory Map (GHH Package)
35
3.1.6 Boot Configuration
36
Boot Configuration Summary
36
Peripherals
37
Direct Memory Access (DMA) Controller
37
DMA Channel Control Register (DMA_CCR)
38
DMA_CCR Bit Locations
38
Synchronization Control Function
38
I 2 C Interface
39
Configurable External Buses
40
3.5.1 External Bus Selection Register
40
External Bus Selection Register Bit Field Description
40
3.5.2 Parallel Port
42
TMS320VC5509 Parallel Port Signal Routing
42
3.5.3 Parallel Port Signal Routing
43
3.5.4 Serial Ports
44
Parallel Port (EMIF) Signal Interface
44
TMS320VC5509 Serial Port1 Signal Routing
44
TMS320VC5509 Serial Port2 Signal Routing
44
General-Purpose Input/Output (GPIO) Ports
45
3.6.1 Dedicated General-Purpose I/O
45
I/O Direction Register (IODIR) Bit Layout
45
I/O Direction Register (IODIR) Bit Functions
45
3.6.2 Address Bus General-Purpose I/O
46
I/O Data Register (IODATA) Bit Layout
46
Address/Gpio Enable Register (AGPIOEN) Bit Layout
46
I/O Data Register (IODATA) Bit Functions
46
Address/Gpio Enable Register (AGPIOEN) Bit Functions
46
Address/Gpio Direction Register (AGPIODIR) Bit Layout
47
Address/Gpio Data Register (AGPIODATA) Bit Layout
47
Address/Gpio Direction Register (AGPIODIR) Bit Functions
47
Address/Gpio Data Register (AGPIODATA) Bit Functions
47
3.6.3 EHPI General-Purpose I/O
48
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout
48
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout
48
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions
48
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions
48
System Register
49
EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout
49
EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions
49
Memory-Mapped Registers
50
CPU Memory-Mapped Registers
50
Peripheral Register Description
52
Idle Control, Status, and System Registers
52
External Memory Interface Registers
52
DMA Configuration Registers
53
Real-Time Clock Registers
56
Clock Generator
56
Timers
56
Multichannel Serial Port #0
57
Multichannel Serial Port #1
58
Multichannel Serial Port #2
59
Gpio
60
Device Revision ID
60
I 2 C Module Registers
60
Watchdog Timer Registers
61
MMC/SD1 Module Registers
61
MMC/SD2 Module Registers
62
USB Module Registers
62
Analog-To-Digital Controller (ADC) Registers
64
External Bus Selection Register
64
Secure ROM Register
64
3.10 Interrupts
65
Interrupt Table
65
IFR and IER Registers
66
IFR0 and IER0 Bit Locations
66
IFR0 and IER0 Register Bit Fields
66
Interrupt Timing
67
IFR1 and IER1 Bit Locations
67
IFR1 and IER1 Register Bit Fields
67
Waking up from IDLE Condition
68
Idling Clock Domain When External Parallel Bus Operating in EHPI Mode
68
Documentation Support
69
Device and Development-Support Tool Nomenclature
70
TMS320VC5509 Device Nomenclature
71
Device Nomenclature for the TMS320VC5509
71
Electrical Specifications
72
Absolute Maximum Ratings
72
Recommended Operating Conditions
72
Electrical Characteristics over Recommended Operating Case Temperature Range
74
V Test Load Circuit
75
5−1 Thermal Resistance Characteristics
75
Package Thermal Resistance Characteristics
75
Timing Parameter Symbology
76
Clock Options
77
Internal System Oscillator with External Crystal
77
5−2 Recommended Crystal Parameters
77
5−3 CLKIN Timing Requirements
78
5−4 CLKOUT Switching Characteristics
78
Clock Generation in Bypass Mode (Dpll Disabled)
78
Layout Considerations
78
Bypass Mode Clock Timings
79
5−5 Multiply-By-N Clock Option Timing Requirements
79
5−6 Multiply-By-N Clock Option Switching Characteristics
79
Clock Generation in Lock Mode (Dpll Synthesis Enabled)
79
External Multiply-By-N Clock Timings
80
Real-Time Clock Oscillator with External Crystal
80
5−7 Asynchronous Memory Cycle Timing Requirements
81
5−8 Asynchronous Memory Cycle Switching Characteristics
81
Memory Interface Timings
81
Asynchronous Memory Timings
81
Asynchronous Memory Read Timings
82
Asynchronous Memory Write Timings
83
5−9 Synchronous DRAM Cycle Timing Requirements
84
5−10 Synchronous DRAM Cycle Switching Characteristics [SDRAM Clock = 1X, (1/4)X, and (1/8)X of CPU Clock]
84
Synchronous DRAM (SDRAM) Timings
84
[SDRAM Clock = 1X, (1/4)X, and (1/8)X of CPU Clock]
84
5−11 Synchronous DRAM Cycle Timing Requirements [SDRAM Clock = (1/2)X of CPU Clock]
85
5−12 Synchronous DRAM Cycle Switching Characteristics [SDRAM Clock = (1/2)X of CPU Clock]
85
Three SDRAM Read Commands
86
Three SDRAM WRT Commands
87
SDRAM ACTV Command
88
SDRAM DCAB Command
89
SDRAM REFR Command
90
SDRAM MRS Command
91
Power-Up Reset (On-Chip Oscillator Active) Timings
92
Power-Up Reset (On-Chip Oscillator Inactive) Timings
92
Reset Timings
92
5−13 Power-Up Reset (On-Chip Oscillator Active) Timing Requirements
92
5−14 Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements
92
5−15 Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics
92
5−16 Reset Timing Requirements
93
5−17 Reset Switching Characteristics
93
Warm Reset
93
5−18 External Interrupt Timing Requirements
94
5−19 Wake-Up from IDLE Switching Characteristics
94
External Interrupt Timings
94
Wake-Up from Idle
94
5−20 XF Switching Characteristics
95
XF Timings
95
5−21 GPIO Pins Configured as Inputs Timing Requirements
96
5−22 GPIO Pins Configured as Outputs Switching Characteristics
96
General-Purpose Input/Output (Iox) Signal Timings
96
5−23 TIN/TOUT Pins Configured as Inputs Timing Requirements
97
5−24 TIN/TOUT Pins Configured as Outputs Switching Characteristics
97
Tin/Tout Timings (Timer0 Only)
97
5−25 Mcbsp Transmit and Receive Timing Requirements
98
Multichannel Buffered Serial Port (Mcbsp) Timings
98
Mcbsp Transmit and Receive Timings
98
5−26 Mcbsp Transmit and Receive Switching Characteristics
99
Mcbsp Receive Timings
100
5−27 Mcbsp General-Purpose I/O Timing Requirements
101
5−28 Mcbsp General-Purpose I/O Switching Characteristics
101
Mcbsp General-Purpose I/O Timings
101
5−29 Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 10B, CLKXP = 0)
102
5−30 Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 10B, CLKXP = 0)
102
Mcbsp as SPI Master or Slave Timings
102
Mcbsp Timings as SPI Master or Slave: CLKSTP = 10B, CLKXP = 0
103
5−31 Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 11B, CLKXP = 0)
104
5−32 Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 11B, CLKXP = 0)
104
Mcbsp Timings as SPI Master or Slave: CLKSTP = 11B, CLKXP = 0
104
5−33 Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 10B, CLKXP = 1)
105
5−34 Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 10B, CLKXP = 1)
105
Mcbsp Timings as SPI Master or Slave: CLKSTP = 10B, CLKXP = 1
105
5−35 Mcbsp as SPI Master or Slave Timing Requirements (CLKSTP = 11B, CLKXP = 1)
106
5−36 Mcbsp as SPI Master or Slave Switching Characteristics (CLKSTP = 11B, CLKXP = 1)
106
Mcbsp Timings as SPI Master or Slave: CLKSTP = 11B, CLKXP = 1
106
5−37 EHPI Timing Requirements
107
5−38 EHPI Switching Characteristics
107
Enhanced Host-Port Interface (EHPI) Timings
107
EHPI Nonmultiplexed Read/Write Timings
108
EHPI Multiplexed Memory (HPID) Access Read/Write Timings Without Autoincrement
109
EHPI Multiplexed Memory (HPID) Access Read Timings with Autoincrement
110
EHPI Multiplexed Memory (HPID) Access Write Timings with Autoincrement
111
EHPI Multiplexed Register Access Read/Write Timings
112
5−39 I 2 C Signals (SDA and SCL) Timing Requirements
113
5−40 I 2 C Signals (SDA and SCL) Switching Characteristics
114
5−41 Multimedia Card (MMC) Timing Requirements
115
5−42 Multimedia Card (MMC) Switching Characteristics
115
Multimedia Card (MMC) Timings
115
5−43 Secure Digital (SD) Card Timing Requirements
116
5−44 Secure Digital (SD) Card Switching Characteristics
116
Secure Digital (SD) Card Timings
116
5−45 Universal Serial Bus (USB) Characteristics
117
Universal Serial Bus (USB) Timings
117
Full-Speed Loads
118
5−46 ADC Characteristics
119
ADC Timings
119
Mechanical Data
120
Packaging Information
121
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