External Clock Mode - Texas Instruments OMAP5912 Reference Manual

Dynamic Voltage Scaling
Figure 30. Behavior of LOW_PWR Signal
LOW_POWER
4.1.2

External Clock Mode

Figure 31. Assertion of the LOW_PWR Signal
CLK32K_IN
CK_REF
LOW_PWR
ULPD_STATE Awake state
94 Power Management
ULPD state Awake...
big sleep
1.5 V
VDD
The LOW_PWR signal is used in external clock mode. When active low,
LOW_PWR indicates to external devices that the input system clock (system
clock) can be shut down. It also indicates that the external core voltage supply
can be lowered to 1.1 V to reduce the chip leakage-current consumption.
The LOW_PWR signal is asserted low when the ULPD enters the deep sleep
state (except at power-up reset) and is released upon deep sleep exit (except
at power-up reset). At power-up reset, LOW_PWR is reset to its inactive value
(high). Figure 31 describes the assertion of the signal, and Figure 32
describes the release of the signal.
Sleep sequence
Deep sleep Setup
timer
1.1 V
ULPD setup timer delays deep sleep
to big sleep/awake transition while the
regulator ramps from 1.1 V to 1.5 V.
Deep sleep
Big sleep...
awake
SPRU753A