Power Management User Services; Power Services; Static Clock Management; Dpll1 Clock - Texas Instruments OMAP5912 Reference Manual

Power Management User Services

3 Power Management User Services
3.1

Power Services

3.2

Static Clock Management

3.2.1

DPLL1 Clock

3.2.2

DSP/MPU/TRAFFIC Clocks

72 Power Management
Power services include software and hardware mechanisms that allow the
user to reduce OMAP5912 chip power-consumption during all system phases.
During major system phases, the clocks of each domain can be immediately
validated or reconfigured by software register modification. Each new static
configuration is held until the next control register modifications. This
management is defined as static because no external hardware events are
allowed to modify the last clock tree configuration .
DPLL1 synthesizes a frequency clock from an input clock reference. Each
clock domain can use the DPLL clock or directly clock reference to build each
clock subdomain.
Static management of the DPLL clock allows users to reduce global chip
consumption through one or several clock domain controls.
Action to reduce consumption:
-
Reduce DPLL frequency value (divider register configuration)
Clock domain control through DPLL configuration is done by software writes
to CLKRST register DPPL1_CTL.
See Section 6 for software configuration details.
Static management allows users to reduce global chip consumption through
one or several specific clock subdomain controls.
Actions to reduce consumption:
-
Reduce clock subdomain frequency value (divider register configuration).
-
For each domain that is idled, deactivate the respective clocks (bit register
configuration).
In all cases, software is responsible for determining and managing the effects
of clock modifications on the system (error transitions, performance decrease,
transition delays, and so on).
SPRU753A